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InstcountCI: Update

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Ryan Houdek 2024-07-04 12:18:47 -07:00
parent 1084a031e7
commit 25306cb373
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2 changed files with 40 additions and 24 deletions
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32
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
View File

@ -1684,16 +1684,18 @@
]
},
"rol eax, cl": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"and x20, x5, #0x1f",
"cbz x20, #+0x18",
"cbz x20, #+0x1c",
"neg w20, w5",
"ror w4, w4, w20",
"rmif x4, #63, #nzCv",
"eor w20, w4, w4, lsr #31",
"rmif x20, #0, #nzcV"
"rmif x20, #0, #nzcV",
"b #+0x8",
"mov w4, w4"
]
},
"rol rax, cl": {
@ -1725,15 +1727,17 @@
]
},
"ror eax, cl": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xd3 /1",
"ExpectedArm64ASM": [
"and x20, x5, #0x1f",
"cbz x20, #+0x14",
"cbz x20, #+0x18",
"ror w4, w4, w5",
"rmif x4, #30, #nzCv",
"eor w20, w4, w4, lsr #1",
"rmif x20, #30, #nzcV"
"rmif x20, #30, #nzcV",
"b #+0x8",
"mov w4, w4"
]
},
"ror rax, cl": {
@ -1777,11 +1781,11 @@
]
},
"rcl eax, cl": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 16,
"Comment": "GROUP2 0xd3 /2",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"cbz x20, #+0x34",
"cbz x20, #+0x38",
"lsl w20, w4, w5",
"cset w21, hs",
"neg w22, w5",
@ -1793,7 +1797,9 @@
"lsl w21, w21, w23",
"orr w4, w20, w21",
"eor w20, w4, w22, lsl #31",
"rmif x20, #31, #nzcV"
"rmif x20, #31, #nzcV",
"b #+0x8",
"mov w4, w4"
]
},
"rcl rax, cl": {
@ -1837,11 +1843,11 @@
]
},
"rcr eax, cl": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 16,
"Comment": "GROUP2 0xd3 /3",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"cbz x20, #+0x34",
"cbz x20, #+0x38",
"lsr w20, w4, w5",
"cset w21, hs",
"neg w22, w5",
@ -1853,7 +1859,9 @@
"lsl w21, w21, w22",
"orr w4, w20, w21",
"eor w20, w4, w4, lsr #1",
"rmif x20, #30, #nzcV"
"rmif x20, #30, #nzcV",
"b #+0x8",
"mov w4, w4"
]
},
"rcr rax, cl": {

32
unittests/InstructionCountCI/PrimaryGroup.json
View File

@ -1987,11 +1987,11 @@
]
},
"rol eax, cl": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"and x20, x5, #0x1f",
"cbz x20, #+0x28",
"cbz x20, #+0x2c",
"neg w20, w5",
"ror w4, w4, w20",
"ubfx x20, x4, #0, #1",
@ -2000,7 +2000,9 @@
"eor w20, w4, w4, lsr #31",
"ubfx x20, x20, #0, #1",
"bfi w21, w20, #28, #1",
"msr nzcv, x21"
"msr nzcv, x21",
"b #+0x8",
"mov w4, w4"
]
},
"rol rax, cl": {
@ -2040,11 +2042,11 @@
]
},
"ror eax, cl": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 12,
"Comment": "GROUP2 0xd3 /1",
"ExpectedArm64ASM": [
"and x20, x5, #0x1f",
"cbz x20, #+0x24",
"cbz x20, #+0x28",
"ror w4, w4, w5",
"ubfx x20, x4, #31, #1",
"mrs x21, nzcv",
@ -2052,7 +2054,9 @@
"eor w20, w4, w4, lsr #1",
"ubfx x20, x20, #30, #1",
"bfi w21, w20, #28, #1",
"msr nzcv, x21"
"msr nzcv, x21",
"b #+0x8",
"mov w4, w4"
]
},
"ror rax, cl": {
@ -2104,11 +2108,11 @@
]
},
"rcl eax, cl": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 20,
"Comment": "GROUP2 0xd3 /2",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"cbz x20, #+0x44",
"cbz x20, #+0x48",
"lsl w20, w4, w5",
"cset w21, hs",
"neg w22, w5",
@ -2124,7 +2128,9 @@
"eor w20, w4, w22, lsl #31",
"ubfx x20, x20, #31, #1",
"bfi w24, w20, #28, #1",
"msr nzcv, x24"
"msr nzcv, x24",
"b #+0x8",
"mov w4, w4"
]
},
"rcl rax, cl": {
@ -2176,11 +2182,11 @@
]
},
"rcr eax, cl": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 20,
"Comment": "GROUP2 0xd3 /3",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"cbz x20, #+0x44",
"cbz x20, #+0x48",
"lsr w20, w4, w5",
"cset w21, hs",
"neg w22, w5",
@ -2196,7 +2202,9 @@
"eor w20, w4, w4, lsr #1",
"ubfx x20, x20, #30, #1",
"bfi w24, w20, #28, #1",
"msr nzcv, x24"
"msr nzcv, x24",
"b #+0x8",
"mov w4, w4"
]
},
"rcr rax, cl": {