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Merge pull request #3724 from alyssarosenzweig/ryan-avx-cut

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First few commits from Ryan's AVX branch
This commit is contained in:
Ryan Houdek 2024-06-18 11:39:51 -07:00 committed by GitHub
commit 29f644235d
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GPG Key ID: B5690EEEBB952194
40 changed files with 18696 additions and 18660 deletions
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2
FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp
View File

@ -110,7 +110,7 @@ void Dispatcher::EmitDispatcher() {
add(ARMEmitter::Size::i64Bit, StaticRegisters[X86State::REG_RSP], ARMEmitter::Reg::rsp, 0);
add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, TMP1, 0);
if (EmitterCTX->HostFeatures.SupportsSVE) {
if (EmitterCTX->HostFeatures.SupportsSVE128) {
ptrue(ARMEmitter::SubRegSize::i8Bit, PRED_TMP_16B, ARMEmitter::PredicatePattern::SVE_VL16);
}

157
FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp
View File

@ -97,6 +97,27 @@ static void ClassifyContextStruct(ContextInfo* ContextClassificationInfo, bool S
FEXCore::IR::InvalidClass,
});
// DeferredSignalRefCount
ContextClassification->emplace_back(ContextMemberInfo {
ContextMemberClassification {
offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount),
sizeof(FEXCore::Core::CPUState::DeferredSignalRefCount),
},
LastAccessType::NONE,
FEXCore::IR::InvalidClass,
});
for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) {
ContextClassification->emplace_back(ContextMemberInfo {
ContextMemberClassification {
offsetof(FEXCore::Core::CPUState, avx_high[0][0]) + FEXCore::Core::CPUState::XMM_SSE_REG_SIZE * i,
FEXCore::Core::CPUState::XMM_SSE_REG_SIZE,
},
LastAccessType::NONE,
FEXCore::IR::InvalidClass,
});
}
ContextClassification->emplace_back(ContextMemberInfo {
ContextMemberClassification {
offsetof(FEXCore::Core::CPUState, rip),
@ -117,6 +138,48 @@ static void ClassifyContextStruct(ContextInfo* ContextClassificationInfo, bool S
});
}
ContextClassification->emplace_back(ContextMemberInfo {
ContextMemberClassification {
offsetof(FEXCore::Core::CPUState, _pad),
sizeof(FEXCore::Core::CPUState::_pad),
},
LastAccessType::INVALID,
FEXCore::IR::InvalidClass,
});
if (SupportsSVE256) {
for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) {
ContextClassification->emplace_back(ContextMemberInfo {
ContextMemberClassification {
offsetof(FEXCore::Core::CPUState, xmm.avx.data[0][0]) + FEXCore::Core::CPUState::XMM_AVX_REG_SIZE * i,
FEXCore::Core::CPUState::XMM_AVX_REG_SIZE,
},
LastAccessType::NONE,
FEXCore::IR::InvalidClass,
});
}
} else {
for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) {
ContextClassification->emplace_back(ContextMemberInfo {
ContextMemberClassification {
offsetof(FEXCore::Core::CPUState, xmm.sse.data[0][0]) + FEXCore::Core::CPUState::XMM_SSE_REG_SIZE * i,
FEXCore::Core::CPUState::XMM_SSE_REG_SIZE,
},
LastAccessType::NONE,
FEXCore::IR::InvalidClass,
});
}
ContextClassification->emplace_back(ContextMemberInfo {
ContextMemberClassification {
offsetof(FEXCore::Core::CPUState, xmm.sse.pad[0][0]),
static_cast<uint16_t>(FEXCore::Core::CPUState::XMM_SSE_REG_SIZE * FEXCore::Core::CPUState::NUM_XMMS),
},
LastAccessType::INVALID,
FEXCore::IR::InvalidClass,
});
}
ContextClassification->emplace_back(ContextMemberInfo {
ContextMemberClassification {
offsetof(FEXCore::Core::CPUState, es_idx),
@ -173,8 +236,8 @@ static void ClassifyContextStruct(ContextInfo* ContextClassificationInfo, bool S
ContextClassification->emplace_back(ContextMemberInfo {
ContextMemberClassification {
offsetof(FEXCore::Core::CPUState, _pad),
sizeof(FEXCore::Core::CPUState::_pad),
offsetof(FEXCore::Core::CPUState, _pad2),
sizeof(FEXCore::Core::CPUState::_pad2),
},
LastAccessType::INVALID,
FEXCore::IR::InvalidClass,
@ -234,39 +297,6 @@ static void ClassifyContextStruct(ContextInfo* ContextClassificationInfo, bool S
FEXCore::IR::InvalidClass,
});
if (SupportsSVE256) {
for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) {
ContextClassification->emplace_back(ContextMemberInfo {
ContextMemberClassification {
offsetof(FEXCore::Core::CPUState, xmm.avx.data[0][0]) + FEXCore::Core::CPUState::XMM_AVX_REG_SIZE * i,
FEXCore::Core::CPUState::XMM_AVX_REG_SIZE,
},
LastAccessType::NONE,
FEXCore::IR::InvalidClass,
});
}
} else {
for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) {
ContextClassification->emplace_back(ContextMemberInfo {
ContextMemberClassification {
offsetof(FEXCore::Core::CPUState, xmm.sse.data[0][0]) + FEXCore::Core::CPUState::XMM_SSE_REG_SIZE * i,
FEXCore::Core::CPUState::XMM_SSE_REG_SIZE,
},
LastAccessType::NONE,
FEXCore::IR::InvalidClass,
});
}
ContextClassification->emplace_back(ContextMemberInfo {
ContextMemberClassification {
offsetof(FEXCore::Core::CPUState, xmm.sse.pad[0][0]),
static_cast<uint16_t>(FEXCore::Core::CPUState::XMM_SSE_REG_SIZE * FEXCore::Core::CPUState::NUM_XMMS),
},
LastAccessType::INVALID,
FEXCore::IR::InvalidClass,
});
}
for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_FLAGS; ++i) {
ContextClassification->emplace_back(ContextMemberInfo {
ContextMemberClassification {
@ -337,21 +367,11 @@ static void ClassifyContextStruct(ContextInfo* ContextClassificationInfo, bool S
FEXCore::IR::InvalidClass,
});
// _pad2
// _pad3
ContextClassification->emplace_back(ContextMemberInfo {
ContextMemberClassification {
offsetof(FEXCore::Core::CPUState, _pad2),
sizeof(FEXCore::Core::CPUState::_pad2),
},
LastAccessType::NONE,
FEXCore::IR::InvalidClass,
});
// DeferredSignalRefCount
ContextClassification->emplace_back(ContextMemberInfo {
ContextMemberClassification {
offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount),
sizeof(FEXCore::Core::CPUState::DeferredSignalRefCount),
offsetof(FEXCore::Core::CPUState, _pad3),
sizeof(FEXCore::Core::CPUState::_pad3),
},
LastAccessType::NONE,
FEXCore::IR::InvalidClass,
@ -385,12 +405,21 @@ static void ResetClassificationAccesses(ContextInfo* ContextClassificationInfo,
ContextClassification->at(Offset).AccessOffset = 0;
ContextClassification->at(Offset).StoreNode = nullptr;
};
size_t Offset = 0;
///< InlineJITBlockHeader
SetAccess(Offset++, LastAccessType::INVALID);
///< rip
// DeferredSignalRefCount
SetAccess(Offset++, LastAccessType::INVALID);
for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) {
///< avx_high
SetAccess(Offset++, LastAccessType::NONE);
}
// rip
SetAccess(Offset++, LastAccessType::NONE);
///< gregs
@ -398,6 +427,19 @@ static void ResetClassificationAccesses(ContextInfo* ContextClassificationInfo,
SetAccess(Offset++, LastAccessType::NONE);
}
// pad
SetAccess(Offset++, LastAccessType::NONE);
// xmm
for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) {
SetAccess(Offset++, LastAccessType::NONE);
}
// xmm_pad
if (!SupportsSVE256) {
SetAccess(Offset++, LastAccessType::NONE);
}
// Segment indexes
SetAccess(Offset++, LastAccessType::NONE);
SetAccess(Offset++, LastAccessType::NONE);
@ -406,7 +448,7 @@ static void ResetClassificationAccesses(ContextInfo* ContextClassificationInfo,
SetAccess(Offset++, LastAccessType::NONE);
SetAccess(Offset++, LastAccessType::NONE);
// Pad
// Pad2
SetAccess(Offset++, LastAccessType::INVALID);
// Segments
@ -417,16 +459,6 @@ static void ResetClassificationAccesses(ContextInfo* ContextClassificationInfo,
SetAccess(Offset++, LastAccessType::NONE);
SetAccess(Offset++, LastAccessType::NONE);
///< xmm
for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) {
SetAccess(Offset++, LastAccessType::NONE);
}
if (!SupportsSVE256) {
///< xmm pad if AVX isn't supported.
SetAccess(Offset++, LastAccessType::NONE);
}
///< flags
for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_FLAGS; ++i) {
SetAccess(Offset++, LastAccessType::NONE);
@ -454,10 +486,7 @@ static void ResetClassificationAccesses(ContextInfo* ContextClassificationInfo,
///< AbridgedFTW
SetAccess(Offset++, LastAccessType::NONE);
///< _pad2
SetAccess(Offset++, LastAccessType::INVALID);
///< DeferredSignalRefCount
// pad3
SetAccess(Offset++, LastAccessType::INVALID);
}

21
FEXCore/include/FEXCore/Core/CoreState.h
View File

@ -89,18 +89,27 @@ struct CPUState {
};
uint64_t InlineJITBlockHeader {};
// Reference counter for FEX's per-thread deferred signals.
// Counts the nesting depth of program sections that cause signals to be deferred.
NonAtomicRefCounter<uint64_t> DeferredSignalRefCount;
// The high 128-bits of AVX registers when not being emulated by SVE256.
uint64_t avx_high[16][2];
uint64_t rip {}; ///< Current core's RIP. May not be entirely accurate while JIT is active
uint64_t gregs[16] {};
uint64_t _pad {};
XMMRegs xmm {};
// Raw segment register indexes
uint16_t es_idx {}, cs_idx {}, ss_idx {}, ds_idx {};
uint16_t gs_idx {}, fs_idx {};
uint16_t _pad[2];
uint16_t _pad2[2];
// Segment registers holding base addresses
uint32_t es_cached {}, cs_cached {}, ss_cached {}, ds_cached {};
uint64_t gs_cached {};
uint64_t fs_cached {};
XMMRegs xmm {};
uint8_t flags[48] {};
uint64_t pf_raw {};
uint64_t af_raw {};
@ -113,11 +122,7 @@ struct CPUState {
uint16_t FCW {0x37F};
uint8_t AbridgedFTW {};
uint8_t _pad2[5];
// Reference counter for FEX's per-thread deferred signals.
// Counts the nesting depth of program sections that cause signals to be deferred.
NonAtomicRefCounter<uint64_t> DeferredSignalRefCount;
uint8_t _pad3[5];
// PF/AF are statically mapped as-if they were r16/r17 (which do not exist in
// x86 otherwise). This allows a straightforward mapping for SRA.
static constexpr uint8_t PF_AS_GREG = 16;
@ -161,8 +166,10 @@ struct CPUState {
};
static_assert(std::is_trivially_copyable_v<CPUState>, "Needs to be trivial");
static_assert(std::is_standard_layout_v<CPUState>, "This needs to be standard layout");
static_assert(offsetof(CPUState, avx_high) % 16 == 0, "avx_high needs to be 128-bit aligned!");
static_assert(offsetof(CPUState, xmm) % 32 == 0, "xmm needs to be 256-bit aligned!");
static_assert(offsetof(CPUState, mm) % 16 == 0, "mm needs to be 128-bit aligned!");
static_assert(offsetof(CPUState, gregs[15]) <= 504, "gregs maximum offset must be <= 504 for ldp/stp to work");
static_assert(offsetof(CPUState, DeferredSignalRefCount) % 8 == 0, "Needs to be 8-byte aligned");
struct InternalThreadState;

2
unittests/InstructionCountCI/AFP/SVE256/Secondary.json
View File

@ -25,7 +25,7 @@
"0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"scvtf v16.2s, v2.2s"
]
}

2
unittests/InstructionCountCI/AFP/Secondary.json
View File

@ -26,7 +26,7 @@
"0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"scvtf v16.2s, v2.2s"
]
}

4
unittests/InstructionCountCI/Crypto/H0F3A.json
View File

@ -55,7 +55,7 @@
"0x66 0x0f 0x3a 0xdf"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2176]",
"ldr q2, [x28, #2432]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
@ -68,7 +68,7 @@
"0x66 0x0f 0x3a 0xdf"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2176]",
"ldr q2, [x28, #2432]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",

126
unittests/InstructionCountCI/DDD.json
View File

@ -21,11 +21,11 @@
"0x0f 0x0f 0x0c"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d2, [x28, #1056]",
"uzp1 v2.4h, v2.4h, v2.4h",
"sxtl v2.4s, v2.4h",
"scvtf v2.2s, v2.2s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pi2fd mm0, mm1": {
@ -34,9 +34,9 @@
"0x0f 0x0f 0x0d"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d2, [x28, #1056]",
"scvtf v2.2s, v2.2s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pf2iw mm0, mm1": {
@ -45,11 +45,11 @@
"0x0f 0x0f 0x1c"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d2, [x28, #1056]",
"fcvtzs v2.2s, v2.2s",
"uzp1 v2.4h, v2.4h, v2.4h",
"sxtl v2.4s, v2.4h",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pf2id mm0, mm1": {
@ -58,9 +58,9 @@
"0x0f 0x0f 0x1d"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d2, [x28, #1056]",
"fcvtzs v2.2s, v2.2s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pfrcpv mm0, mm1": {
@ -69,10 +69,10 @@
"0x0f 0x0f 0x86"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d2, [x28, #1056]",
"fmov v0.4s, #0x70 (1.0000)",
"fdiv v2.4s, v0.4s, v2.4s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pfrsqrtv mm0, mm1": {
@ -81,57 +81,57 @@
"0x0f 0x0f 0x87"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d2, [x28, #1056]",
"fmov v0.4s, #0x70 (1.0000)",
"fsqrt v1.4s, v2.4s",
"fdiv v2.4s, v0.4s, v1.4s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pfnacc mm0, mm1": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0x0f 0x8a",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"uzp1 v4.2s, v2.2s, v3.2s",
"uzp2 v2.2s, v2.2s, v3.2s",
"fsub v2.4s, v4.4s, v2.4s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pfpnacc mm0, mm1": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x0f 0x8e",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"dup v4.2s, v2.s[1]",
"fsub s2, s2, s4",
"faddp v3.4s, v3.4s, v3.4s",
"mov v2.s[1], v3.s[0]",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pfcmpge mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0x90",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"fcmge v2.4s, v3.4s, v2.4s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pfmin mm0, mm1": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x0f 0x94",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"fcmgt v0.4s, v3.4s, v2.4s",
"bif v2.16b, v3.16b, v0.16b",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pfrcp mm0, mm1": {
@ -140,11 +140,11 @@
"0x0f 0x0f 0x96"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d2, [x28, #1056]",
"fmov s0, #0x70 (1.0000)",
"fdiv s2, s0, s2",
"dup v2.2s, v2.s[0]",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pfrsqrt mm0, mm1": {
@ -153,61 +153,61 @@
"0x0f 0x0f 0x97"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d2, [x28, #1056]",
"fmov s0, #0x70 (1.0000)",
"fsqrt s1, s2",
"fdiv s2, s0, s1",
"dup v2.2s, v2.s[0]",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pfsub mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0x9a",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"fsub v2.4s, v3.4s, v2.4s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pfadd mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0x9e",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"fadd v2.4s, v3.4s, v2.4s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pfcmpgt mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0xa0",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"fcmgt v2.4s, v3.4s, v2.4s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pfmax mm0, mm1": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x0f 0xa4",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"fcmgt v0.4s, v3.4s, v2.4s",
"bit v2.16b, v3.16b, v0.16b",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pfrcpit1 mm0, mm1": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x0f 0xa6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"str d2, [x28, #768]"
"ldr d2, [x28, #1056]",
"str d2, [x28, #1040]"
]
},
"pfrcpit1 mm0, mm0": {
@ -219,8 +219,8 @@
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x0f 0xa7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"str d2, [x28, #768]"
"ldr d2, [x28, #1056]",
"str d2, [x28, #1040]"
]
},
"pfrsqit1 mm0, mm0": {
@ -232,38 +232,38 @@
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0xaa",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"fsub v2.4s, v2.4s, v3.4s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pfcmpeq mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0xb0",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"fcmeq v2.4s, v3.4s, v2.4s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pfmul mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0xb4",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"fmul v2.4s, v3.4s, v2.4s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pfrcpit2 mm0, mm1": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x0f 0xb6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"str d2, [x28, #768]"
"ldr d2, [x28, #1056]",
"str d2, [x28, #1040]"
]
},
"pfrcpit2 mm0, mm0": {
@ -279,32 +279,32 @@
"0x0f 0x0f 0xb7"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"smull v2.4s, v2.4h, v3.4h",
"movi v3.4s, #0x80, lsl #8",
"add v2.4s, v2.4s, v3.4s",
"shrn v2.4h, v2.4s, #16",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pswapd mm0, mm1": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0x0f 0xbb",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d2, [x28, #1056]",
"rev64 v2.2s, v2.2s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pavgusb mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0xbf",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"urhadd v2.16b, v3.16b, v2.16b",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
}
}

48
unittests/InstructionCountCI/FEXOpt/MultiInst.json
View File

@ -69,7 +69,7 @@
],
"ExpectedArm64ASM": [
"mov w20, #0x1",
"strb w20, [x28, #714]",
"strb w20, [x28, #986]",
"ldrb w20, [x10]",
"strb w20, [x11]",
"add x10, x10, #0x1 (1)",
@ -88,7 +88,7 @@
],
"ExpectedArm64ASM": [
"mov w20, #0x1",
"strb w20, [x28, #714]",
"strb w20, [x28, #986]",
"ldrh w20, [x10]",
"strh w20, [x11]",
"add x10, x10, #0x2 (2)",
@ -107,7 +107,7 @@
],
"ExpectedArm64ASM": [
"mov w20, #0x1",
"strb w20, [x28, #714]",
"strb w20, [x28, #986]",
"ldr w20, [x10]",
"str w20, [x11]",
"add x10, x10, #0x4 (4)",
@ -126,7 +126,7 @@
],
"ExpectedArm64ASM": [
"mov w20, #0x1",
"strb w20, [x28, #714]",
"strb w20, [x28, #986]",
"ldr x20, [x10]",
"str x20, [x11]",
"add x10, x10, #0x8 (8)",
@ -145,7 +145,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #714]",
"strb w20, [x28, #986]",
"ldrb w20, [x10]",
"strb w20, [x11]",
"sub x10, x10, #0x1 (1)",
@ -164,7 +164,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #714]",
"strb w20, [x28, #986]",
"ldrh w20, [x10]",
"strh w20, [x11]",
"sub x10, x10, #0x2 (2)",
@ -183,7 +183,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #714]",
"strb w20, [x28, #986]",
"ldr w20, [x10]",
"str w20, [x11]",
"sub x10, x10, #0x4 (4)",
@ -202,7 +202,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #714]",
"strb w20, [x28, #986]",
"ldr x20, [x10]",
"str x20, [x11]",
"sub x10, x10, #0x8 (8)",
@ -222,7 +222,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #714]",
"strb w21, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@ -279,7 +279,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #714]",
"strb w21, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@ -336,7 +336,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #714]",
"strb w21, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@ -393,7 +393,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #714]",
"strb w21, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@ -449,7 +449,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #714]",
"strb w20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@ -509,7 +509,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #714]",
"strb w20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@ -569,7 +569,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #714]",
"strb w20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@ -629,7 +629,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #714]",
"strb w20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@ -690,7 +690,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #714]",
"strb w21, [x28, #986]",
"uxtb w21, w4",
"mov x0, x5",
"mov x1, x11",
@ -733,7 +733,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #714]",
"strb w21, [x28, #986]",
"uxth w21, w4",
"mov x0, x5",
"mov x1, x11",
@ -776,7 +776,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #714]",
"strb w21, [x28, #986]",
"mov w21, w4",
"mov x0, x5",
"mov x1, x11",
@ -819,7 +819,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #714]",
"strb w21, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"cbz x0, #+0x58",
@ -860,7 +860,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #714]",
"strb w20, [x28, #986]",
"uxtb w20, w4",
"mov x0, x5",
"mov x1, x11",
@ -904,7 +904,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #714]",
"strb w20, [x28, #986]",
"uxth w20, w4",
"mov x0, x5",
"mov x1, x11",
@ -948,7 +948,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #714]",
"strb w20, [x28, #986]",
"mov w20, w4",
"mov x0, x5",
"mov x1, x11",
@ -992,7 +992,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #714]",
"strb w20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"cbz x0, #+0x60",

6
unittests/InstructionCountCI/FEXOpt/libnss.json
View File

@ -197,10 +197,10 @@
"ldr q19, [x11, #272]",
"ldr q24, [x11]",
"ldr q23, [x11, #16]",
"ldr x0, [x28, #1760]",
"ldr x0, [x28, #2016]",
"ldr q2, [x0, #2832]",
"tbl v16.16b, {v18.16b}, v2.16b",
"ldr x0, [x28, #1760]",
"ldr x0, [x28, #2016]",
"ldr q3, [x0, #432]",
"tbl v18.16b, {v19.16b}, v3.16b",
"ldr q22, [x11, #32]",
@ -284,7 +284,7 @@
"mov v4.s[1], w21",
"mov v20.16b, v4.16b",
"mov v20.s[0], w23",
"ldr x0, [x28, #1760]",
"ldr x0, [x28, #2016]",
"ldr q4, [x0, #224]",
"tbl v16.16b, {v16.16b}, v4.16b",
"mov w21, v20.s[1]",

22
unittests/InstructionCountCI/FlagM/HotBlocks.json
View File

@ -230,11 +230,11 @@
],
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #728]",
"stp x4, x5, [x28, #16]",
"stp x6, x7, [x28, #32]",
"str x8, [x28, #48]",
"stp x16, x17, [x28, #112]",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
@ -245,14 +245,14 @@
"mov x2, v17.d[0]",
"mov x3, v17.d[1]",
"mov w4, #0xd",
"ldr x5, [x28, #1560]",
"ldr x5, [x28, #1816]",
"blr x5",
"ldr w4, [x28, #728]",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #16]",
"ldp x6, x7, [x28, #32]",
"ldr x8, [x28, #48]",
"ldp x16, x17, [x28, #112]",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",

1796
unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json
View File

File diff suppressed because it is too large Load Diff

114
unittests/InstructionCountCI/FlagM/Primary.json
View File

@ -1664,30 +1664,30 @@
"eor w21, w27, w26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
"ldrb w21, [x28, #712]",
"ldrb w21, [x28, #984]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #713]",
"ldrb w21, [x28, #985]",
"orr x20, x20, x21, lsl #9",
"ldrsb x21, [x28, #714]",
"ldrsb x21, [x28, #986]",
"lsr x21, x21, #63",
"orr x20, x20, x21, lsl #10",
"cset w21, vs",
"orr x20, x20, x21, lsl #11",
"ldrb w21, [x28, #716]",
"ldrb w21, [x28, #988]",
"orr x20, x20, x21, lsl #12",
"ldrb w21, [x28, #718]",
"ldrb w21, [x28, #990]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #720]",
"ldrb w21, [x28, #992]",
"orr x20, x20, x21, lsl #16",
"ldrb w21, [x28, #721]",
"ldrb w21, [x28, #993]",
"orr x20, x20, x21, lsl #17",
"ldrb w21, [x28, #722]",
"ldrb w21, [x28, #994]",
"orr x20, x20, x21, lsl #18",
"ldrb w21, [x28, #723]",
"ldrb w21, [x28, #995]",
"orr x20, x20, x21, lsl #19",
"ldrb w21, [x28, #724]",
"ldrb w21, [x28, #996]",
"orr x20, x20, x21, lsl #20",
"ldrb w21, [x28, #725]",
"ldrb w21, [x28, #997]",
"orr x20, x20, x21, lsl #21",
"eor w21, w26, w26, lsr #4",
"eor w21, w21, w21, lsr #2",
@ -1709,30 +1709,30 @@
"eor w21, w27, w26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
"ldrb w21, [x28, #712]",
"ldrb w21, [x28, #984]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #713]",
"ldrb w21, [x28, #985]",
"orr x20, x20, x21, lsl #9",
"ldrsb x21, [x28, #714]",
"ldrsb x21, [x28, #986]",
"lsr x21, x21, #63",
"orr x20, x20, x21, lsl #10",
"cset w21, vs",
"orr x20, x20, x21, lsl #11",
"ldrb w21, [x28, #716]",
"ldrb w21, [x28, #988]",
"orr x20, x20, x21, lsl #12",
"ldrb w21, [x28, #718]",
"ldrb w21, [x28, #990]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #720]",
"ldrb w21, [x28, #992]",
"orr x20, x20, x21, lsl #16",
"ldrb w21, [x28, #721]",
"ldrb w21, [x28, #993]",
"orr x20, x20, x21, lsl #17",
"ldrb w21, [x28, #722]",
"ldrb w21, [x28, #994]",
"orr x20, x20, x21, lsl #18",
"ldrb w21, [x28, #723]",
"ldrb w21, [x28, #995]",
"orr x20, x20, x21, lsl #19",
"ldrb w21, [x28, #724]",
"ldrb w21, [x28, #996]",
"orr x20, x20, x21, lsl #20",
"ldrb w21, [x28, #725]",
"ldrb w21, [x28, #997]",
"orr x20, x20, x21, lsl #21",
"eor w21, w26, w26, lsr #4",
"eor w21, w21, w21, lsr #2",
@ -1761,29 +1761,29 @@
"rmif x27, #4, #nZcv",
"rmif x27, #4, #Nzcv",
"ubfx w20, w27, #8, #1",
"strb w20, [x28, #712]",
"strb w20, [x28, #984]",
"ubfx w20, w27, #9, #1",
"strb w20, [x28, #713]",
"strb w20, [x28, #985]",
"ubfx w20, w27, #10, #1",
"sub x20, x21, x20, lsl #1",
"strb w20, [x28, #714]",
"strb w20, [x28, #986]",
"rmif x27, #11, #nzcV",
"ubfx w20, w27, #12, #1",
"strb w20, [x28, #716]",
"strb w20, [x28, #988]",
"ubfx w20, w27, #14, #1",
"strb w20, [x28, #718]",
"strb w20, [x28, #990]",
"ubfx w20, w27, #16, #1",
"strb w20, [x28, #720]",
"strb w20, [x28, #992]",
"ubfx w20, w27, #17, #1",
"strb w20, [x28, #721]",
"strb w20, [x28, #993]",
"ubfx w20, w27, #18, #1",
"strb w20, [x28, #722]",
"strb w20, [x28, #994]",
"ubfx w20, w27, #19, #1",
"strb w20, [x28, #723]",
"strb w20, [x28, #995]",
"ubfx w20, w27, #20, #1",
"strb w20, [x28, #724]",
"strb w20, [x28, #996]",
"ubfx w20, w27, #21, #1",
"strb w20, [x28, #725]"
"strb w20, [x28, #997]"
]
},
"sahf": {
@ -1829,7 +1829,7 @@
"ExpectedArm64ASM": [
"ldrb w20, [x11]",
"ldrb w21, [x10]",
"ldrsb x22, [x28, #714]",
"ldrsb x22, [x28, #986]",
"add x11, x11, x22",
"add x10, x10, x22",
"eor w27, w21, w20",
@ -1847,7 +1847,7 @@
"ExpectedArm64ASM": [
"ldrh w20, [x11]",
"ldrh w21, [x10]",
"ldrsb x22, [x28, #714]",
"ldrsb x22, [x28, #986]",
"lsl x22, x22, #1",
"add x11, x11, x22",
"add x10, x10, x22",
@ -1866,7 +1866,7 @@
"ExpectedArm64ASM": [
"ldr w20, [x11]",
"ldr w21, [x10]",
"ldrsb x22, [x28, #714]",
"ldrsb x22, [x28, #986]",
"lsl x22, x22, #2",
"add x11, x11, x22",
"add x10, x10, x22",
@ -1883,7 +1883,7 @@
"ExpectedArm64ASM": [
"ldr x20, [x11]",
"ldr x21, [x10]",
"ldrsb x22, [x28, #714]",
"ldrsb x22, [x28, #986]",
"lsl x22, x22, #3",
"add x11, x11, x22",
"add x10, x10, x22",
@ -1897,7 +1897,7 @@
"Comment": "0xa6",
"ExpectedArm64ASM": [
"cbz x5, #+0x6c",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@ -1930,7 +1930,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x6c",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@ -1963,7 +1963,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x64",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@ -1994,7 +1994,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x64",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@ -2025,7 +2025,7 @@
"Comment": "0xa6",
"ExpectedArm64ASM": [
"cbz x5, #+0x6c",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@ -2058,7 +2058,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x6c",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@ -2091,7 +2091,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x64",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@ -2122,7 +2122,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x64",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@ -2213,7 +2213,7 @@
"Comment": "0xae",
"ExpectedArm64ASM": [
"ldrb w20, [x11]",
"ldrsb x21, [x28, #714]",
"ldrsb x21, [x28, #986]",
"add x11, x11, x21",
"eor w27, w4, w20",
"lsl w0, w4, #24",
@ -2227,7 +2227,7 @@
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrh w20, [x11]",
"ldrsb x21, [x28, #714]",
"ldrsb x21, [x28, #986]",
"add x11, x11, x21, lsl #1",
"eor w27, w4, w20",
"lsl w0, w4, #16",
@ -2241,7 +2241,7 @@
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldr w20, [x11]",
"ldrsb x21, [x28, #714]",
"ldrsb x21, [x28, #986]",
"add x11, x11, x21, lsl #2",
"eor w27, w4, w20",
"subs w26, w4, w20",
@ -2253,7 +2253,7 @@
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldr x20, [x11]",
"ldrsb x21, [x28, #714]",
"ldrsb x21, [x28, #986]",
"add x11, x11, x21, lsl #3",
"eor w27, w4, w20",
"subs x26, x4, x20",
@ -2264,7 +2264,7 @@
"ExpectedInstructionCount": 25,
"Comment": "0xae",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x30",
@ -2295,7 +2295,7 @@
"ExpectedInstructionCount": 25,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x30",
@ -2326,7 +2326,7 @@
"ExpectedInstructionCount": 21,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x28",
@ -2353,7 +2353,7 @@
"ExpectedInstructionCount": 21,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x28",
@ -2380,7 +2380,7 @@
"ExpectedInstructionCount": 25,
"Comment": "0xae",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x30",
@ -2411,7 +2411,7 @@
"ExpectedInstructionCount": 25,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x30",
@ -2442,7 +2442,7 @@
"ExpectedInstructionCount": 21,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x28",
@ -2469,7 +2469,7 @@
"ExpectedInstructionCount": 21,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x28",

26
unittests/InstructionCountCI/FlagM/Primary_32Bit.json
View File

@ -16,7 +16,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x06",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #144]",
"ldrh w20, [x28, #928]",
"str w20, [x8, #-4]!"
]
},
@ -26,18 +26,18 @@
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #144]",
"strh w20, [x28, #928]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #160]"
"ldr w20, [x0, #1168]",
"str w20, [x28, #944]"
]
},
"push cs": {
"ExpectedInstructionCount": 2,
"Comment": "0x0e",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #146]",
"ldrh w20, [x28, #930]",
"str w20, [x8, #-4]!"
]
},
@ -45,7 +45,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x16",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #148]",
"ldrh w20, [x28, #932]",
"str w20, [x8, #-4]!"
]
},
@ -55,18 +55,18 @@
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #148]",
"strh w20, [x28, #932]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #168]"
"ldr w20, [x0, #1168]",
"str w20, [x28, #952]"
]
},
"push ds": {
"ExpectedInstructionCount": 2,
"Comment": "0x1e",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #150]",
"ldrh w20, [x28, #934]",
"str w20, [x8, #-4]!"
]
},
@ -76,11 +76,11 @@
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #150]",
"strh w20, [x28, #934]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #172]"
"ldr w20, [x0, #1168]",
"str w20, [x28, #956]"
]
},
"daa": {

8
unittests/InstructionCountCI/FlagM/Secondary.json
View File

@ -1609,8 +1609,8 @@
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xd7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #2288]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #2544]",
"cmlt v2.16b, v2.16b, #0",
"and v2.16b, v2.16b, v3.16b",
"addp v2.16b, v2.16b, v2.16b",
@ -1623,9 +1623,9 @@
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xf7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d2, [x28, #1056]",
"cmlt v2.16b, v2.16b, #0",
"ldr d3, [x28, #768]",
"ldr d3, [x28, #1040]",
"ldr d4, [x11]",
"bsl v2.8b, v3.8b, v4.8b",
"str d2, [x11]"

230
unittests/InstructionCountCI/FlagM/SecondaryGroup.json
View File

@ -789,9 +789,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"ushr v2.8h, v2.8h, #15",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psrlw mm0, 16": {
@ -799,9 +799,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psrlw xmm0, 0": {
@ -837,9 +837,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psraw mm0, 16": {
@ -847,9 +847,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psraw xmm0, 0": {
@ -885,9 +885,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"shl v2.8h, v2.8h, #15",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psllw mm0, 16": {
@ -895,9 +895,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psllw xmm0, 0": {
@ -933,9 +933,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"ushr v2.4s, v2.4s, #31",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psrld mm0, 32": {
@ -943,9 +943,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psrld xmm0, 0": {
@ -981,9 +981,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psrad mm0, 32": {
@ -991,9 +991,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psrad xmm0, 0": {
@ -1029,9 +1029,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"shl v2.4s, v2.4s, #31",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pslld mm0, 32": {
@ -1039,9 +1039,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pslld xmm0, 0": {
@ -1077,9 +1077,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"ushr v2.2d, v2.2d, #63",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psrlq mm0, 64": {
@ -1087,9 +1087,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psrlq xmm0, 0": {
@ -1148,9 +1148,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"shl v2.2d, v2.2d, #63",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psllq mm0, 64": {
@ -1158,9 +1158,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psllq xmm0, 0": {
@ -1189,37 +1189,37 @@
"ExpectedInstructionCount": 57,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #1024]",
"ldrh w20, [x28, #1296]",
"strh w20, [x4]",
"mov w20, #0x0",
"ldrb w21, [x28, #747]",
"ldrb w21, [x28, #1019]",
"bfi x20, x21, #11, #3",
"ldrb w21, [x28, #744]",
"ldrb w22, [x28, #745]",
"ldrb w23, [x28, #746]",
"ldrb w24, [x28, #750]",
"ldrb w21, [x28, #1016]",
"ldrb w22, [x28, #1017]",
"ldrb w23, [x28, #1018]",
"ldrb w24, [x28, #1022]",
"orr x20, x20, x21, lsl #8",
"orr x20, x20, x22, lsl #9",
"orr x20, x20, x23, lsl #10",
"orr x20, x20, x24, lsl #14",
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1026]",
"ldrb w20, [x28, #1298]",
"strb w20, [x4, #4]",
"ldr q2, [x28, #768]",
"ldr q2, [x28, #1040]",
"str q2, [x4, #32]",
"ldr q2, [x28, #784]",
"ldr q2, [x28, #1056]",
"str q2, [x4, #48]",
"ldr q2, [x28, #800]",
"ldr q2, [x28, #1072]",
"str q2, [x4, #64]",
"ldr q2, [x28, #816]",
"ldr q2, [x28, #1088]",
"str q2, [x4, #80]",
"ldr q2, [x28, #832]",
"ldr q2, [x28, #1104]",
"str q2, [x4, #96]",
"ldr q2, [x28, #848]",
"ldr q2, [x28, #1120]",
"str q2, [x4, #112]",
"ldr q2, [x28, #864]",
"ldr q2, [x28, #1136]",
"str q2, [x4, #128]",
"ldr q2, [x28, #880]",
"ldr q2, [x28, #1152]",
"str q2, [x4, #144]",
"str q16, [x4, #160]",
"str q17, [x4, #176]",
@ -1252,14 +1252,14 @@
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldr w4, [x28, #184]"
"ldr w4, [x28, #968]"
]
},
"rdfsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldr x4, [x28, #184]"
"ldr x4, [x28, #968]"
]
},
"fxrstor [rax]": {
@ -1267,36 +1267,36 @@
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"strh w20, [x28, #1024]",
"strh w20, [x28, #1296]",
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #747]",
"strb w21, [x28, #1019]",
"ubfx w21, w20, #8, #1",
"ubfx w22, w20, #9, #1",
"ubfx w23, w20, #10, #1",
"ubfx w20, w20, #14, #1",
"strb w21, [x28, #744]",
"strb w22, [x28, #745]",
"strb w23, [x28, #746]",
"strb w20, [x28, #750]",
"strb w21, [x28, #1016]",
"strb w22, [x28, #1017]",
"strb w23, [x28, #1018]",
"strb w20, [x28, #1022]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1026]",
"strb w20, [x28, #1298]",
"ldr q2, [x4, #32]",
"str q2, [x28, #768]",
"str q2, [x28, #1040]",
"ldr q2, [x4, #48]",
"str q2, [x28, #784]",
"str q2, [x28, #1056]",
"ldr q2, [x4, #64]",
"str q2, [x28, #800]",
"str q2, [x28, #1072]",
"ldr q2, [x4, #80]",
"str q2, [x28, #816]",
"str q2, [x28, #1088]",
"ldr q2, [x4, #96]",
"str q2, [x28, #832]",
"str q2, [x28, #1104]",
"ldr q2, [x4, #112]",
"str q2, [x28, #848]",
"str q2, [x28, #1120]",
"ldr q2, [x4, #128]",
"str q2, [x28, #864]",
"str q2, [x28, #1136]",
"ldr q2, [x4, #144]",
"str q2, [x28, #880]",
"str q2, [x28, #1152]",
"ldr q16, [x4, #160]",
"ldr q17, [x4, #176]",
"ldr q18, [x4, #192]",
@ -1328,14 +1328,14 @@
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldr w4, [x28, #176]"
"ldr w4, [x28, #960]"
]
},
"rdgsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldr x4, [x28, #176]"
"ldr x4, [x28, #960]"
]
},
"ldmxcsr [rax]": {
@ -1358,14 +1358,14 @@
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"mov w20, w4",
"str x20, [x28, #184]"
"str x20, [x28, #968]"
]
},
"wrfsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"str x4, [x28, #184]"
"str x4, [x28, #968]"
]
},
"stmxcsr [rax]": {
@ -1386,14 +1386,14 @@
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"mov w20, w4",
"str x20, [x28, #176]"
"str x20, [x28, #960]"
]
},
"wrgsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"str x4, [x28, #176]"
"str x4, [x28, #960]"
]
},
"xsave [rax]": {
@ -1403,37 +1403,37 @@
"ubfx x20, x4, #0, #1",
"cbnz x20, #+0x8",
"b #+0x84",
"ldrh w20, [x28, #1024]",
"ldrh w20, [x28, #1296]",
"strh w20, [x4]",
"mov w20, #0x0",
"ldrb w21, [x28, #747]",
"ldrb w21, [x28, #1019]",
"bfi x20, x21, #11, #3",
"ldrb w21, [x28, #744]",
"ldrb w22, [x28, #745]",
"ldrb w23, [x28, #746]",
"ldrb w24, [x28, #750]",
"ldrb w21, [x28, #1016]",
"ldrb w22, [x28, #1017]",
"ldrb w23, [x28, #1018]",
"ldrb w24, [x28, #1022]",
"orr x20, x20, x21, lsl #8",
"orr x20, x20, x22, lsl #9",
"orr x20, x20, x23, lsl #10",
"orr x20, x20, x24, lsl #14",
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1026]",
"ldrb w20, [x28, #1298]",
"strb w20, [x4, #4]",
"ldr q2, [x28, #768]",
"ldr q2, [x28, #1040]",
"str q2, [x4, #32]",
"ldr q2, [x28, #784]",
"ldr q2, [x28, #1056]",
"str q2, [x4, #48]",
"ldr q2, [x28, #800]",
"ldr q2, [x28, #1072]",
"str q2, [x4, #64]",
"ldr q2, [x28, #816]",
"ldr q2, [x28, #1088]",
"str q2, [x4, #80]",
"ldr q2, [x28, #832]",
"ldr q2, [x28, #1104]",
"str q2, [x4, #96]",
"ldr q2, [x28, #848]",
"ldr q2, [x28, #1120]",
"str q2, [x4, #112]",
"ldr q2, [x28, #864]",
"ldr q2, [x28, #1136]",
"str q2, [x4, #128]",
"ldr q2, [x28, #880]",
"ldr q2, [x28, #1152]",
"str q2, [x4, #144]",
"ubfx x20, x4, #1, #1",
"cbnz x20, #+0x8",
@ -1486,55 +1486,55 @@
"cbnz x20, #+0x8",
"b #+0x84",
"ldrh w20, [x4]",
"strh w20, [x28, #1024]",
"strh w20, [x28, #1296]",
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #747]",
"strb w21, [x28, #1019]",
"ubfx w21, w20, #8, #1",
"ubfx w22, w20, #9, #1",
"ubfx w23, w20, #10, #1",
"ubfx w20, w20, #14, #1",
"strb w21, [x28, #744]",
"strb w22, [x28, #745]",
"strb w23, [x28, #746]",
"strb w20, [x28, #750]",
"strb w21, [x28, #1016]",
"strb w22, [x28, #1017]",
"strb w23, [x28, #1018]",
"strb w20, [x28, #1022]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1026]",
"strb w20, [x28, #1298]",
"ldr q2, [x4, #32]",
"str q2, [x28, #768]",
"str q2, [x28, #1040]",
"ldr q2, [x4, #48]",
"str q2, [x28, #784]",
"str q2, [x28, #1056]",
"ldr q2, [x4, #64]",
"str q2, [x28, #800]",
"str q2, [x28, #1072]",
"ldr q2, [x4, #80]",
"str q2, [x28, #816]",
"str q2, [x28, #1088]",
"ldr q2, [x4, #96]",
"str q2, [x28, #832]",
"str q2, [x28, #1104]",
"ldr q2, [x4, #112]",
"str q2, [x28, #848]",
"str q2, [x28, #1120]",
"ldr q2, [x4, #128]",
"str q2, [x28, #864]",
"str q2, [x28, #1136]",
"ldr q2, [x4, #144]",
"str q2, [x28, #880]",
"str q2, [x28, #1152]",
"b #+0x4c",
"mov w20, #0x0",
"mov w21, #0x37f",
"strh w21, [x28, #1024]",
"strb w20, [x28, #747]",
"strb w20, [x28, #744]",
"strb w20, [x28, #745]",
"strb w20, [x28, #746]",
"strb w20, [x28, #750]",
"strb w20, [x28, #1026]",
"strh w21, [x28, #1296]",
"strb w20, [x28, #1019]",
"strb w20, [x28, #1016]",
"strb w20, [x28, #1017]",
"strb w20, [x28, #1018]",
"strb w20, [x28, #1022]",
"strb w20, [x28, #1298]",
"movi v2.2d, #0x0",
"str q2, [x28, #768]",
"str q2, [x28, #784]",
"str q2, [x28, #800]",
"str q2, [x28, #816]",
"str q2, [x28, #832]",
"str q2, [x28, #848]",
"str q2, [x28, #864]",
"str q2, [x28, #880]",
"str q2, [x28, #1040]",
"str q2, [x28, #1056]",
"str q2, [x28, #1072]",
"str q2, [x28, #1088]",
"str q2, [x28, #1104]",
"str q2, [x28, #1120]",
"str q2, [x28, #1136]",
"str q2, [x28, #1152]",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #1, #1",
"cbnz x20, #+0x8",

64
unittests/InstructionCountCI/FlagM/SecondaryModRM.json
View File

@ -25,43 +25,43 @@
"st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x3], #64",
"str x30, [x3]",
"mrs x3, nzcv",
"str w3, [x28, #728]",
"stp x4, x5, [x28, #16]",
"stp x6, x7, [x28, #32]",
"stp x8, x9, [x28, #48]",
"stp x10, x11, [x28, #64]",
"stp x12, x13, [x28, #80]",
"stp x14, x15, [x28, #96]",
"stp x16, x17, [x28, #112]",
"stp x19, x29, [x28, #128]",
"str x26, [x28, #752]",
"str x27, [x28, #760]",
"add x3, x28, #0xc0 (192)",
"str w3, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
"stp x14, x15, [x28, #360]",
"stp x16, x17, [x28, #376]",
"stp x19, x29, [x28, #392]",
"str x26, [x28, #1024]",
"str x27, [x28, #1032]",
"add x3, x28, #0x1a0 (416)",
"st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x3], #64",
"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x3], #64",
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x3], #64",
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x3], #64",
"mov w1, w5",
"ldr x0, [x28, #1112]",
"ldr x2, [x28, #1128]",
"ldr x0, [x28, #1368]",
"ldr x2, [x28, #1384]",
"blr x2",
"ldr w4, [x28, #728]",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"add x4, x28, #0xc0 (192)",
"add x4, x28, #0x1a0 (416)",
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #16]",
"ldp x6, x7, [x28, #32]",
"ldp x8, x9, [x28, #48]",
"ldp x10, x11, [x28, #64]",
"ldp x12, x13, [x28, #80]",
"ldp x14, x15, [x28, #96]",
"ldp x16, x17, [x28, #112]",
"ldp x19, x29, [x28, #128]",
"ldr x26, [x28, #752]",
"ldr x27, [x28, #760]",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
"ldp x14, x15, [x28, #360]",
"ldp x16, x17, [x28, #376]",
"ldp x19, x29, [x28, #392]",
"ldr x26, [x28, #1024]",
"ldr x27, [x28, #1032]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
@ -82,10 +82,10 @@
"lsl w4, w20, #7",
"lsr x6, x20, #25",
"mrs x0, nzcv",
"str w0, [x28, #728]",
"str x8, [x28, #48]",
"str w0, [x28, #1000]",
"str x8, [x28, #312]",
"mov w0, #0x100",
"str x0, [x28, #1048]",
"str x0, [x28, #1312]",
"sub sp, sp, #0x10 (16)",
"mov w8, #0xa8",
"mov x0, sp",
@ -93,10 +93,10 @@
"svc #0x0",
"ldp w0, w1, [sp]",
"sub sp, sp, #0x10 (16)",
"ldr w8, [x28, #728]",
"ldr w8, [x28, #1000]",
"msr nzcv, x8",
"ldr x8, [x28, #48]",
"str xzr, [x28, #1048]",
"ldr x8, [x28, #312]",
"str xzr, [x28, #1312]",
"orr x5, x0, x1, lsl #12"
]
}

2
unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
View File

@ -39,7 +39,7 @@
"ExpectedInstructionCount": 7,
"Comment": "0x66 0x0f 0xd7",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2288]",
"ldr q2, [x28, #2544]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",

4
unittests/InstructionCountCI/FlagM/VEX_map1.json
View File

@ -72,7 +72,7 @@
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2288]",
"ldr q2, [x28, #2544]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",
@ -87,7 +87,7 @@
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1680]",
"ldr x0, [x28, #1936]",
"ld1b {z2.b}, p7/z, [x0]",
"mrs x0, nzcv",
"mov z0.d, #0",

11448
unittests/InstructionCountCI/FlagM/x87.json
View File

File diff suppressed because it is too large Load Diff

5218
unittests/InstructionCountCI/FlagM/x87_f64.json
View File

File diff suppressed because it is too large Load Diff

86
unittests/InstructionCountCI/H0F38.json
View File

@ -18,12 +18,12 @@
"NP 0x0f 0x38 0x00"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"movi v4.16b, #0x87",
"and v3.16b, v3.16b, v4.16b",
"tbl v2.8b, {v2.16b}, v3.8b",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pshufb xmm0, xmm1": {
@ -43,10 +43,10 @@
"NP 0x0f 0x38 0x01"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"addp v2.4h, v3.4h, v2.4h",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"phaddw xmm0, xmm1": {
@ -64,10 +64,10 @@
"NP 0x0f 0x38 0x02"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"addp v2.2s, v3.2s, v2.2s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"phaddd xmm0, xmm1": {
@ -85,12 +85,12 @@
"NP 0x0f 0x38 0x03"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"uzp1 v4.4h, v2.4h, v3.4h",
"uzp2 v2.4h, v2.4h, v3.4h",
"sqadd v2.8h, v4.8h, v2.8h",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"phaddsw xmm0, xmm1": {
@ -110,15 +110,15 @@
"NP 0x0f 0x38 0x04"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"uxtl v2.8h, v2.8b",
"sxtl v3.8h, v3.8b",
"smull v4.4s, v2.4h, v3.4h",
"smull2 v2.4s, v2.8h, v3.8h",
"addp v2.4s, v4.4s, v2.4s",
"sqxtn v2.4h, v2.4s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pmaddubsw xmm0, xmm1": {
@ -148,12 +148,12 @@
"NP 0x0f 0x38 0x05"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"uzp1 v4.4h, v2.4h, v3.4h",
"uzp2 v2.4h, v2.4h, v3.4h",
"sub v2.8h, v4.8h, v2.8h",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"phsubw xmm0, xmm1": {
@ -173,12 +173,12 @@
"NP 0x0f 0x38 0x06"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"uzp1 v4.2s, v2.2s, v3.2s",
"uzp2 v2.2s, v2.2s, v3.2s",
"sub v2.4s, v4.4s, v2.4s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"phsubd xmm0, xmm1": {
@ -198,12 +198,12 @@
"NP 0x0f 0x38 0x07"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"uzp1 v4.4h, v2.4h, v3.4h",
"uzp2 v2.4h, v2.4h, v3.4h",
"sqsub v2.8h, v4.8h, v2.8h",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"phsubsw xmm0, xmm1": {
@ -223,12 +223,12 @@
"NP 0x0f 0x38 0x08"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"sqshl v2.8b, v2.8b, #7",
"srshr v2.8b, v2.8b, #7",
"mul v2.16b, v3.16b, v2.16b",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psignb xmm0, xmm1": {
@ -248,12 +248,12 @@
"NP 0x0f 0x38 0x09"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"sqshl v2.4h, v2.4h, #15",
"srshr v2.4h, v2.4h, #15",
"mul v2.8h, v3.8h, v2.8h",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psignw xmm0, xmm1": {
@ -273,12 +273,12 @@
"NP 0x0f 0x38 0x0a"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"sqshl v2.2s, v2.2s, #31",
"srshr v2.2s, v2.2s, #31",
"mul v2.4s, v3.4s, v2.4s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psignd xmm0, xmm1": {
@ -299,14 +299,14 @@
"NP 0x0f 0x38 0x0b"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"smull v2.4s, v2.4h, v3.4h",
"sshr v2.4s, v2.4s, #14",
"movi v3.4s, #0x1, lsl #0",
"add v2.4s, v2.4s, v3.4s",
"shrn v2.4h, v2.4s, #1",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pmulhrsw xmm0, xmm1": {
@ -417,9 +417,9 @@
"NP 0x0f 0x38 0x1c"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d2, [x28, #1056]",
"abs v2.16b, v2.16b",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pabsb xmm0, xmm1": {
@ -437,9 +437,9 @@
"NP 0x0f 0x38 0x1d"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d2, [x28, #1056]",
"abs v2.8h, v2.8h",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pabsw xmm0, xmm1": {
@ -457,9 +457,9 @@
"NP 0x0f 0x38 0x1e"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d2, [x28, #1056]",
"abs v2.4s, v2.4s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pabsd xmm0, xmm1": {
@ -625,7 +625,7 @@
"0x66 0x0f 0x38 0x41"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2064]",
"ldr q2, [x28, #2320]",
"zip1 v3.8h, v2.8h, v17.8h",
"zip2 v2.8h, v2.8h, v17.8h",
"umin v2.4s, v3.4s, v2.4s",

26
unittests/InstructionCountCI/H0F3A.json
View File

@ -20,8 +20,8 @@
"NP 0x0f 0x3a 0x0f"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"str d2, [x28, #768]"
"ldr d2, [x28, #1056]",
"str d2, [x28, #1040]"
]
},
"palignr mm0, mm1, 1": {
@ -30,10 +30,10 @@
"NP 0x0f 0x3a 0x0f"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #1056]",
"ldr d3, [x28, #1040]",
"ext v2.8b, v2.8b, v3.8b, #1",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"palignr mm0, mm1, 255": {
@ -43,7 +43,7 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"roundps xmm0, xmm1, 00000000b": {
@ -315,7 +315,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2192]",
"ldr q2, [x28, #2448]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@ -325,7 +325,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2208]",
"ldr q2, [x28, #2464]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@ -344,7 +344,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2224]",
"ldr q2, [x28, #2480]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@ -364,7 +364,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2240]",
"ldr q2, [x28, #2496]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@ -383,7 +383,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2256]",
"ldr q2, [x28, #2512]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@ -393,7 +393,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2272]",
"ldr q2, [x28, #2528]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@ -462,7 +462,7 @@
"0x66 0x0f 0x3a 0x0e"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1792]",
"ldr x0, [x28, #2048]",
"ldr q2, [x0, #3440]",
"tbx v16.16b, {v17.16b}, v2.16b"
]

208
unittests/InstructionCountCI/Primary.json
View File

@ -2043,7 +2043,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #146]",
"ldrh w20, [x28, #930]",
"bfxil x4, x20, #0, #16"
]
},
@ -2051,21 +2051,21 @@
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #146]"
"ldrh w4, [x28, #930]"
]
},
"mov rax, cs": {
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #146]"
"ldrh w4, [x28, #930]"
]
},
"mov ax, es": {
"ExpectedInstructionCount": 2,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #144]",
"ldrh w20, [x28, #928]",
"bfxil x4, x20, #0, #16"
]
},
@ -2073,21 +2073,21 @@
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #144]"
"ldrh w4, [x28, #928]"
]
},
"mov rax, es": {
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #144]"
"ldrh w4, [x28, #928]"
]
},
"mov ax, ss": {
"ExpectedInstructionCount": 2,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #148]",
"ldrh w20, [x28, #932]",
"bfxil x4, x20, #0, #16"
]
},
@ -2095,21 +2095,21 @@
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #148]"
"ldrh w4, [x28, #932]"
]
},
"mov rax, ss": {
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #148]"
"ldrh w4, [x28, #932]"
]
},
"mov ax, ds": {
"ExpectedInstructionCount": 2,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #150]",
"ldrh w20, [x28, #934]",
"bfxil x4, x20, #0, #16"
]
},
@ -2117,14 +2117,14 @@
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #150]"
"ldrh w4, [x28, #934]"
]
},
"mov rax, ds": {
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #150]"
"ldrh w4, [x28, #934]"
]
},
"mov ax, gs": {
@ -2371,11 +2371,11 @@
"Comment": "0x8e",
"ExpectedArm64ASM": [
"uxth w20, w4",
"strh w20, [x28, #144]",
"strh w20, [x28, #928]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #160]"
"ldr w20, [x0, #1168]",
"str w20, [x28, #944]"
]
},
"mov ss, ax": {
@ -2383,11 +2383,11 @@
"Comment": "0x8e",
"ExpectedArm64ASM": [
"uxth w20, w4",
"strh w20, [x28, #148]",
"strh w20, [x28, #932]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #168]"
"ldr w20, [x0, #1168]",
"str w20, [x28, #952]"
]
},
"mov ds, ax": {
@ -2395,11 +2395,11 @@
"Comment": "0x8e",
"ExpectedArm64ASM": [
"uxth w20, w4",
"strh w20, [x28, #150]",
"strh w20, [x28, #934]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #172]"
"ldr w20, [x0, #1168]",
"str w20, [x28, #956]"
]
},
"mov gs, ax": {
@ -2525,30 +2525,30 @@
"eor w21, w27, w26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
"ldrb w21, [x28, #712]",
"ldrb w21, [x28, #984]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #713]",
"ldrb w21, [x28, #985]",
"orr x20, x20, x21, lsl #9",
"ldrsb x21, [x28, #714]",
"ldrsb x21, [x28, #986]",
"lsr x21, x21, #63",
"orr x20, x20, x21, lsl #10",
"cset w21, vs",
"orr x20, x20, x21, lsl #11",
"ldrb w21, [x28, #716]",
"ldrb w21, [x28, #988]",
"orr x20, x20, x21, lsl #12",
"ldrb w21, [x28, #718]",
"ldrb w21, [x28, #990]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #720]",
"ldrb w21, [x28, #992]",
"orr x20, x20, x21, lsl #16",
"ldrb w21, [x28, #721]",
"ldrb w21, [x28, #993]",
"orr x20, x20, x21, lsl #17",
"ldrb w21, [x28, #722]",
"ldrb w21, [x28, #994]",
"orr x20, x20, x21, lsl #18",
"ldrb w21, [x28, #723]",
"ldrb w21, [x28, #995]",
"orr x20, x20, x21, lsl #19",
"ldrb w21, [x28, #724]",
"ldrb w21, [x28, #996]",
"orr x20, x20, x21, lsl #20",
"ldrb w21, [x28, #725]",
"ldrb w21, [x28, #997]",
"orr x20, x20, x21, lsl #21",
"eor w21, w26, w26, lsr #4",
"eor w21, w21, w21, lsr #2",
@ -2570,30 +2570,30 @@
"eor w21, w27, w26",
"ubfx w21, w21, #4, #1",
"orr x20, x20, x21, lsl #4",
"ldrb w21, [x28, #712]",
"ldrb w21, [x28, #984]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #713]",
"ldrb w21, [x28, #985]",
"orr x20, x20, x21, lsl #9",
"ldrsb x21, [x28, #714]",
"ldrsb x21, [x28, #986]",
"lsr x21, x21, #63",
"orr x20, x20, x21, lsl #10",
"cset w21, vs",
"orr x20, x20, x21, lsl #11",
"ldrb w21, [x28, #716]",
"ldrb w21, [x28, #988]",
"orr x20, x20, x21, lsl #12",
"ldrb w21, [x28, #718]",
"ldrb w21, [x28, #990]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #720]",
"ldrb w21, [x28, #992]",
"orr x20, x20, x21, lsl #16",
"ldrb w21, [x28, #721]",
"ldrb w21, [x28, #993]",
"orr x20, x20, x21, lsl #17",
"ldrb w21, [x28, #722]",
"ldrb w21, [x28, #994]",
"orr x20, x20, x21, lsl #18",
"ldrb w21, [x28, #723]",
"ldrb w21, [x28, #995]",
"orr x20, x20, x21, lsl #19",
"ldrb w21, [x28, #724]",
"ldrb w21, [x28, #996]",
"orr x20, x20, x21, lsl #20",
"ldrb w21, [x28, #725]",
"ldrb w21, [x28, #997]",
"orr x20, x20, x21, lsl #21",
"eor w21, w26, w26, lsr #4",
"eor w21, w21, w21, lsr #2",
@ -2625,30 +2625,30 @@
"ubfx x21, x27, #7, #1",
"orr w20, w20, w21, lsl #31",
"ubfx w21, w27, #8, #1",
"strb w21, [x28, #712]",
"strb w21, [x28, #984]",
"ubfx w21, w27, #9, #1",
"strb w21, [x28, #713]",
"strb w21, [x28, #985]",
"ubfx w21, w27, #10, #1",
"sub x21, x22, x21, lsl #1",
"strb w21, [x28, #714]",
"strb w21, [x28, #986]",
"ubfx x21, x27, #11, #1",
"orr w20, w20, w21, lsl #28",
"ubfx w21, w27, #12, #1",
"strb w21, [x28, #716]",
"strb w21, [x28, #988]",
"ubfx w21, w27, #14, #1",
"strb w21, [x28, #718]",
"strb w21, [x28, #990]",
"ubfx w21, w27, #16, #1",
"strb w21, [x28, #720]",
"strb w21, [x28, #992]",
"ubfx w21, w27, #17, #1",
"strb w21, [x28, #721]",
"strb w21, [x28, #993]",
"ubfx w21, w27, #18, #1",
"strb w21, [x28, #722]",
"strb w21, [x28, #994]",
"ubfx w21, w27, #19, #1",
"strb w21, [x28, #723]",
"strb w21, [x28, #995]",
"ubfx w21, w27, #20, #1",
"strb w21, [x28, #724]",
"strb w21, [x28, #996]",
"ubfx w21, w27, #21, #1",
"strb w21, [x28, #725]",
"strb w21, [x28, #997]",
"msr nzcv, x20"
]
},
@ -2753,7 +2753,7 @@
"ExpectedArm64ASM": [
"ldrb w20, [x10]",
"strb w20, [x11]",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"add x10, x10, x20",
"add x11, x11, x20"
]
@ -2766,7 +2766,7 @@
"ExpectedArm64ASM": [
"ldrh w20, [x10]",
"strh w20, [x11]",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsl x20, x20, #1",
"add x10, x10, x20",
"add x11, x11, x20"
@ -2780,7 +2780,7 @@
"ExpectedArm64ASM": [
"ldr w20, [x10]",
"str w20, [x11]",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsl x20, x20, #2",
"add x10, x10, x20",
"add x11, x11, x20"
@ -2794,7 +2794,7 @@
"ExpectedArm64ASM": [
"ldr x20, [x10]",
"str x20, [x11]",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsl x20, x20, #3",
"add x10, x10, x20",
"add x11, x11, x20"
@ -2804,7 +2804,7 @@
"ExpectedInstructionCount": 83,
"Comment": "0xa4",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@ -2893,7 +2893,7 @@
"ExpectedInstructionCount": 83,
"Comment": "0xa5",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@ -2982,7 +2982,7 @@
"ExpectedInstructionCount": 83,
"Comment": "0xa5",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@ -3071,7 +3071,7 @@
"ExpectedInstructionCount": 83,
"Comment": "0xa5",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@ -3164,7 +3164,7 @@
"ExpectedArm64ASM": [
"ldrb w20, [x11]",
"ldrb w21, [x10]",
"ldrsb x22, [x28, #714]",
"ldrsb x22, [x28, #986]",
"add x11, x11, x22",
"add x10, x10, x22",
"eor w27, w21, w20",
@ -3184,7 +3184,7 @@
"ExpectedArm64ASM": [
"ldrh w20, [x11]",
"ldrh w21, [x10]",
"ldrsb x22, [x28, #714]",
"ldrsb x22, [x28, #986]",
"lsl x22, x22, #1",
"add x11, x11, x22",
"add x10, x10, x22",
@ -3205,7 +3205,7 @@
"ExpectedArm64ASM": [
"ldr w20, [x11]",
"ldr w21, [x10]",
"ldrsb x22, [x28, #714]",
"ldrsb x22, [x28, #986]",
"lsl x22, x22, #2",
"add x11, x11, x22",
"add x10, x10, x22",
@ -3224,7 +3224,7 @@
"ExpectedArm64ASM": [
"ldr x20, [x11]",
"ldr x21, [x10]",
"ldrsb x22, [x28, #714]",
"ldrsb x22, [x28, #986]",
"lsl x22, x22, #3",
"add x11, x11, x22",
"add x10, x10, x22",
@ -3240,7 +3240,7 @@
"Comment": "0xa6",
"ExpectedArm64ASM": [
"cbz x5, #+0x74",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@ -3275,7 +3275,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x74",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@ -3310,7 +3310,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x6c",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@ -3343,7 +3343,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x6c",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@ -3376,7 +3376,7 @@
"Comment": "0xa6",
"ExpectedArm64ASM": [
"cbz x5, #+0x74",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@ -3411,7 +3411,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x74",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@ -3446,7 +3446,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x6c",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@ -3479,7 +3479,7 @@
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x6c",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x24",
@ -3572,7 +3572,7 @@
"Comment": "0xaa",
"ExpectedArm64ASM": [
"strb w4, [x11]",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"add x11, x11, x20"
]
},
@ -3581,7 +3581,7 @@
"Comment": "0xab",
"ExpectedArm64ASM": [
"strh w4, [x11]",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"add x11, x11, x20, lsl #1"
]
},
@ -3590,7 +3590,7 @@
"Comment": "0xab",
"ExpectedArm64ASM": [
"str w4, [x11]",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"add x11, x11, x20, lsl #2"
]
},
@ -3599,7 +3599,7 @@
"Comment": "0xab",
"ExpectedArm64ASM": [
"str x4, [x11]",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"add x11, x11, x20, lsl #3"
]
},
@ -3608,7 +3608,7 @@
"Comment": "0xaa",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"ldrsb x21, [x28, #714]",
"ldrsb x21, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"tbnz w21, #1, #+0x64",
@ -3669,7 +3669,7 @@
"Comment": "0xab",
"ExpectedArm64ASM": [
"uxth w20, w4",
"ldrsb x21, [x28, #714]",
"ldrsb x21, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"tbnz w21, #1, #+0x64",
@ -3730,7 +3730,7 @@
"Comment": "0xab",
"ExpectedArm64ASM": [
"mov w20, w4",
"ldrsb x21, [x28, #714]",
"ldrsb x21, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"tbnz w21, #1, #+0x64",
@ -3794,7 +3794,7 @@
"0xab"
],
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"tbnz w20, #1, #+0x64",
@ -3856,7 +3856,7 @@
"ExpectedArm64ASM": [
"ldrb w20, [x10]",
"bfxil x4, x20, #0, #8",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"add x10, x10, x20"
]
},
@ -3866,7 +3866,7 @@
"ExpectedArm64ASM": [
"ldrh w20, [x10]",
"bfxil x4, x20, #0, #16",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"add x10, x10, x20, lsl #1"
]
},
@ -3875,7 +3875,7 @@
"Comment": "0xad",
"ExpectedArm64ASM": [
"ldr w4, [x10]",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"add x10, x10, x20, lsl #2"
]
},
@ -3884,7 +3884,7 @@
"Comment": "0xad",
"ExpectedArm64ASM": [
"ldr x4, [x10]",
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"add x10, x10, x20, lsl #3"
]
},
@ -3892,7 +3892,7 @@
"ExpectedInstructionCount": 17,
"Comment": "0xac",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x20",
@ -3915,7 +3915,7 @@
"ExpectedInstructionCount": 17,
"Comment": "0xad",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x20",
@ -3938,7 +3938,7 @@
"ExpectedInstructionCount": 15,
"Comment": "0xad",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x1c",
@ -3959,7 +3959,7 @@
"ExpectedInstructionCount": 15,
"Comment": "0xad",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x1c",
@ -3981,7 +3981,7 @@
"Comment": "0xae",
"ExpectedArm64ASM": [
"ldrb w20, [x11]",
"ldrsb x21, [x28, #714]",
"ldrsb x21, [x28, #986]",
"add x11, x11, x21",
"eor w27, w4, w20",
"lsl w0, w4, #24",
@ -3997,7 +3997,7 @@
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrh w20, [x11]",
"ldrsb x21, [x28, #714]",
"ldrsb x21, [x28, #986]",
"add x11, x11, x21, lsl #1",
"eor w27, w4, w20",
"lsl w0, w4, #16",
@ -4013,7 +4013,7 @@
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldr w20, [x11]",
"ldrsb x21, [x28, #714]",
"ldrsb x21, [x28, #986]",
"add x11, x11, x21, lsl #2",
"eor w27, w4, w20",
"subs w26, w4, w20",
@ -4027,7 +4027,7 @@
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldr x20, [x11]",
"ldrsb x21, [x28, #714]",
"ldrsb x21, [x28, #986]",
"add x11, x11, x21, lsl #3",
"eor w27, w4, w20",
"subs x26, x4, x20",
@ -4040,7 +4040,7 @@
"ExpectedInstructionCount": 29,
"Comment": "0xae",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x38",
@ -4075,7 +4075,7 @@
"ExpectedInstructionCount": 29,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x38",
@ -4110,7 +4110,7 @@
"ExpectedInstructionCount": 25,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x30",
@ -4141,7 +4141,7 @@
"ExpectedInstructionCount": 25,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x30",
@ -4172,7 +4172,7 @@
"ExpectedInstructionCount": 29,
"Comment": "0xae",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x38",
@ -4207,7 +4207,7 @@
"ExpectedInstructionCount": 29,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x38",
@ -4242,7 +4242,7 @@
"ExpectedInstructionCount": 25,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x30",
@ -4273,7 +4273,7 @@
"ExpectedInstructionCount": 25,
"Comment": "0xaf",
"ExpectedArm64ASM": [
"ldrsb x20, [x28, #714]",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
"b #+0x30",
@ -4416,7 +4416,7 @@
"Comment": "0xfc",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"strb w20, [x28, #714]"
"strb w20, [x28, #986]"
]
},
"std": {
@ -4424,7 +4424,7 @@
"Comment": "0xfd",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #714]"
"strb w20, [x28, #986]"
]
}
}

8
unittests/InstructionCountCI/PrimaryGroup.json
View File

@ -2702,7 +2702,7 @@
"mov x0, x6",
"mov x1, x4",
"mov x2, x7",
"ldr x3, [x28, #2448]",
"ldr x3, [x28, #2704]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
@ -2713,7 +2713,7 @@
"mov x0, x6",
"mov x1, x4",
"mov x2, x7",
"ldr x3, [x28, #2464]",
"ldr x3, [x28, #2720]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
@ -2774,7 +2774,7 @@
"mov x0, x6",
"mov x1, x4",
"mov x2, x7",
"ldr x3, [x28, #2456]",
"ldr x3, [x28, #2712]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
@ -2787,7 +2787,7 @@
"mov x0, x6",
"mov x1, x4",
"mov x2, x7",
"ldr x3, [x28, #2472]",
"ldr x3, [x28, #2728]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",

26
unittests/InstructionCountCI/Primary_32Bit.json
View File

@ -15,7 +15,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x06",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #144]",
"ldrh w20, [x28, #928]",
"str w20, [x8, #-4]!"
]
},
@ -25,18 +25,18 @@
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #144]",
"strh w20, [x28, #928]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #160]"
"ldr w20, [x0, #1168]",
"str w20, [x28, #944]"
]
},
"push cs": {
"ExpectedInstructionCount": 2,
"Comment": "0x0e",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #146]",
"ldrh w20, [x28, #930]",
"str w20, [x8, #-4]!"
]
},
@ -44,7 +44,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x16",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #148]",
"ldrh w20, [x28, #932]",
"str w20, [x8, #-4]!"
]
},
@ -54,18 +54,18 @@
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #148]",
"strh w20, [x28, #932]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #168]"
"ldr w20, [x0, #1168]",
"str w20, [x28, #952]"
]
},
"push ds": {
"ExpectedInstructionCount": 2,
"Comment": "0x1e",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #150]",
"ldrh w20, [x28, #934]",
"str w20, [x8, #-4]!"
]
},
@ -75,11 +75,11 @@
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #150]",
"strh w20, [x28, #934]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #172]"
"ldr w20, [x0, #1168]",
"str w20, [x28, #956]"
]
},
"daa": {

16
unittests/InstructionCountCI/RPRES/DDD.json
View File

@ -17,9 +17,9 @@
"0x0f 0x0f 0x86"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d2, [x28, #1056]",
"frecpe v2.2s, v2.2s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pfrsqrtv mm0, mm1": {
@ -28,9 +28,9 @@
"0x0f 0x0f 0x87"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d2, [x28, #1056]",
"frsqrte v2.2s, v2.2s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pfrcp mm0, mm1": {
@ -39,10 +39,10 @@
"0x0f 0x0f 0x96"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d2, [x28, #1056]",
"frecpe s2, s2",
"dup v2.2s, v2.s[0]",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pfrsqrt mm0, mm1": {
@ -51,10 +51,10 @@
"0x0f 0x0f 0x97"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d2, [x28, #1056]",
"frsqrte s2, s2",
"dup v2.2s, v2.s[0]",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
}
}

88
unittests/InstructionCountCI/SSE42_Strings.json
View File

@ -44,11 +44,11 @@
"mov x0, x4",
"mov x1, x6",
"mrs x2, nzcv",
"str w2, [x28, #728]",
"stp x4, x5, [x28, #16]",
"stp x6, x7, [x28, #32]",
"str x8, [x28, #48]",
"stp x16, x17, [x28, #112]",
"str w2, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x2, sp",
"st1 {v2.2d, v3.2d}, [x2], #32",
@ -59,14 +59,14 @@
"mov x4, v17.d[0]",
"mov x5, v17.d[1]",
"mov w6, #0x0",
"ldr x7, [x28, #1552]",
"ldr x7, [x28, #1808]",
"blr x7",
"ldr w4, [x28, #728]",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #16]",
"ldp x6, x7, [x28, #32]",
"ldr x8, [x28, #48]",
"ldp x16, x17, [x28, #112]",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
@ -87,11 +87,11 @@
"mov x0, x4",
"mov x1, x6",
"mrs x2, nzcv",
"str w2, [x28, #728]",
"stp x4, x5, [x28, #16]",
"stp x6, x7, [x28, #32]",
"str x8, [x28, #48]",
"stp x16, x17, [x28, #112]",
"str w2, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x2, sp",
"st1 {v2.2d, v3.2d}, [x2], #32",
@ -102,14 +102,14 @@
"mov x4, v17.d[0]",
"mov x5, v17.d[1]",
"mov w6, #0x0",
"ldr x7, [x28, #1552]",
"ldr x7, [x28, #1808]",
"blr x7",
"ldr w4, [x28, #728]",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #16]",
"ldp x6, x7, [x28, #32]",
"ldr x8, [x28, #48]",
"ldp x16, x17, [x28, #112]",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
@ -135,11 +135,11 @@
],
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #728]",
"stp x4, x5, [x28, #16]",
"stp x6, x7, [x28, #32]",
"str x8, [x28, #48]",
"stp x16, x17, [x28, #112]",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
@ -150,14 +150,14 @@
"mov x2, v17.d[0]",
"mov x3, v17.d[1]",
"mov w4, #0x0",
"ldr x5, [x28, #1560]",
"ldr x5, [x28, #1816]",
"blr x5",
"ldr w4, [x28, #728]",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #16]",
"ldp x6, x7, [x28, #32]",
"ldr x8, [x28, #48]",
"ldp x16, x17, [x28, #112]",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
@ -176,11 +176,11 @@
],
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #728]",
"stp x4, x5, [x28, #16]",
"stp x6, x7, [x28, #32]",
"str x8, [x28, #48]",
"stp x16, x17, [x28, #112]",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
@ -191,14 +191,14 @@
"mov x2, v17.d[0]",
"mov x3, v17.d[1]",
"mov w4, #0x0",
"ldr x5, [x28, #1560]",
"ldr x5, [x28, #1816]",
"blr x5",
"ldr w4, [x28, #728]",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #16]",
"ldp x6, x7, [x28, #32]",
"ldr x8, [x28, #48]",
"ldp x16, x17, [x28, #112]",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",

502
unittests/InstructionCountCI/Secondary.json
View File

File diff suppressed because it is too large Load Diff

254
unittests/InstructionCountCI/SecondaryGroup.json
View File

@ -919,10 +919,10 @@
"Comment": "GROUP9 0xF3 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #728]",
"str x8, [x28, #48]",
"str w0, [x28, #1000]",
"str x8, [x28, #312]",
"mov w0, #0x100",
"str x0, [x28, #1048]",
"str x0, [x28, #1312]",
"sub sp, sp, #0x10 (16)",
"mov w8, #0xa8",
"mov x0, sp",
@ -930,10 +930,10 @@
"svc #0x0",
"ldp w0, w1, [sp]",
"sub sp, sp, #0x10 (16)",
"ldr w8, [x28, #728]",
"ldr w8, [x28, #1000]",
"msr nzcv, x8",
"ldr x8, [x28, #48]",
"str xzr, [x28, #1048]",
"ldr x8, [x28, #312]",
"str xzr, [x28, #1312]",
"orr x20, x0, x1, lsl #12",
"mov w4, w20"
]
@ -943,10 +943,10 @@
"Comment": "GROUP9 0xF3 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #728]",
"str x8, [x28, #48]",
"str w0, [x28, #1000]",
"str x8, [x28, #312]",
"mov w0, #0x100",
"str x0, [x28, #1048]",
"str x0, [x28, #1312]",
"sub sp, sp, #0x10 (16)",
"mov w8, #0xa8",
"mov x0, sp",
@ -954,10 +954,10 @@
"svc #0x0",
"ldp w0, w1, [sp]",
"sub sp, sp, #0x10 (16)",
"ldr w8, [x28, #728]",
"ldr w8, [x28, #1000]",
"msr nzcv, x8",
"ldr x8, [x28, #48]",
"str xzr, [x28, #1048]",
"ldr x8, [x28, #312]",
"str xzr, [x28, #1312]",
"orr x20, x0, x1, lsl #12",
"mov w4, w20"
]
@ -973,9 +973,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"ushr v2.8h, v2.8h, #15",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psrlw mm0, 16": {
@ -983,9 +983,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psrlw xmm0, 0": {
@ -1021,9 +1021,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psraw mm0, 16": {
@ -1031,9 +1031,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psraw xmm0, 0": {
@ -1069,9 +1069,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"shl v2.8h, v2.8h, #15",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psllw mm0, 16": {
@ -1079,9 +1079,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psllw xmm0, 0": {
@ -1117,9 +1117,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"ushr v2.4s, v2.4s, #31",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psrld mm0, 32": {
@ -1127,9 +1127,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psrld xmm0, 0": {
@ -1165,9 +1165,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psrad mm0, 32": {
@ -1175,9 +1175,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psrad xmm0, 0": {
@ -1213,9 +1213,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"shl v2.4s, v2.4s, #31",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pslld mm0, 32": {
@ -1223,9 +1223,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pslld xmm0, 0": {
@ -1261,9 +1261,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"ushr v2.2d, v2.2d, #63",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psrlq mm0, 64": {
@ -1271,9 +1271,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psrlq xmm0, 0": {
@ -1332,9 +1332,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"shl v2.2d, v2.2d, #63",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psllq mm0, 64": {
@ -1342,9 +1342,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psllq xmm0, 0": {
@ -1373,37 +1373,37 @@
"ExpectedInstructionCount": 57,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #1024]",
"ldrh w20, [x28, #1296]",
"strh w20, [x4]",
"mov w20, #0x0",
"ldrb w21, [x28, #747]",
"ldrb w21, [x28, #1019]",
"bfi x20, x21, #11, #3",
"ldrb w21, [x28, #744]",
"ldrb w22, [x28, #745]",
"ldrb w23, [x28, #746]",
"ldrb w24, [x28, #750]",
"ldrb w21, [x28, #1016]",
"ldrb w22, [x28, #1017]",
"ldrb w23, [x28, #1018]",
"ldrb w24, [x28, #1022]",
"orr x20, x20, x21, lsl #8",
"orr x20, x20, x22, lsl #9",
"orr x20, x20, x23, lsl #10",
"orr x20, x20, x24, lsl #14",
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1026]",
"ldrb w20, [x28, #1298]",
"strb w20, [x4, #4]",
"ldr q2, [x28, #768]",
"ldr q2, [x28, #1040]",
"str q2, [x4, #32]",
"ldr q2, [x28, #784]",
"ldr q2, [x28, #1056]",
"str q2, [x4, #48]",
"ldr q2, [x28, #800]",
"ldr q2, [x28, #1072]",
"str q2, [x4, #64]",
"ldr q2, [x28, #816]",
"ldr q2, [x28, #1088]",
"str q2, [x4, #80]",
"ldr q2, [x28, #832]",
"ldr q2, [x28, #1104]",
"str q2, [x4, #96]",
"ldr q2, [x28, #848]",
"ldr q2, [x28, #1120]",
"str q2, [x4, #112]",
"ldr q2, [x28, #864]",
"ldr q2, [x28, #1136]",
"str q2, [x4, #128]",
"ldr q2, [x28, #880]",
"ldr q2, [x28, #1152]",
"str q2, [x4, #144]",
"str q16, [x4, #160]",
"str q17, [x4, #176]",
@ -1436,14 +1436,14 @@
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldr w4, [x28, #184]"
"ldr w4, [x28, #968]"
]
},
"rdfsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldr x4, [x28, #184]"
"ldr x4, [x28, #968]"
]
},
"fxrstor [rax]": {
@ -1451,36 +1451,36 @@
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"strh w20, [x28, #1024]",
"strh w20, [x28, #1296]",
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #747]",
"strb w21, [x28, #1019]",
"ubfx w21, w20, #8, #1",
"ubfx w22, w20, #9, #1",
"ubfx w23, w20, #10, #1",
"ubfx w20, w20, #14, #1",
"strb w21, [x28, #744]",
"strb w22, [x28, #745]",
"strb w23, [x28, #746]",
"strb w20, [x28, #750]",
"strb w21, [x28, #1016]",
"strb w22, [x28, #1017]",
"strb w23, [x28, #1018]",
"strb w20, [x28, #1022]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1026]",
"strb w20, [x28, #1298]",
"ldr q2, [x4, #32]",
"str q2, [x28, #768]",
"str q2, [x28, #1040]",
"ldr q2, [x4, #48]",
"str q2, [x28, #784]",
"str q2, [x28, #1056]",
"ldr q2, [x4, #64]",
"str q2, [x28, #800]",
"str q2, [x28, #1072]",
"ldr q2, [x4, #80]",
"str q2, [x28, #816]",
"str q2, [x28, #1088]",
"ldr q2, [x4, #96]",
"str q2, [x28, #832]",
"str q2, [x28, #1104]",
"ldr q2, [x4, #112]",
"str q2, [x28, #848]",
"str q2, [x28, #1120]",
"ldr q2, [x4, #128]",
"str q2, [x28, #864]",
"str q2, [x28, #1136]",
"ldr q2, [x4, #144]",
"str q2, [x28, #880]",
"str q2, [x28, #1152]",
"ldr q16, [x4, #160]",
"ldr q17, [x4, #176]",
"ldr q18, [x4, #192]",
@ -1512,14 +1512,14 @@
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldr w4, [x28, #176]"
"ldr w4, [x28, #960]"
]
},
"rdgsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldr x4, [x28, #176]"
"ldr x4, [x28, #960]"
]
},
"ldmxcsr [rax]": {
@ -1542,14 +1542,14 @@
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"mov w20, w4",
"str x20, [x28, #184]"
"str x20, [x28, #968]"
]
},
"wrfsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"str x4, [x28, #184]"
"str x4, [x28, #968]"
]
},
"stmxcsr [rax]": {
@ -1570,14 +1570,14 @@
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"mov w20, w4",
"str x20, [x28, #176]"
"str x20, [x28, #960]"
]
},
"wrgsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"str x4, [x28, #176]"
"str x4, [x28, #960]"
]
},
"xsave [rax]": {
@ -1587,37 +1587,37 @@
"ubfx x20, x4, #0, #1",
"cbnz x20, #+0x8",
"b #+0x84",
"ldrh w20, [x28, #1024]",
"ldrh w20, [x28, #1296]",
"strh w20, [x4]",
"mov w20, #0x0",
"ldrb w21, [x28, #747]",
"ldrb w21, [x28, #1019]",
"bfi x20, x21, #11, #3",
"ldrb w21, [x28, #744]",
"ldrb w22, [x28, #745]",
"ldrb w23, [x28, #746]",
"ldrb w24, [x28, #750]",
"ldrb w21, [x28, #1016]",
"ldrb w22, [x28, #1017]",
"ldrb w23, [x28, #1018]",
"ldrb w24, [x28, #1022]",
"orr x20, x20, x21, lsl #8",
"orr x20, x20, x22, lsl #9",
"orr x20, x20, x23, lsl #10",
"orr x20, x20, x24, lsl #14",
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1026]",
"ldrb w20, [x28, #1298]",
"strb w20, [x4, #4]",
"ldr q2, [x28, #768]",
"ldr q2, [x28, #1040]",
"str q2, [x4, #32]",
"ldr q2, [x28, #784]",
"ldr q2, [x28, #1056]",
"str q2, [x4, #48]",
"ldr q2, [x28, #800]",
"ldr q2, [x28, #1072]",
"str q2, [x4, #64]",
"ldr q2, [x28, #816]",
"ldr q2, [x28, #1088]",
"str q2, [x4, #80]",
"ldr q2, [x28, #832]",
"ldr q2, [x28, #1104]",
"str q2, [x4, #96]",
"ldr q2, [x28, #848]",
"ldr q2, [x28, #1120]",
"str q2, [x4, #112]",
"ldr q2, [x28, #864]",
"ldr q2, [x28, #1136]",
"str q2, [x4, #128]",
"ldr q2, [x28, #880]",
"ldr q2, [x28, #1152]",
"str q2, [x4, #144]",
"ubfx x20, x4, #1, #1",
"cbnz x20, #+0x8",
@ -1670,55 +1670,55 @@
"cbnz x20, #+0x8",
"b #+0x84",
"ldrh w20, [x4]",
"strh w20, [x28, #1024]",
"strh w20, [x28, #1296]",
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #747]",
"strb w21, [x28, #1019]",
"ubfx w21, w20, #8, #1",
"ubfx w22, w20, #9, #1",
"ubfx w23, w20, #10, #1",
"ubfx w20, w20, #14, #1",
"strb w21, [x28, #744]",
"strb w22, [x28, #745]",
"strb w23, [x28, #746]",
"strb w20, [x28, #750]",
"strb w21, [x28, #1016]",
"strb w22, [x28, #1017]",
"strb w23, [x28, #1018]",
"strb w20, [x28, #1022]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1026]",
"strb w20, [x28, #1298]",
"ldr q2, [x4, #32]",
"str q2, [x28, #768]",
"str q2, [x28, #1040]",
"ldr q2, [x4, #48]",
"str q2, [x28, #784]",
"str q2, [x28, #1056]",
"ldr q2, [x4, #64]",
"str q2, [x28, #800]",
"str q2, [x28, #1072]",
"ldr q2, [x4, #80]",
"str q2, [x28, #816]",
"str q2, [x28, #1088]",
"ldr q2, [x4, #96]",
"str q2, [x28, #832]",
"str q2, [x28, #1104]",
"ldr q2, [x4, #112]",
"str q2, [x28, #848]",
"str q2, [x28, #1120]",
"ldr q2, [x4, #128]",
"str q2, [x28, #864]",
"str q2, [x28, #1136]",
"ldr q2, [x4, #144]",
"str q2, [x28, #880]",
"str q2, [x28, #1152]",
"b #+0x4c",
"mov w20, #0x0",
"mov w21, #0x37f",
"strh w21, [x28, #1024]",
"strb w20, [x28, #747]",
"strb w20, [x28, #744]",
"strb w20, [x28, #745]",
"strb w20, [x28, #746]",
"strb w20, [x28, #750]",
"strb w20, [x28, #1026]",
"strh w21, [x28, #1296]",
"strb w20, [x28, #1019]",
"strb w20, [x28, #1016]",
"strb w20, [x28, #1017]",
"strb w20, [x28, #1018]",
"strb w20, [x28, #1022]",
"strb w20, [x28, #1298]",
"movi v2.2d, #0x0",
"str q2, [x28, #768]",
"str q2, [x28, #784]",
"str q2, [x28, #800]",
"str q2, [x28, #816]",
"str q2, [x28, #832]",
"str q2, [x28, #848]",
"str q2, [x28, #864]",
"str q2, [x28, #880]",
"str q2, [x28, #1040]",
"str q2, [x28, #1056]",
"str q2, [x28, #1072]",
"str q2, [x28, #1088]",
"str q2, [x28, #1104]",
"str q2, [x28, #1120]",
"str q2, [x28, #1136]",
"str q2, [x28, #1152]",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #1, #1",
"cbnz x20, #+0x8",

64
unittests/InstructionCountCI/SecondaryModRM.json
View File

@ -25,43 +25,43 @@
"st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x3], #64",
"str x30, [x3]",
"mrs x3, nzcv",
"str w3, [x28, #728]",
"stp x4, x5, [x28, #16]",
"stp x6, x7, [x28, #32]",
"stp x8, x9, [x28, #48]",
"stp x10, x11, [x28, #64]",
"stp x12, x13, [x28, #80]",
"stp x14, x15, [x28, #96]",
"stp x16, x17, [x28, #112]",
"stp x19, x29, [x28, #128]",
"str x26, [x28, #752]",
"str x27, [x28, #760]",
"add x3, x28, #0xc0 (192)",
"str w3, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
"stp x14, x15, [x28, #360]",
"stp x16, x17, [x28, #376]",
"stp x19, x29, [x28, #392]",
"str x26, [x28, #1024]",
"str x27, [x28, #1032]",
"add x3, x28, #0x1a0 (416)",
"st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x3], #64",
"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x3], #64",
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x3], #64",
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x3], #64",
"mov w1, w5",
"ldr x0, [x28, #1112]",
"ldr x2, [x28, #1128]",
"ldr x0, [x28, #1368]",
"ldr x2, [x28, #1384]",
"blr x2",
"ldr w4, [x28, #728]",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"add x4, x28, #0xc0 (192)",
"add x4, x28, #0x1a0 (416)",
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #16]",
"ldp x6, x7, [x28, #32]",
"ldp x8, x9, [x28, #48]",
"ldp x10, x11, [x28, #64]",
"ldp x12, x13, [x28, #80]",
"ldp x14, x15, [x28, #96]",
"ldp x16, x17, [x28, #112]",
"ldp x19, x29, [x28, #128]",
"ldr x26, [x28, #752]",
"ldr x27, [x28, #760]",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
"ldp x14, x15, [x28, #360]",
"ldp x16, x17, [x28, #376]",
"ldp x19, x29, [x28, #392]",
"ldr x26, [x28, #1024]",
"ldr x27, [x28, #1032]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
@ -82,10 +82,10 @@
"lsl w4, w20, #7",
"lsr x6, x20, #25",
"mrs x0, nzcv",
"str w0, [x28, #728]",
"str x8, [x28, #48]",
"str w0, [x28, #1000]",
"str x8, [x28, #312]",
"mov w0, #0x100",
"str x0, [x28, #1048]",
"str x0, [x28, #1312]",
"sub sp, sp, #0x10 (16)",
"mov w8, #0xa8",
"mov x0, sp",
@ -93,10 +93,10 @@
"svc #0x0",
"ldp w0, w1, [sp]",
"sub sp, sp, #0x10 (16)",
"ldr w8, [x28, #728]",
"ldr w8, [x28, #1000]",
"msr nzcv, x8",
"ldr x8, [x28, #48]",
"str xzr, [x28, #1048]",
"ldr x8, [x28, #312]",
"str xzr, [x28, #1312]",
"orr x5, x0, x1, lsl #12"
]
},

16
unittests/InstructionCountCI/Secondary_32Bit.json
View File

@ -13,7 +13,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xa0",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #154]",
"ldrh w20, [x28, #938]",
"str w20, [x8, #-4]!"
]
},
@ -23,18 +23,18 @@
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #154]",
"strh w20, [x28, #938]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #184]"
"ldr w20, [x0, #1168]",
"str w20, [x28, #968]"
]
},
"push gs": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xa8",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #152]",
"ldrh w20, [x28, #936]",
"str w20, [x8, #-4]!"
]
},
@ -44,11 +44,11 @@
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #152]",
"strh w20, [x28, #936]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #176]"
"ldr w20, [x0, #1168]",
"str w20, [x28, #960]"
]
}
}

14
unittests/InstructionCountCI/Secondary_OpSize.json
View File

@ -110,7 +110,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0x66 0x0f 0x2a",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #1040]",
"sxtl v2.2d, v2.2s",
"scvtf v16.2d, v2.2d"
]
@ -128,7 +128,7 @@
"ExpectedArm64ASM": [
"fcvtn v2.2s, v16.2d",
"fcvtzs v2.2s, v2.2s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"cvtpd2pi mm0, xmm0": {
@ -138,7 +138,7 @@
"fcvtn v2.2s, v16.2d",
"frinti v2.2s, v2.2s",
"fcvtzs v2.2s, v2.2s",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"ucomisd xmm0, xmm1": {
@ -523,7 +523,7 @@
"0x66 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1760]",
"ldr x0, [x28, #2016]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@ -537,7 +537,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"ldr x0, [x28, #1760]",
"ldr x0, [x28, #2016]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v2.16b}, v3.16b"
]
@ -1015,7 +1015,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0x66 0x0f 0xd0",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2128]",
"ldr q2, [x28, #2384]",
"eor v2.16b, v17.16b, v2.16b",
"fadd v16.2d, v16.2d, v2.2d"
]
@ -1071,7 +1071,7 @@
"ExpectedInstructionCount": 7,
"Comment": "0x66 0x0f 0xd7",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2288]",
"ldr q2, [x28, #2544]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",

4
unittests/InstructionCountCI/Secondary_REP.json
View File

@ -354,7 +354,7 @@
"0xf3 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1752]",
"ldr x0, [x28, #2008]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@ -611,7 +611,7 @@
"ExpectedInstructionCount": 1,
"Comment": "0xf3 0x0f 0xd6",
"ExpectedArm64ASM": [
"ldr d16, [x28, #768]"
"ldr d16, [x28, #1040]"
]
},
"cvtdq2pd xmm0, xmm1": {

6
unittests/InstructionCountCI/Secondary_REPNE.json
View File

@ -296,7 +296,7 @@
"0xf2 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1744]",
"ldr x0, [x28, #2000]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@ -452,7 +452,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0xf2 0x0f 0xd0",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2096]",
"ldr q2, [x28, #2352]",
"eor v2.16b, v17.16b, v2.16b",
"fadd v16.4s, v16.4s, v2.4s"
]
@ -461,7 +461,7 @@
"ExpectedInstructionCount": 1,
"Comment": "0xf2 0x0f 0xd6",
"ExpectedArm64ASM": [
"str d16, [x28, #768]"
"str d16, [x28, #1040]"
]
},
"cvtpd2dq xmm0, xmm1": {

48
unittests/InstructionCountCI/Secondary_SVE128.json
View File

@ -36,80 +36,80 @@
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xd1",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"lsr z2.h, p6/m, z2.h, z3.d",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psrld mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xd2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"lsr z2.s, p6/m, z2.s, z3.d",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psrlq mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xd3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"lsr z2.d, p6/m, z2.d, z3.d",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psraw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xe1",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"asr z2.h, p6/m, z2.h, z3.d",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psrad mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xe2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"asr z2.s, p6/m, z2.s, z3.d",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psllw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xf1",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"lsl z2.h, p6/m, z2.h, z3.d",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"pslld mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xf2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"lsl z2.s, p6/m, z2.s, z3.d",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
},
"psllq mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xf3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #1056]",
"lsl z2.d, p6/m, z2.d, z3.d",
"str d2, [x28, #768]"
"str d2, [x28, #1040]"
]
}
}

18
unittests/InstructionCountCI/VEX_map1.json
View File

@ -2749,7 +2749,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1768]",
"ldr x0, [x28, #2024]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@ -2818,7 +2818,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1768]",
"ldr x0, [x28, #2024]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@ -2887,7 +2887,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1768]",
"ldr x0, [x28, #2024]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@ -4332,7 +4332,7 @@
"Map 1 0b01 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2128]",
"ldr q2, [x28, #2384]",
"eor v2.16b, v18.16b, v2.16b",
"fadd v16.2d, v17.2d, v2.2d"
]
@ -4343,7 +4343,7 @@
"Map 1 0b01 0xd0 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1600]",
"ldr x0, [x28, #1856]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"fadd z16.d, z17.d, z2.d"
@ -4355,7 +4355,7 @@
"Map 1 0b11 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2096]",
"ldr q2, [x28, #2352]",
"eor v2.16b, v18.16b, v2.16b",
"fadd v16.4s, v17.4s, v2.4s"
]
@ -4366,7 +4366,7 @@
"Map 1 0b11 0xd0 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1584]",
"ldr x0, [x28, #1840]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"fadd z16.s, z17.s, z2.s"
@ -4492,7 +4492,7 @@
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2288]",
"ldr q2, [x28, #2544]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",
@ -4507,7 +4507,7 @@
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1680]",
"ldr x0, [x28, #1936]",
"ld1b {z2.b}, p7/z, [x0]",
"mrs x0, nzcv",
"mov z0.d, #0",

2
unittests/InstructionCountCI/VEX_map2.json
View File

@ -1575,7 +1575,7 @@
"Map 2 0b01 0x41 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2064]",
"ldr q2, [x28, #2320]",
"zip1 v3.8h, v2.8h, v17.8h",
"zip2 v2.8h, v2.8h, v17.8h",
"umin v2.4s, v3.4s, v2.4s",

4
unittests/InstructionCountCI/VEX_map3.json
View File

@ -4796,7 +4796,7 @@
"Map 3 0b01 0xdf 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2176]",
"ldr q2, [x28, #2432]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
@ -4809,7 +4809,7 @@
"Map 3 0b01 0xdf 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2176]",
"ldr q2, [x28, #2432]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",

11448
unittests/InstructionCountCI/x87.json
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5218
unittests/InstructionCountCI/x87_f64.json
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