From 2abac03ab0d6b8fd689694747e7a5a16d3e40d36 Mon Sep 17 00:00:00 2001
From: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Date: Wed, 3 Apr 2024 13:21:23 -0400
Subject: [PATCH] OpcodeDispatcher: add LoadConstantShift helper

shows up a bunch

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
---
 FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 13 +++++++++++++
 FEXCore/Source/Interface/Core/OpcodeDispatcher.h   |  1 +
 2 files changed, 14 insertions(+)

diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index 7cd27b25e..e61afb266 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -1546,6 +1546,19 @@ void OpDispatchBuilder::CPUIDOp(OpcodeArgs) {
   StoreGPRRegister(X86State::REG_RCX, _Bfe(OpSize::i64Bit, 32, 0,  Result_Upper));
 }
 
+uint32_t OpDispatchBuilder::LoadConstantShift(X86Tables::DecodedOp Op, bool Is1Bit) {
+  if (Is1Bit) {
+    return 1;
+  } else {
+    // x86 masks the shift by 0x3F or 0x1F depending on size of op
+    const uint32_t Size = GetSrcBitSize(Op);
+    uint64_t Mask = Size == 64 ? 0x3F : 0x1F;
+
+    LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
+    return Op->Src[1].Data.Literal.Value & Mask;
+  }
+}
+
 void OpDispatchBuilder::XGetBVOp(OpcodeArgs) {
   OrderedNode *Function = LoadGPRRegister(X86State::REG_RCX);
 
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h
index 46a268137..761464cae 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h
@@ -329,6 +329,7 @@ public:
   void CMOVOp(OpcodeArgs);
   void CPUIDOp(OpcodeArgs);
   void XGetBVOp(OpcodeArgs);
+  uint32_t LoadConstantShift(X86Tables::DecodedOp Op, bool Is1Bit);
   template<bool SHL1Bit>
   void SHLOp(OpcodeArgs);
   void SHLImmediateOp(OpcodeArgs);