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InstCountCI: Update

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig 2024-09-08 10:27:20 -04:00
parent 39cc1e5116
commit 2b0041a291
6 changed files with 350 additions and 370 deletions
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224
unittests/InstructionCountCI/Atomics.json
View File

@ -687,13 +687,12 @@
]
},
"lock adc byte [rax], 1": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 17,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cinc w20, w20, lo",
"ldaddalb w20, w27, [x4]",
"mov w20, #0x1",
"cinc w21, w20, lo",
"ldaddalb w21, w27, [x4]",
"cinc w20, w20, lo",
"add w21, w27, w20",
"uxtb w26, w21",
@ -711,38 +710,36 @@
]
},
"lock adc byte [rax], 0xFF": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"cinc w21, w20, lo",
"ldaddalb w21, w21, [x4]",
"mvn w27, w21",
"cinc w20, w20, lo",
"ldaddalb w20, w20, [x4]",
"mvn w27, w20",
"mov w21, #0xff",
"cinc w21, w21, lo",
"add w22, w20, w21",
"add w22, w21, w20",
"uxtb w26, w22",
"cmp w26, w21",
"cset x21, hs",
"cmp w26, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, #0xff",
"eor w20, w26, w20",
"bic w20, w20, w22",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"orr w20, w22, w20, lsl #29",
"eor w22, w21, #0xff",
"eor w21, w26, w21",
"bic w21, w21, w22",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock adc word [rax], 0x100": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 17,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cinc w20, w20, lo",
"ldaddalh w20, w27, [x4]",
"mov w20, #0x100",
"cinc w21, w20, lo",
"ldaddalh w21, w27, [x4]",
"cinc w20, w20, lo",
"add w21, w27, w20",
"uxth w26, w21",
@ -760,27 +757,26 @@
]
},
"lock adc word [rax], 0xFFFF": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"cinc w21, w20, lo",
"ldaddalh w21, w21, [x4]",
"mvn w27, w21",
"cinc w20, w20, lo",
"ldaddalh w20, w20, [x4]",
"mvn w27, w20",
"mov w21, #0xffff",
"cinc w21, w21, lo",
"add w22, w20, w21",
"add w22, w21, w20",
"uxth w26, w22",
"cmp w26, w21",
"cset x21, hs",
"cmp w26, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, #0xffff",
"eor w20, w26, w20",
"bic w20, w20, w22",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"orr w20, w22, w20, lsl #29",
"eor w22, w21, #0xffff",
"eor w21, w26, w21",
"bic w21, w21, w22",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
@ -850,13 +846,12 @@
]
},
"lock adc word [rax], 1": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 17,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cinc w20, w20, lo",
"ldaddalh w20, w27, [x4]",
"mov w20, #0x1",
"cinc w21, w20, lo",
"ldaddalh w21, w27, [x4]",
"cinc w20, w20, lo",
"add w21, w27, w20",
"uxth w26, w21",
@ -906,108 +901,104 @@
]
},
"lock sbb byte [rax], 1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 19,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cinc w20, w20, lo",
"neg w1, w20",
"cinc w21, w20, lo",
"neg w1, w21",
"ldaddalb w1, w27, [x4]",
"uxtb w20, w27",
"mov w21, #0x1",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"uxtb w21, w27",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxtb w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, #0x1",
"eor w20, w26, w20",
"and w20, w20, w22",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"orr w20, w22, w20, lsl #29",
"eor w22, w21, #0x1",
"eor w21, w26, w21",
"and w21, w21, w22",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb byte [rax], 0xFF": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 20,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"cinc w21, w20, lo",
"neg w1, w21",
"ldaddalb w1, w21, [x4]",
"mvn w27, w21",
"uxtb w21, w21",
"cinc w20, w20, lo",
"neg w1, w20",
"ldaddalb w1, w20, [x4]",
"mvn w27, w20",
"uxtb w20, w20",
"mov w21, #0xff",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"sub w22, w21, w20",
"uxtb w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, #0xff",
"eor w20, w26, w20",
"and w20, w20, w22",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"orr w20, w22, w20, lsl #29",
"eor w22, w21, #0xff",
"eor w21, w26, w21",
"and w21, w21, w22",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb word [rax], 0x100": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 19,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cinc w20, w20, lo",
"neg w1, w20",
"cinc w21, w20, lo",
"neg w1, w21",
"ldaddalh w1, w27, [x4]",
"uxth w20, w27",
"mov w21, #0x100",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"uxth w21, w27",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxth w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, #0x100",
"eor w20, w26, w20",
"and w20, w20, w22",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"orr w20, w22, w20, lsl #29",
"eor w22, w21, #0x100",
"eor w21, w26, w21",
"and w21, w21, w22",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb word [rax], 0xFFFF": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 20,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"cinc w21, w20, lo",
"neg w1, w21",
"ldaddalh w1, w21, [x4]",
"mvn w27, w21",
"uxth w21, w21",
"cinc w20, w20, lo",
"neg w1, w20",
"ldaddalh w1, w20, [x4]",
"mvn w27, w20",
"uxth w20, w20",
"mov w21, #0xffff",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"sub w22, w21, w20",
"uxth w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, #0xffff",
"eor w20, w26, w20",
"and w20, w20, w22",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"orr w20, w22, w20, lsl #29",
"eor w22, w21, #0xffff",
"eor w21, w26, w21",
"and w21, w21, w22",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
@ -1057,28 +1048,27 @@
]
},
"lock sbb word [rax], 1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 19,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cinc w20, w20, lo",
"neg w1, w20",
"cinc w21, w20, lo",
"neg w1, w21",
"ldaddalh w1, w27, [x4]",
"uxth w20, w27",
"mov w21, #0x1",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"uxth w21, w27",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxth w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, #0x1",
"eor w20, w26, w20",
"and w20, w20, w22",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"orr w20, w22, w20, lsl #29",
"eor w22, w21, #0x1",
"eor w21, w26, w21",
"and w21, w21, w22",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},

196
unittests/InstructionCountCI/FlagM/Atomics.json
View File

@ -580,13 +580,12 @@
]
},
"lock adc byte [rax], 1": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 14,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cinc w20, w20, lo",
"ldaddalb w20, w27, [x4]",
"mov w20, #0x1",
"cinc w21, w20, lo",
"ldaddalb w21, w27, [x4]",
"cinc w20, w20, lo",
"add w21, w27, w20",
"uxtb w26, w21",
@ -601,35 +600,33 @@
]
},
"lock adc byte [rax], 0xFF": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 15,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"cinc w21, w20, lo",
"ldaddalb w21, w21, [x4]",
"mvn w27, w21",
"cinc w20, w20, lo",
"ldaddalb w20, w20, [x4]",
"mvn w27, w20",
"mov w21, #0xff",
"cinc w21, w21, lo",
"add w22, w20, w21",
"add w22, w21, w20",
"uxtb w26, w22",
"cmp w26, w21",
"cset x21, hs",
"cmp w26, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x21, #63, #nzCv",
"eor w21, w20, #0xff",
"eor w20, w26, w20",
"bic w20, w20, w21",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0xff",
"eor w21, w26, w21",
"bic w20, w21, w20",
"rmif x20, #7, #nzcV"
]
},
"lock adc word [rax], 0x100": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 14,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cinc w20, w20, lo",
"ldaddalh w20, w27, [x4]",
"mov w20, #0x100",
"cinc w21, w20, lo",
"ldaddalh w21, w27, [x4]",
"cinc w20, w20, lo",
"add w21, w27, w20",
"uxth w26, w21",
@ -644,24 +641,23 @@
]
},
"lock adc word [rax], 0xFFFF": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 15,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"cinc w21, w20, lo",
"ldaddalh w21, w21, [x4]",
"mvn w27, w21",
"cinc w20, w20, lo",
"ldaddalh w20, w20, [x4]",
"mvn w27, w20",
"mov w21, #0xffff",
"cinc w21, w21, lo",
"add w22, w20, w21",
"add w22, w21, w20",
"uxth w26, w22",
"cmp w26, w21",
"cset x21, hs",
"cmp w26, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x21, #63, #nzCv",
"eor w21, w20, #0xffff",
"eor w20, w26, w20",
"bic w20, w20, w21",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0xffff",
"eor w21, w26, w21",
"bic w20, w21, w20",
"rmif x20, #15, #nzcV"
]
},
@ -715,13 +711,12 @@
]
},
"lock adc word [rax], 1": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 14,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cinc w20, w20, lo",
"ldaddalh w20, w27, [x4]",
"mov w20, #0x1",
"cinc w21, w20, lo",
"ldaddalh w21, w27, [x4]",
"cinc w20, w20, lo",
"add w21, w27, w20",
"uxth w26, w21",
@ -760,96 +755,92 @@
]
},
"lock sbb byte [rax], 1": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 16,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cinc w20, w20, lo",
"neg w1, w20",
"cinc w21, w20, lo",
"neg w1, w21",
"ldaddalb w1, w27, [x4]",
"uxtb w20, w27",
"mov w21, #0x1",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"uxtb w21, w27",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxtb w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x21, #63, #nzCv",
"eor w21, w20, #0x1",
"eor w20, w26, w20",
"and w20, w20, w21",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0x1",
"eor w21, w26, w21",
"and w20, w21, w20",
"rmif x20, #7, #nzcV"
]
},
"lock sbb byte [rax], 0xFF": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 17,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"cinc w21, w20, lo",
"neg w1, w21",
"ldaddalb w1, w21, [x4]",
"mvn w27, w21",
"uxtb w21, w21",
"cinc w20, w20, lo",
"neg w1, w20",
"ldaddalb w1, w20, [x4]",
"mvn w27, w20",
"uxtb w20, w20",
"mov w21, #0xff",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"sub w22, w21, w20",
"uxtb w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x21, #63, #nzCv",
"eor w21, w20, #0xff",
"eor w20, w26, w20",
"and w20, w20, w21",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0xff",
"eor w21, w26, w21",
"and w20, w21, w20",
"rmif x20, #7, #nzcV"
]
},
"lock sbb word [rax], 0x100": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 16,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cinc w20, w20, lo",
"neg w1, w20",
"cinc w21, w20, lo",
"neg w1, w21",
"ldaddalh w1, w27, [x4]",
"uxth w20, w27",
"mov w21, #0x100",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"uxth w21, w27",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxth w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x21, #63, #nzCv",
"eor w21, w20, #0x100",
"eor w20, w26, w20",
"and w20, w20, w21",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0x100",
"eor w21, w26, w21",
"and w20, w21, w20",
"rmif x20, #15, #nzcV"
]
},
"lock sbb word [rax], 0xFFFF": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 17,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"cinc w21, w20, lo",
"neg w1, w21",
"ldaddalh w1, w21, [x4]",
"mvn w27, w21",
"uxth w21, w21",
"cinc w20, w20, lo",
"neg w1, w20",
"ldaddalh w1, w20, [x4]",
"mvn w27, w20",
"uxth w20, w20",
"mov w21, #0xffff",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"sub w22, w21, w20",
"uxth w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x21, #63, #nzCv",
"eor w21, w20, #0xffff",
"eor w20, w26, w20",
"and w20, w20, w21",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0xffff",
"eor w21, w26, w21",
"and w20, w21, w20",
"rmif x20, #15, #nzcV"
]
},
@ -899,25 +890,24 @@
]
},
"lock sbb word [rax], 1": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 16,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cinc w20, w20, lo",
"neg w1, w20",
"cinc w21, w20, lo",
"neg w1, w21",
"ldaddalh w1, w27, [x4]",
"uxth w20, w27",
"mov w21, #0x1",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"uxth w21, w27",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxth w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x21, #63, #nzCv",
"eor w21, w20, #0x1",
"eor w20, w26, w20",
"and w20, w20, w21",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0x1",
"eor w21, w26, w21",
"and w20, w21, w20",
"rmif x20, #15, #nzcV"
]
},

96
unittests/InstructionCountCI/FlagM/Primary.json
View File

@ -593,8 +593,8 @@
"ExpectedInstructionCount": 14,
"Comment": "0x14",
"ExpectedArm64ASM": [
"mvn w27, w4",
"mov w20, #0xff",
"mvn w27, w4",
"cinc w20, w20, lo",
"add w21, w4, w20",
"uxtb w26, w21",
@ -613,8 +613,8 @@
"ExpectedInstructionCount": 14,
"Comment": "0x15",
"ExpectedArm64ASM": [
"mvn w27, w4",
"mov w20, #0xffff",
"mvn w27, w4",
"cinc w20, w20, lo",
"add w21, w4, w20",
"uxth w26, w21",
@ -789,18 +789,18 @@
"ExpectedInstructionCount": 17,
"Comment": "0x1C",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"mov w21, #0x1",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"mov w20, #0x1",
"uxtb w21, w4",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxtb w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x21, #63, #nzCv",
"eor w21, w20, #0x1",
"eor w20, w26, w20",
"and w20, w20, w21",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0x1",
"eor w21, w26, w21",
"and w20, w21, w20",
"rmif x20, #7, #nzcV",
"mov x20, x4",
"bfxil x20, x26, #0, #8",
@ -812,18 +812,18 @@
"ExpectedInstructionCount": 17,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov w21, #0x1",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"mov w20, #0x1",
"uxth w21, w4",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxth w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x21, #63, #nzCv",
"eor w21, w20, #0x1",
"eor w20, w26, w20",
"and w20, w20, w21",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0x1",
"eor w21, w26, w21",
"and w20, w21, w20",
"rmif x20, #15, #nzcV",
"mov x20, x4",
"bfxil x20, x26, #0, #16",
@ -855,19 +855,19 @@
"ExpectedInstructionCount": 15,
"Comment": "0x1C",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"mvn w27, w4",
"uxtb w20, w4",
"mov w21, #0xff",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"uxtb w21, w4",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxtb w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x21, #63, #nzCv",
"eor w21, w20, #0xff",
"eor w20, w26, w20",
"and w20, w20, w21",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0xff",
"eor w21, w26, w21",
"and w20, w21, w20",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
@ -876,19 +876,19 @@
"ExpectedInstructionCount": 15,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"mvn w27, w4",
"uxth w20, w4",
"mov w21, #0xffff",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"uxth w21, w4",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxth w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x21, #63, #nzCv",
"eor w21, w20, #0xffff",
"eor w20, w26, w20",
"and w20, w20, w21",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0xffff",
"eor w21, w26, w21",
"and w20, w21, w20",
"rmif x20, #15, #nzcV",
"bfxil x4, x26, #0, #16"
]
@ -1587,9 +1587,9 @@
"ExpectedInstructionCount": 8,
"Comment": "0x69",
"ExpectedArm64ASM": [
"sxth x20, w6",
"mov w21, #0x101",
"mul x20, x20, x21",
"mov w20, #0x101",
"sxth x21, w6",
"mul x20, x21, x20",
"sbfx x21, x20, #16, #16",
"bfxil x4, x20, #0, #16",
"sbfx x20, x20, #15, #1",
@ -1626,9 +1626,9 @@
"ExpectedInstructionCount": 8,
"Comment": "0x6b",
"ExpectedArm64ASM": [
"sxth x20, w6",
"mov w21, #0x3",
"mul x20, x20, x21",
"mov w20, #0x3",
"sxth x21, w6",
"mul x20, x21, x20",
"sbfx x21, x20, #16, #16",
"bfxil x4, x20, #0, #16",
"sbfx x20, x20, #15, #1",

42
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
View File

@ -63,18 +63,18 @@
"ExpectedInstructionCount": 17,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"mov w21, #0x1",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"mov w20, #0x1",
"uxtb w21, w4",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxtb w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x21, #63, #nzCv",
"eor w21, w20, #0x1",
"eor w20, w26, w20",
"and w20, w20, w21",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0x1",
"eor w21, w26, w21",
"and w20, w21, w20",
"rmif x20, #7, #nzcV",
"mov x20, x4",
"bfxil x20, x26, #0, #8",
@ -154,8 +154,8 @@
"ExpectedInstructionCount": 14,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mvn w27, w4",
"mov w20, #0xff",
"mvn w27, w4",
"cinc w20, w20, lo",
"add w21, w4, w20",
"uxtb w26, w21",
@ -174,19 +174,19 @@
"ExpectedInstructionCount": 15,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"mvn w27, w4",
"uxtb w20, w4",
"mov w21, #0xff",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"uxtb w21, w4",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxtb w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x21, #63, #nzCv",
"eor w21, w20, #0xff",
"eor w20, w26, w20",
"and w20, w20, w21",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0xff",
"eor w21, w26, w21",
"and w20, w21, w20",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]

112
unittests/InstructionCountCI/Primary.json
View File

@ -684,8 +684,8 @@
"ExpectedInstructionCount": 17,
"Comment": "0x14",
"ExpectedArm64ASM": [
"mvn w27, w4",
"mov w20, #0xff",
"mvn w27, w4",
"cinc w20, w20, lo",
"add w21, w4, w20",
"uxtb w26, w21",
@ -707,8 +707,8 @@
"ExpectedInstructionCount": 17,
"Comment": "0x15",
"ExpectedArm64ASM": [
"mvn w27, w4",
"mov w20, #0xffff",
"mvn w27, w4",
"cinc w20, w20, lo",
"add w21, w4, w20",
"uxth w26, w21",
@ -906,21 +906,21 @@
"ExpectedInstructionCount": 20,
"Comment": "0x1C",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"mov w21, #0x1",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"mov w20, #0x1",
"uxtb w21, w4",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxtb w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, #0x1",
"eor w20, w26, w20",
"and w20, w20, w22",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"orr w20, w22, w20, lsl #29",
"eor w22, w21, #0x1",
"eor w21, w26, w21",
"and w21, w21, w22",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"mov x21, x4",
"bfxil x21, x26, #0, #8",
"msr nzcv, x20",
@ -932,21 +932,21 @@
"ExpectedInstructionCount": 20,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov w21, #0x1",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"mov w20, #0x1",
"uxth w21, w4",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxth w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, #0x1",
"eor w20, w26, w20",
"and w20, w20, w22",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"orr w20, w22, w20, lsl #29",
"eor w22, w21, #0x1",
"eor w21, w26, w21",
"and w21, w21, w22",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"mov x21, x4",
"bfxil x21, x26, #0, #16",
"msr nzcv, x20",
@ -978,22 +978,22 @@
"ExpectedInstructionCount": 18,
"Comment": "0x1C",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"mvn w27, w4",
"uxtb w20, w4",
"mov w21, #0xff",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"uxtb w21, w4",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxtb w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, #0xff",
"eor w20, w26, w20",
"and w20, w20, w22",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"orr w20, w22, w20, lsl #29",
"eor w22, w21, #0xff",
"eor w21, w26, w21",
"and w21, w21, w22",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
]
@ -1002,22 +1002,22 @@
"ExpectedInstructionCount": 18,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"mvn w27, w4",
"uxth w20, w4",
"mov w21, #0xffff",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"uxth w21, w4",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxth w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, #0xffff",
"eor w20, w26, w20",
"and w20, w20, w22",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"orr w20, w22, w20, lsl #29",
"eor w22, w21, #0xffff",
"eor w21, w26, w21",
"and w21, w21, w22",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x4, x26, #0, #16",
"msr nzcv, x20"
]
@ -1816,9 +1816,9 @@
"ExpectedInstructionCount": 8,
"Comment": "0x69",
"ExpectedArm64ASM": [
"sxth x20, w6",
"mov w21, #0x101",
"mul x20, x20, x21",
"mov w20, #0x101",
"sxth x21, w6",
"mul x20, x21, x20",
"sbfx x21, x20, #16, #16",
"bfxil x4, x20, #0, #16",
"sbfx x20, x20, #15, #1",
@ -1879,9 +1879,9 @@
"ExpectedInstructionCount": 8,
"Comment": "0x6b",
"ExpectedArm64ASM": [
"sxth x20, w6",
"mov w21, #0x3",
"mul x20, x20, x21",
"mov w20, #0x3",
"sxth x21, w6",
"mul x20, x21, x20",
"sbfx x21, x20, #16, #16",
"bfxil x4, x20, #0, #16",
"sbfx x20, x20, #15, #1",

50
unittests/InstructionCountCI/PrimaryGroup.json
View File

@ -73,21 +73,21 @@
"ExpectedInstructionCount": 20,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"mov w21, #0x1",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"mov w20, #0x1",
"uxtb w21, w4",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxtb w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, #0x1",
"eor w20, w26, w20",
"and w20, w20, w22",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"orr w20, w22, w20, lsl #29",
"eor w22, w21, #0x1",
"eor w21, w26, w21",
"and w21, w21, w22",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"mov x21, x4",
"bfxil x21, x26, #0, #8",
"msr nzcv, x20",
@ -175,8 +175,8 @@
"ExpectedInstructionCount": 17,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mvn w27, w4",
"mov w20, #0xff",
"mvn w27, w4",
"cinc w20, w20, lo",
"add w21, w4, w20",
"uxtb w26, w21",
@ -198,22 +198,22 @@
"ExpectedInstructionCount": 18,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"mvn w27, w4",
"uxtb w20, w4",
"mov w21, #0xff",
"cinc w21, w21, lo",
"sub w22, w20, w21",
"uxtb w21, w4",
"cinc w20, w20, lo",
"sub w22, w21, w20",
"uxtb w26, w22",
"cmp w20, w21",
"cset x21, hs",
"cmp w21, w20",
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, #0xff",
"eor w20, w26, w20",
"and w20, w20, w22",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"orr w20, w22, w20, lsl #29",
"eor w22, w21, #0xff",
"eor w21, w26, w21",
"and w21, w21, w22",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
]