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OpcodeDispatcher: Remove unnecessary moves from AVXVariableShiftImpl

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We already zero-extend on a store if necessary.
This commit is contained in:
Lioncache 2023-08-22 21:18:41 -04:00
parent 1f2c5fc6c6
commit 2b071e282e
2 changed files with 6 additions and 18 deletions
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9
FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
View File

@ -1870,20 +1870,13 @@ void OpDispatchBuilder::AVXVariableShiftImpl(OpcodeArgs, IROps IROp) {
const auto DstSize = GetDstSize(Op);
const auto SrcSize = GetSrcSize(Op);
const auto Is128Bit = DstSize == Core::CPUState::XMM_SSE_REG_SIZE;
OrderedNode *Vector = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], DstSize, Op->Flags, -1);
OrderedNode *ShiftVector = LoadSource_WithOpSize(FPRClass, Op, Op->Src[1], DstSize, Op->Flags, -1);
auto Shift = _VUShr(DstSize, SrcSize, Vector, ShiftVector);
Shift.first->Header.Op = IROp;
OrderedNode *Result = Shift;
if (Is128Bit) {
Result = _VMov(16, Result);
}
StoreResult(FPRClass, Op, Result, -1);
StoreResult(FPRClass, Op, Shift, -1);
}
void OpDispatchBuilder::VPSLLVOp(OpcodeArgs) {

15
unittests/InstructionCountCI/VEX_map2.json
View File

@ -1909,7 +1909,7 @@
]
},
"vpsrlvd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x45 128-bit"
@ -1922,7 +1922,6 @@
"neg v0.4s, v0.4s",
"ushl v4.4s, v4.4s, v0.4s",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
@ -1943,7 +1942,7 @@
]
},
"vpsrlvq xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x45 128-bit"
@ -1958,7 +1957,6 @@
"neg v0.2d, v0.2d",
"ushl v4.2d, v4.2d, v0.2d",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
@ -1979,7 +1977,7 @@
]
},
"vpsravd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x46 128-bit"
@ -1992,7 +1990,6 @@
"neg v0.4s, v0.4s",
"sshl v4.4s, v4.4s, v0.4s",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
@ -2013,7 +2010,7 @@
]
},
"vpsllvd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x47 128-bit"
@ -2025,7 +2022,6 @@
"umin v0.4s, v0.4s, v5.4s",
"ushl v4.4s, v4.4s, v0.4s",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},
@ -2046,7 +2042,7 @@
]
},
"vpsllvq xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x47 128-bit"
@ -2060,7 +2056,6 @@
"bif v0.16b, v5.16b, v1.16b",
"ushl v4.2d, v4.2d, v0.2d",
"mov v4.16b, v4.16b",
"mov v4.16b, v4.16b",
"mov z16.d, p7/m, z4.d"
]
},