From 2d9cb65d5c5f169e2bd20d94f902bf4c56f3b734 Mon Sep 17 00:00:00 2001 From: lioncash Date: Wed, 21 Dec 2022 20:35:31 +0000 Subject: [PATCH] OpcodeDispatcher: Handle VCMPSD --- .../Interface/Core/OpcodeDispatcher.cpp | 1 + .../Core/OpcodeDispatcher/Vector.cpp | 2 + .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vcmpsd.asm | 76 +++++++++++++++++++ 4 files changed, 80 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vcmpsd.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 83ee3c199..7648503d0 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5922,6 +5922,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(1, 0b00, 0xC2), 1, &OpDispatchBuilder::AVXVFCMPOp<4, false>}, {OPD(1, 0b01, 0xC2), 1, &OpDispatchBuilder::AVXVFCMPOp<8, false>}, {OPD(1, 0b10, 0xC2), 1, &OpDispatchBuilder::AVXVFCMPOp<4, true>}, + {OPD(1, 0b11, 0xC2), 1, &OpDispatchBuilder::AVXVFCMPOp<8, true>}, {OPD(1, 0b01, 0xC5), 1, &OpDispatchBuilder::PExtrOp<2>}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index c8807616d..d7daf49e4 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -2034,6 +2034,8 @@ template void OpDispatchBuilder::AVXVFCMPOp<4, true>(OpcodeArgs); template void OpDispatchBuilder::AVXVFCMPOp<8, false>(OpcodeArgs); +template +void OpDispatchBuilder::AVXVFCMPOp<8, true>(OpcodeArgs); void OpDispatchBuilder::FXSaveOp(OpcodeArgs) { OrderedNode *Mem = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1, false); diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index c9608e4d5..664f7d93c 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -100,7 +100,7 @@ void InitializeVEXTables() { {OPD(1, 0b00, 0xC2), 1, X86InstInfo{"VCMPccPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}}, {OPD(1, 0b01, 0xC2), 1, X86InstInfo{"VCMPccPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}}, {OPD(1, 0b10, 0xC2), 1, X86InstInfo{"VCMPccSS", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}}, - {OPD(1, 0b11, 0xC2), 1, X86InstInfo{"VCMPccSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(1, 0b11, 0xC2), 1, X86InstInfo{"VCMPccSD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}}, {OPD(1, 0b01, 0xC4), 1, X86InstInfo{"VPINSRW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(1, 0b01, 0xC5), 1, X86InstInfo{"VPEXTRW", TYPE_INST, GenFlagsSizes(SIZE_32BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_REG_ONLY | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, nullptr}}, diff --git a/unittests/ASM/VEX/vcmpsd.asm b/unittests/ASM/VEX/vcmpsd.asm new file mode 100644 index 000000000..827f86614 --- /dev/null +++ b/unittests/ASM/VEX/vcmpsd.asm @@ -0,0 +1,76 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM2": ["0xFFFFFFFFFFFFFFFF", "0x4000000000000000", "0x0000000000000000", "0x0000000000000000"], + "XMM3": ["0x0000000000000000", "0x4000000000000000", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0xFFFFFFFFFFFFFFFF", "0x4000000000000000", "0x0000000000000000", "0x0000000000000000"], + "XMM5": ["0x0000000000000000", "0x4000000000000000", "0x0000000000000000", "0x0000000000000000"], + "XMM6": ["0xFFFFFFFFFFFFFFFF", "0x4000000000000000", "0x0000000000000000", "0x0000000000000000"], + "XMM7": ["0x0000000000000000", "0x4000000000000000", "0x0000000000000000", "0x0000000000000000"], + "XMM10": ["0xFFFFFFFFFFFFFFFF", "0x7FF8000000000000", "0x0000000000000000", "0x0000000000000000"], + "XMM11": ["0x0000000000000000", "0x7FF8000000000000", "0x0000000000000000", "0x0000000000000000"], + "XMM12": ["0x0000000000000000", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"], + "XMM13": ["0xFFFFFFFFFFFFFFFF", "0x7FF8000000000000", "0x0000000000000000", "0x0000000000000000"] + }, + "MemoryRegions": { + "0x100000000": "4096" + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx + 32 * 0] +vmovapd ymm1, [rdx + 32 * 1] + +vcmpsd xmm2, xmm0, xmm1, 0x00 ; EQ +vcmpsd xmm3, xmm0, xmm1, 0x01 ; LT +vcmpsd xmm4, xmm0, xmm1, 0x02 ; LTE +vcmpsd xmm5, xmm0, xmm1, 0x04 ; NEQ +vcmpsd xmm6, xmm0, xmm1, 0x05 ; NLT +vcmpsd xmm7, xmm0, xmm1, 0x06 ; NLTE + +; Unordered and Ordered tests need to be special cased +vmovapd ymm8, [rdx + 32 * 2] +vmovapd ymm9, [rdx + 32 * 3] + +; Unordered will return true when either input is nan +; [0.0, nan] unord [nan, 0.0] = [1, 1] +vcmpsd xmm10, xmm8, xmm9, 0x03 ; Unordered + +; Ordered will return true when both inputs are NOT nan +; [0.0, nan] ord [nan, 0.0] = [0, 0] +vcmpsd xmm11, xmm8, xmm9, 0x07 ; Ordered + +; Ordered will return true when both inputs are NOT nan +; [nan, 0.0] ord [nan, 0.0] = [0, 1] +vcmpsd xmm12, xmm9, xmm8, 0x07 ; Ordered + +; Ordered will return true when both inputs are NOT nan +; [0.0, nan] ord [0.0, nan] = [1, 0] +vcmpsd xmm13, xmm8, xmm8, 0x07 ; Ordered + +hlt + +align 32 +.data: +dq 0x3FF0000000000000 +dq 0x4000000000000000 +dq 0x3FF0000000000000 +dq 0x4000000000000000 + +dq 0x3FF0000000000000 +dq 0x4008000000000000 +dq 0x3FF0000000000000 +dq 0x4008000000000000 + +dq 0x0000000000000000 +dq 0x7FF8000000000000 +dq 0x0000000000000000 +dq 0x7FF8000000000000 + +dq 0x7FF8000000000000 +dq 0x0000000000000000 +dq 0x7FF8000000000000 +dq 0x0000000000000000