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InstCountCI: Update

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig 2024-08-10 13:06:51 -04:00
parent 91f4c54768
commit 3383786205
41 changed files with 4472 additions and 3980 deletions
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24
unittests/InstructionCountCI/AVX128/VEX_map1.json
View File

@ -2922,13 +2922,13 @@
"fcmp s16, s17",
"mov w27, #0x0",
"cset w20, eq",
"cset w21, lo",
"cset w21, hs",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -2941,13 +2941,13 @@
"fcmp d16, d17",
"mov w27, #0x0",
"cset w20, eq",
"cset w21, lo",
"cset w21, hs",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -2960,13 +2960,13 @@
"fcmp s16, s17",
"mov w27, #0x0",
"cset w20, eq",
"cset w21, lo",
"cset w21, hs",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -2979,13 +2979,13 @@
"fcmp d16, d17",
"mov w27, #0x0",
"cset w20, eq",
"cset w21, lo",
"cset w21, hs",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},

20
unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json
View File

@ -13,7 +13,7 @@
},
"Instructions": {
"vucomiss xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b00 0x2e 128-bit"
],
@ -21,12 +21,11 @@
"fcmp s16, s17",
"mov w27, #0x0",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"vucomisd xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0x2e 128-bit"
],
@ -34,12 +33,11 @@
"fcmp d16, d17",
"mov w27, #0x0",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"vcomiss xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b00 0x2f 128-bit"
],
@ -47,12 +45,11 @@
"fcmp s16, s17",
"mov w27, #0x0",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"vcomisd xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0x2f 128-bit"
],
@ -60,8 +57,7 @@
"fcmp d16, d17",
"mov w27, #0x0",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
}
}

36
unittests/InstructionCountCI/AVX128/VEX_map2.json
View File

@ -528,10 +528,10 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"orr w20, w20, w21, lsl #29",
"bfi w20, w21, #29, #1",
"msr nzcv, x20"
]
},
@ -560,10 +560,10 @@
"addv s2, v2.4s",
"mov w21, v2.s[0]",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"orr w20, w20, w21, lsl #29",
"bfi w20, w21, #29, #1",
"msr nzcv, x20"
]
},
@ -586,10 +586,10 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"orr w20, w20, w21, lsl #29",
"bfi w20, w21, #29, #1",
"msr nzcv, x20"
]
},
@ -618,10 +618,10 @@
"addp v2.2d, v2.2d, v2.2d",
"mov x21, v2.d[0]",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"orr w20, w20, w21, lsl #29",
"bfi w20, w21, #29, #1",
"msr nzcv, x20"
]
},
@ -693,10 +693,10 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"orr w20, w20, w21, lsl #29",
"bfi w20, w21, #29, #1",
"msr nzcv, x20"
]
},
@ -721,10 +721,10 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"orr w20, w20, w21, lsl #29",
"bfi w20, w21, #29, #1",
"msr nzcv, x20"
]
},

40
unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json
View File

@ -32,8 +32,8 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
]
},
@ -62,8 +62,8 @@
"addv s2, v2.4s",
"mov w21, v2.s[0]",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
]
},
@ -86,8 +86,8 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
]
},
@ -116,8 +116,8 @@
"addp v2.2d, v2.2d, v2.2d",
"mov x21, v2.d[0]",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
]
},
@ -136,8 +136,8 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
]
},
@ -162,8 +162,8 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
]
},
@ -622,7 +622,7 @@
],
"ExpectedArm64ASM": [
"bic w26, w5, w7",
"tst w26, w26",
"cmp w26, #0x0 (0)",
"mov x4, x26"
]
},
@ -633,7 +633,7 @@
],
"ExpectedArm64ASM": [
"bic x26, x5, x7",
"tst x26, x26",
"cmp x26, #0x0 (0)",
"mov x4, x26"
]
},
@ -648,8 +648,8 @@
"bic w20, w7, w20",
"tst x5, #0xe0",
"csel w4, w7, w20, ne",
"cset w20, ne",
"tst w4, w4",
"cset w20, eq",
"cmp w4, #0x0 (0)",
"rmif x20, #63, #nzCv"
]
},
@ -664,8 +664,8 @@
"bic x20, x7, x20",
"tst x5, #0xc0",
"csel x4, x7, x20, ne",
"cset w20, ne",
"tst x4, x4",
"cset w20, eq",
"cmp x4, #0x0 (0)",
"rmif x20, #63, #nzCv"
]
},
@ -730,7 +730,7 @@
"bic w22, w20, w22",
"cmp w21, #0x1f (31)",
"csel w4, w22, w20, ls",
"tst w4, w4"
"cmp w4, #0x0 (0)"
]
},
"bextr rax, rbx, rcx": {
@ -750,7 +750,7 @@
"bic x22, x20, x22",
"cmp x21, #0x3f (63)",
"csel x4, x22, x20, ls",
"tst x4, x4"
"cmp x4, #0x0 (0)"
]
}
}

741
unittests/InstructionCountCI/Atomics.json
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File diff suppressed because it is too large Load Diff

5
unittests/InstructionCountCI/FEXOpt/MultiInst.json
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@ -1024,7 +1024,7 @@
]
},
"Sekiro spill block": {
"ExpectedInstructionCount": 147,
"ExpectedInstructionCount": 148,
"Comment": [
"This block of code came from the settings screen when it loaded",
"It was originally at RIP: 0x14232cca0 and has been deobfuscated"
@ -1297,7 +1297,8 @@
"ldr x9, [x8]",
"add x8, x8, #0x8 (8)",
"ldr x7, [x8]",
"add x8, x8, #0x8 (8)"
"add x8, x8, #0x8 (8)",
"cfinv"
]
}
}

547
unittests/InstructionCountCI/FlagM/Atomics.json
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File diff suppressed because it is too large Load Diff

86
unittests/InstructionCountCI/FlagM/FlagOpts.json
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@ -12,7 +12,7 @@
},
"Instructions": {
"Chained add": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"x86Insts": [
"add rax, rbx",
"adc rcx, rcx"
@ -21,27 +21,25 @@
"adds x4, x4, x7",
"mov w27, #0x0",
"adcs x26, x5, x5",
"cfinv",
"mov x5, x26"
]
},
"Chained sub": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 4,
"x86Insts": [
"sub rax, rbx",
"sbb rcx, rdx"
],
"ExpectedArm64ASM": [
"subs x4, x4, x7",
"cfinv",
"eor w27, w5, w6",
"cfinv",
"sbcs x26, x5, x6",
"cfinv",
"mov x5, x26"
]
},
"Inverted add": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"x86Insts": [
"add rax, rbx",
"adc rcx, rdx",
@ -51,12 +49,11 @@
"adds x4, x4, x7",
"eor w27, w5, w6",
"adcs x26, x5, x6",
"mov x5, x26",
"cfinv"
"mov x5, x26"
]
},
"Inverted sub": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"x86Insts": [
"sub rax, rbx",
"sbb rcx, rcx",
@ -64,17 +61,14 @@
],
"ExpectedArm64ASM": [
"subs x4, x4, x7",
"cfinv",
"mov w27, #0x0",
"cfinv",
"sbcs x26, x5, x5",
"cfinv",
"mov x5, x26",
"cfinv"
]
},
"ADC dead": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"x86Insts": [
"add rax, rbx",
"adc rcx, rcx",
@ -83,7 +77,8 @@
"ExpectedArm64ASM": [
"adds x4, x4, x7",
"adc x5, x5, x5",
"ands x26, x5, x5"
"ands x26, x5, x5",
"cfinv"
]
},
"INC consumed": {
@ -94,7 +89,7 @@
],
"ExpectedArm64ASM": [
"adds x4, x4, x7",
"cset w20, hs",
"cset w20, lo",
"adds x26, x4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
@ -102,7 +97,7 @@
]
},
"INC dead": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"x86Insts": [
"add rax, rbx",
"inc rax",
@ -111,18 +106,18 @@
"ExpectedArm64ASM": [
"add x4, x4, x7",
"add x4, x4, #0x1 (1)",
"ands x26, x4, x6"
"ands x26, x4, x6",
"cfinv"
]
},
"DEC consumed": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"x86Insts": [
"sub rax, rbx",
"dec rax"
],
"ExpectedArm64ASM": [
"subs x4, x4, x7",
"cfinv",
"cset w20, hs",
"subs x26, x4, #0x1 (1)",
"rmif x20, #63, #nzCv",
@ -131,7 +126,7 @@
]
},
"DEC dead": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"x86Insts": [
"sub rax, rbx",
"dec rax",
@ -140,11 +135,12 @@
"ExpectedArm64ASM": [
"sub x4, x4, x7",
"sub x4, x4, #0x1 (1)",
"ands x26, x4, x5"
"ands x26, x4, x5",
"cfinv"
]
},
"8-bit DEC consumed": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 11,
"x86Insts": [
"sub al, ah",
"dec al"
@ -154,7 +150,6 @@
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w20, w4, w20",
"cfinv",
"bfxil x4, x20, #0, #8",
"uxtb w27, w4",
"sub w26, w27, #0x1 (1)",
@ -165,7 +160,7 @@
]
},
"8-bit DEC dead": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 9,
"x86Insts": [
"sub al, ah",
"dec al",
@ -179,46 +174,50 @@
"sub w20, w20, #0x1 (1)",
"bfxil x4, x20, #0, #8",
"mov x26, x4",
"cmn wzr, w26, lsl #24"
"cmn wzr, w26, lsl #24",
"cfinv"
]
},
"Variable shift dead": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 3,
"x86Insts": [
"sar rax, cl",
"test rax, rdx"
],
"ExpectedArm64ASM": [
"asr x4, x4, x5",
"ands x26, x4, x6"
"ands x26, x4, x6",
"cfinv"
]
},
"Variable rotate-through-carry dead": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 17,
"x86Insts": [
"rcr rax, cl",
"test rax, rdx"
],
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"cbz x20, #+0x34",
"cbz x20, #+0x38",
"lsr x20, x4, x5",
"cset w21, hs",
"cset w21, lo",
"neg x22, x5",
"lsl x23, x4, x22",
"orr x20, x20, x23, lsl #1",
"sub x23, x5, #0x1 (1)",
"lsr x23, x4, x23",
"eor x23, x23, #0x1",
"rmif x23, #63, #nzCv",
"lsl x21, x21, x22",
"orr x4, x20, x21",
"eor x20, x4, x4, lsr #1",
"rmif x20, #62, #nzcV",
"ands x26, x4, x6"
"ands x26, x4, x6",
"cfinv"
]
},
"Partial NZCV select (cmp)": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"x86Insts": [
"cmp rax, rbx",
"setz cl",
@ -229,11 +228,12 @@
"cset x21, eq",
"bfxil x5, x21, #0, #8",
"mov x26, x5",
"cmn wzr, w26, lsl #24"
"cmn wzr, w26, lsl #24",
"cfinv"
]
},
"Partial NZCV select (add)": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"x86Insts": [
"add rax, rbx",
"setz cl",
@ -244,11 +244,12 @@
"cset x20, eq",
"bfxil x5, x20, #0, #8",
"mov x26, x5",
"cmn wzr, w26, lsl #24"
"cmn wzr, w26, lsl #24",
"cfinv"
]
},
"AND use only ZF": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"x86Insts": [
"and eax, ebx",
"setz cl",
@ -259,11 +260,12 @@
"cset x20, eq",
"bfxil x5, x20, #0, #8",
"mov x26, x5",
"cmn wzr, w26, lsl #24"
"cmn wzr, w26, lsl #24",
"cfinv"
]
},
"AND use only PF": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 10,
"x86Insts": [
"and eax, ebx",
"setp cl",
@ -278,11 +280,12 @@
"and x20, x20, #0x1",
"bfxil x5, x20, #0, #8",
"mov x26, x5",
"cmn wzr, w26, lsl #24"
"cmn wzr, w26, lsl #24",
"cfinv"
]
},
"Dead cmpxchg flags": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 23,
"x86Insts": [
"cmpxchg8b [rbp]",
"test rax, rax"
@ -309,7 +312,8 @@
"mov w21, w22",
"csel x4, x21, x4, ne",
"csel x6, x20, x6, ne",
"ands x26, x4, x4"
"ands x26, x4, x4",
"cfinv"
]
}
}

14
unittests/InstructionCountCI/FlagM/H0F38.json
View File

@ -27,18 +27,18 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
]
},
"adcx eax, ebx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 15,
"Comment": [
"0x66 0x0f 0x38 0xf6"
],
"ExpectedArm64ASM": [
"cset w20, hs",
"cset w20, lo",
"mov w21, w7",
"mov w22, w4",
"add w23, w21, w20",
@ -50,17 +50,18 @@
"cset x21, ls",
"cmp x20, #0x1 (1)",
"csel x20, x21, x23, eq",
"eor x20, x20, #0x1",
"msr nzcv, x22",
"rmif x20, #63, #nzCv"
]
},
"adcx rax, rbx": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 13,
"Comment": [
"0x66 REX.W 0x0f 0x38 0xf6"
],
"ExpectedArm64ASM": [
"cset w20, hs",
"cset w20, lo",
"add x21, x7, x20",
"add x4, x4, x21",
"mrs x21, nzcv",
@ -70,6 +71,7 @@
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
"eor x20, x20, #0x1",
"msr nzcv, x21",
"rmif x20, #63, #nzCv"
]

24
unittests/InstructionCountCI/FlagM/HotBlocks.json
View File

@ -13,7 +13,7 @@
},
"Instructions": {
"The Witcher 3": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 10,
"x86Insts": [
"mov eax, 0x1",
"lock xadd qword [rcx], rax",
@ -32,11 +32,12 @@
"lsl x6, x6, #6",
"eor w27, w6, w5",
"adds x26, x6, x5",
"cfinv",
"mov x6, x26"
]
},
"FMOD scalar loop": {
"ExpectedInstructionCount": 65,
"ExpectedInstructionCount": 64,
"x86Insts": [
"mov esi, ecx",
"mov rdx, rbp",
@ -140,13 +141,12 @@
"mov v18.s[0], v0.s[0]",
"stur s18, [x4, #-4]",
"subs w26, w10, #0x1 (1)",
"cfinv",
"mov x27, x10",
"mov x10, x26"
]
},
"Scalar vector add loop": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": [
"Saw this in bytemark"
],
@ -163,12 +163,11 @@
"str q16, [x16, x4, sxtx]",
"add x4, x4, #0x10 (16)",
"eor w27, w10, w4",
"subs x26, x10, x4",
"cfinv"
"subs x26, x10, x4"
]
},
"bytemark data xor loop": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"Saw this in bytemark"
],
@ -195,12 +194,11 @@
"eor x20, x20, x19",
"str x20, [x7, x6, sxtx #3]",
"eor w27, w11, w4",
"subs x26, x11, x4",
"cfinv"
"subs x26, x11, x4"
]
},
"bytemark num sort": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": [
"Saw this in bytemark"
],
@ -216,12 +214,11 @@
"orr x15, x15, #0x1",
"ldr x20, [x10, x15, sxtx #3]",
"eor w27, w17, w20",
"subs x26, x17, x20",
"cfinv"
"subs x26, x17, x20"
]
},
"pcmpistri xmm0, xmm1, 0_0_00_11_01b": {
"ExpectedInstructionCount": 40,
"ExpectedInstructionCount": 41,
"Comment": [
"A Hat In Time spends at least 5% CPU time in this instruction",
"Comes from vcruntime140.dll wcsstr"
@ -266,6 +263,7 @@
"cmp x21, #0x0 (0)",
"csel x5, x22, x23, eq",
"mov w26, #0x1",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
}

16
unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json
View File

@ -13,7 +13,7 @@
},
"Instructions": {
"Sonic Mania movie player": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 15,
"Comment": "Used to be hottest block in Sonic Mania",
"x86Insts": [
"movzx edx, byte [esi+ecx]",
@ -42,12 +42,11 @@
"str w20, [x4]",
"add w4, w4, #0x4 (4)",
"eor w27, w10, w7",
"subs w26, w10, w7",
"cfinv"
"subs w26, w10, w7"
]
},
"wine mscrt.dll memmove": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 13,
"Comment": "Hot in Sonic Mania",
"x86Insts": [
"movdqu xmm0, [esi]",
@ -76,12 +75,11 @@
"add w11, w11, #0x40 (64)",
"sub w5, w5, #0x40 (64)",
"subs w26, w5, #0x40 (64)",
"cfinv",
"mov x27, x5"
]
},
"dxvk hotblock from MGRR": {
"ExpectedInstructionCount": 38,
"ExpectedInstructionCount": 39,
"Comment": [
"Hottest block in Metal Gear Rising: Revengeance render thread"
],
@ -139,11 +137,12 @@
"rmif x0, #0, #NzCV",
"mov w22, w21",
"csel x4, x20, x4, ne",
"csel x6, x22, x6, ne"
"csel x6, x22, x6, ne",
"cfinv"
]
},
"Psychonauts matrix swizzle": {
"ExpectedInstructionCount": 165,
"ExpectedInstructionCount": 164,
"Comment": [
"Hottest block in Windows Psychonauts",
"Doing a 4x4 32-bit float matrix swizzle",
@ -258,7 +257,6 @@
"str w9, [x8, #-4]!",
"mov x9, x8",
"subs w26, w8, #0x44 (68)",
"cfinv",
"mov x27, x8",
"mov x8, x26",
"mov x20, #0xffffffffffffffbc",

3
unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json
View File

@ -13,7 +13,7 @@
},
"Instructions": {
"FMOD scalar loop": {
"ExpectedInstructionCount": 49,
"ExpectedInstructionCount": 48,
"x86Insts": [
"mov esi, ecx",
"mov rdx, rbp",
@ -101,7 +101,6 @@
"fadd s18, s18, s2",
"stur s18, [x4, #-4]",
"subs w26, w10, #0x1 (1)",
"cfinv",
"mov x27, x10",
"mov x10, x26"
]

789
unittests/InstructionCountCI/FlagM/Primary.json
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File diff suppressed because it is too large Load Diff

875
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
View File

File diff suppressed because it is too large Load Diff

49
unittests/InstructionCountCI/FlagM/Primary_32Bit.json
View File

@ -96,14 +96,14 @@
"ubfx w23, w23, #4, #1",
"orr x22, x23, x22",
"cmp x20, #0x99 (153)",
"cset x23, hi",
"orr x21, x21, x23",
"cset x23, ls",
"and x21, x21, x23",
"add x23, x20, #0x6 (6)",
"cmp x22, #0x0 (0)",
"csel x20, x23, x20, ne",
"add x23, x20, #0x60 (96)",
"cmp x21, #0x0 (0)",
"csel x26, x23, x20, ne",
"csel x26, x23, x20, eq",
"bfxil w4, w26, #0, #8",
"cmn wzr, w26, lsl #24",
"rmif x21, #63, #nzCv",
@ -111,11 +111,11 @@
]
},
"das": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 25,
"Comment": "0x2f",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"cset w21, hs",
"cset w21, lo",
"and x22, x20, #0xf",
"cmp x22, #0x9 (9)",
"cset x22, hi",
@ -136,12 +136,13 @@
"csel x26, x24, x20, ne",
"bfxil w4, w26, #0, #8",
"cmn wzr, w26, lsl #24",
"rmif x23, #63, #nzCv",
"eor x20, x23, #0x1",
"rmif x20, #63, #nzCv",
"eor w27, w26, w22, lsl #4"
]
},
"aaa": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 15,
"Comment": "0x37",
"ExpectedArm64ASM": [
"and x20, x4, #0xf",
@ -150,18 +151,19 @@
"eor w21, w27, w26",
"ubfx w21, w21, #4, #1",
"orr x20, x21, x20",
"lsl x21, x20, #29",
"eor x21, x20, #0x1",
"lsl x21, x21, #29",
"eor w27, w26, w20, lsl #4",
"msr nzcv, x21",
"add w20, w4, #0x106 (262)",
"csel w20, w20, w4, hs",
"csel w20, w20, w4, lo",
"mov w21, #0xff0f",
"and w20, w20, w21",
"bfxil w4, w20, #0, #16"
]
},
"aas": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 15,
"Comment": "0x3f",
"ExpectedArm64ASM": [
"and x20, x4, #0xf",
@ -170,11 +172,12 @@
"eor w21, w27, w26",
"ubfx w21, w21, #4, #1",
"orr x20, x21, x20",
"lsl x21, x20, #29",
"eor x21, x20, #0x1",
"lsl x21, x21, #29",
"eor w27, w26, w20, lsl #4",
"msr nzcv, x21",
"sub w20, w4, #0x106 (262)",
"csel w20, w20, w4, hs",
"csel w20, w20, w4, lo",
"mov w21, #0xff0f",
"and w20, w20, w21",
"bfxil w4, w20, #0, #16"
@ -313,7 +316,7 @@
]
},
"aam": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 9,
"Comment": "0xd4",
"ExpectedArm64ASM": [
"uxtb w20, w4",
@ -323,11 +326,12 @@
"msub x20, x2, x21, x20",
"add x26, x20, x22, lsl #8",
"bfxil w4, w26, #0, #16",
"cmn wzr, w26, lsl #24"
"cmn wzr, w26, lsl #24",
"cfinv"
]
},
"aad": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 8,
"Comment": "0xd5",
"ExpectedArm64ASM": [
"lsr w20, w4, #8",
@ -336,11 +340,12 @@
"add x20, x4, x20",
"and x26, x20, #0xff",
"bfxil w4, w26, #0, #16",
"cmn wzr, w26, lsl #24"
"cmn wzr, w26, lsl #24",
"cfinv"
]
},
"db 0xd4, 0x40": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 9,
"Comment": [
"aam with a different immediate byte base",
"0xd4"
@ -353,11 +358,12 @@
"msub x20, x2, x21, x20",
"add x26, x20, x22, lsl #8",
"bfxil w4, w26, #0, #16",
"cmn wzr, w26, lsl #24"
"cmn wzr, w26, lsl #24",
"cfinv"
]
},
"db 0xd5, 0x40": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 7,
"Comment": [
"aad with a different immediate byte base",
"0xd5"
@ -368,14 +374,15 @@
"add x20, x4, x20",
"and x26, x20, #0xff",
"bfxil w4, w26, #0, #16",
"cmn wzr, w26, lsl #24"
"cmn wzr, w26, lsl #24",
"cfinv"
]
},
"salc": {
"ExpectedInstructionCount": 2,
"Comment": "0xd6",
"ExpectedArm64ASM": [
"csetm w20, hs",
"csetm w20, lo",
"bfxil w4, w20, #0, #8"
]
}

357
unittests/InstructionCountCI/FlagM/Secondary.json
View File

File diff suppressed because it is too large Load Diff

312
unittests/InstructionCountCI/FlagM/SecondaryGroup.json
View File

@ -24,623 +24,689 @@
]
},
"bt ax, 0": {
"ExpectedInstructionCount": 1,
"ExpectedInstructionCount": 2,
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"rmif x4, #63, #nzCv"
"eor x20, x4, #0x1",
"rmif x20, #63, #nzCv"
]
},
"bt eax, 0": {
"ExpectedInstructionCount": 1,
"ExpectedInstructionCount": 2,
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"rmif x4, #63, #nzCv"
"eor x20, x4, #0x1",
"rmif x20, #63, #nzCv"
]
},
"bt rax, 0": {
"ExpectedInstructionCount": 1,
"ExpectedInstructionCount": 2,
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"rmif x4, #63, #nzCv"
"eor x20, x4, #0x1",
"rmif x20, #63, #nzCv"
]
},
"bt ax, 15": {
"ExpectedInstructionCount": 1,
"ExpectedInstructionCount": 2,
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"rmif x4, #14, #nzCv"
"eor x20, x4, #0x8000",
"rmif x20, #14, #nzCv"
]
},
"bt eax, 31": {
"ExpectedInstructionCount": 1,
"ExpectedInstructionCount": 2,
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"rmif x4, #30, #nzCv"
"eor x20, x4, #0x80000000",
"rmif x20, #30, #nzCv"
]
},
"bt rax, 63": {
"ExpectedInstructionCount": 1,
"ExpectedInstructionCount": 2,
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"rmif x4, #62, #nzCv"
"eor x20, x4, #0x8000000000000000",
"rmif x20, #62, #nzCv"
]
},
"bt word [rax], 0": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 3,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"bt dword [rax], 0": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 3,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"bt qword [rax], 0": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 3,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"bt word [rax], 15": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #1]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"bt dword [rax], 31": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #3]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"bt qword [rax], 63": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #7]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"bts ax, 0": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"rmif x4, #63, #nzCv",
"eor x20, x4, #0x1",
"rmif x20, #63, #nzCv",
"orr w20, w4, #0x1",
"bfxil x4, x20, #0, #16"
]
},
"bts eax, 0": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 3,
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"rmif x4, #63, #nzCv",
"eor x20, x4, #0x1",
"rmif x20, #63, #nzCv",
"orr w4, w4, #0x1"
]
},
"bts rax, 0": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 3,
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"rmif x4, #63, #nzCv",
"eor x20, x4, #0x1",
"rmif x20, #63, #nzCv",
"orr x4, x4, #0x1"
]
},
"bts ax, 15": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"rmif x4, #14, #nzCv",
"eor x20, x4, #0x8000",
"rmif x20, #14, #nzCv",
"orr w20, w4, #0x8000",
"bfxil x4, x20, #0, #16"
]
},
"bts eax, 31": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 3,
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"rmif x4, #30, #nzCv",
"eor x20, x4, #0x80000000",
"rmif x20, #30, #nzCv",
"orr w4, w4, #0x80000000"
]
},
"bts rax, 63": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 3,
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"rmif x4, #62, #nzCv",
"eor x20, x4, #0x8000000000000000",
"rmif x20, #62, #nzCv",
"orr x4, x4, #0x8000000000000000"
]
},
"bts word [rax], 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"orr x21, x20, #0x1",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"bts dword [rax], 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"orr x21, x20, #0x1",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"bts qword [rax], 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"orr x21, x20, #0x1",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"bts word [rax], 15": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #1]",
"orr x21, x20, #0x80",
"strb w21, [x4, #1]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"bts dword [rax], 31": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #3]",
"orr x21, x20, #0x80",
"strb w21, [x4, #3]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"bts qword [rax], 63": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #7]",
"orr x21, x20, #0x80",
"strb w21, [x4, #7]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"lock bts word [rax], 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldsetalb w20, w20, [x21]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"lock bts dword [rax], 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldsetalb w20, w20, [x21]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"lock bts qword [rax], 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldsetalb w20, w20, [x21]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"lock bts word [rax], 15": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x1 (1)",
"ldsetalb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"lock bts dword [rax], 31": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x3 (3)",
"ldsetalb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"lock bts qword [rax], 63": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x7 (7)",
"ldsetalb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"btr ax, 0": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"rmif x4, #63, #nzCv",
"eor x20, x4, #0x1",
"rmif x20, #63, #nzCv",
"and w20, w4, #0xfffffffe",
"bfxil x4, x20, #0, #16"
]
},
"btr eax, 0": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 3,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"rmif x4, #63, #nzCv",
"eor x20, x4, #0x1",
"rmif x20, #63, #nzCv",
"and w4, w4, #0xfffffffe"
]
},
"btr rax, 0": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 3,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"rmif x4, #63, #nzCv",
"eor x20, x4, #0x1",
"rmif x20, #63, #nzCv",
"and x4, x4, #0xfffffffffffffffe"
]
},
"btr ax, 15": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"rmif x4, #14, #nzCv",
"eor x20, x4, #0x8000",
"rmif x20, #14, #nzCv",
"and w20, w4, #0xffff7fff",
"bfxil x4, x20, #0, #16"
]
},
"btr eax, 31": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 3,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"rmif x4, #30, #nzCv",
"eor x20, x4, #0x80000000",
"rmif x20, #30, #nzCv",
"and w4, w4, #0x7fffffff"
]
},
"btr rax, 63": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 3,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"rmif x4, #62, #nzCv",
"eor x20, x4, #0x8000000000000000",
"rmif x20, #62, #nzCv",
"and x4, x4, #0x7fffffffffffffff"
]
},
"btr word [rax], 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"and x21, x20, #0xfffffffffffffffe",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"btr dword [rax], 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"and x21, x20, #0xfffffffffffffffe",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"btr qword [rax], 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"and x21, x20, #0xfffffffffffffffe",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"btr word [rax], 15": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #1]",
"and x21, x20, #0xffffffffffffff7f",
"strb w21, [x4, #1]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"btr dword [rax], 31": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #3]",
"and x21, x20, #0xffffffffffffff7f",
"strb w21, [x4, #3]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"btr qword [rax], 63": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #7]",
"and x21, x20, #0xffffffffffffff7f",
"strb w21, [x4, #7]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"lock btr word [rax], 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldclralb w20, w20, [x21]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"lock btr dword [rax], 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldclralb w20, w20, [x21]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"lock btr qword [rax], 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldclralb w20, w20, [x21]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"lock btr word [rax], 15": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x1 (1)",
"ldclralb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"lock btr dword [rax], 31": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x3 (3)",
"ldclralb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"lock btr qword [rax], 63": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x7 (7)",
"ldclralb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"btc ax, 0": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"rmif x4, #63, #nzCv",
"eor x20, x4, #0x1",
"rmif x20, #63, #nzCv",
"eor w20, w4, #0x1",
"bfxil x4, x20, #0, #16"
]
},
"btc eax, 0": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 3,
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"rmif x4, #63, #nzCv",
"eor x20, x4, #0x1",
"rmif x20, #63, #nzCv",
"eor w4, w4, #0x1"
]
},
"btc rax, 0": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 3,
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"rmif x4, #63, #nzCv",
"eor x20, x4, #0x1",
"rmif x20, #63, #nzCv",
"eor x4, x4, #0x1"
]
},
"btc ax, 15": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"rmif x4, #14, #nzCv",
"eor x20, x4, #0x8000",
"rmif x20, #14, #nzCv",
"eor w20, w4, #0x8000",
"bfxil x4, x20, #0, #16"
]
},
"btc eax, 31": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 3,
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"rmif x4, #30, #nzCv",
"eor x20, x4, #0x80000000",
"rmif x20, #30, #nzCv",
"eor w4, w4, #0x80000000"
]
},
"btc rax, 63": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 3,
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"rmif x4, #62, #nzCv",
"eor x20, x4, #0x8000000000000000",
"rmif x20, #62, #nzCv",
"eor x4, x4, #0x8000000000000000"
]
},
"btc word [rax], 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"eor x21, x20, #0x1",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"btc dword [rax], 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"eor x21, x20, #0x1",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"btc qword [rax], 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"eor x21, x20, #0x1",
"strb w21, [x4]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"btc word [rax], 15": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #1]",
"eor x21, x20, #0x80",
"strb w21, [x4, #1]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"btc dword [rax], 31": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #3]",
"eor x21, x20, #0x80",
"strb w21, [x4, #3]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"btc qword [rax], 63": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ldrb w20, [x4, #7]",
"eor x21, x20, #0x80",
"strb w21, [x4, #7]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"lock btc word [rax], 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldeoralb w20, w20, [x21]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"lock btc dword [rax], 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldeoralb w20, w20, [x21]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"lock btc qword [rax], 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"add x21, x4, #0x0 (0)",
"ldeoralb w20, w20, [x21]",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"lock btc word [rax], 15": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x1 (1)",
"ldeoralb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"lock btc dword [rax], 31": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x3 (3)",
"ldeoralb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
"lock btc qword [rax], 63": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov w20, #0x80",
"add x21, x4, #0x7 (7)",
"ldeoralb w20, w20, [x21]",
"lsr w20, w20, #7",
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv"
]
},
@ -695,87 +761,73 @@
]
},
"rdrand ax": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x20, rndr",
"cset x21, ne",
"mov x22, x21",
"bfxil x4, x20, #0, #16",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x22, #29",
"msr nzcv, x20"
"mov w27, #0x0",
"cset w20, eq",
"rmif x20, #63, #NZCV"
]
},
"rdrand eax": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x20, rndr",
"cset x21, ne",
"mov x22, x21",
"mov w4, w20",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x22, #29",
"msr nzcv, x20"
"mov w27, #0x0",
"cset w20, eq",
"rmif x20, #63, #NZCV"
]
},
"rdrand rax": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x20, rndr",
"cset x21, ne",
"mov x22, x21",
"mov x4, x20",
"mov w27, #0x0",
"mrs x4, rndr",
"mov w26, #0x1",
"lsl x20, x22, #29",
"msr nzcv, x20"
"mov w27, #0x0",
"cset w20, eq",
"rmif x20, #63, #NZCV"
]
},
"rdseed ax": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
"cset x21, ne",
"mov x22, x21",
"bfxil x4, x20, #0, #16",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x22, #29",
"msr nzcv, x20"
"mov w27, #0x0",
"cset w20, eq",
"rmif x20, #63, #NZCV"
]
},
"rdseed eax": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
"cset x21, ne",
"mov x22, x21",
"mov w4, w20",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x22, #29",
"msr nzcv, x20"
"mov w27, #0x0",
"cset w20, eq",
"rmif x20, #63, #NZCV"
]
},
"rdseed rax": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
"cset x21, ne",
"mov x22, x21",
"mov x4, x20",
"mov w27, #0x0",
"mrs x4, rndrrs",
"mov w26, #0x1",
"lsl x20, x22, #29",
"msr nzcv, x20"
"mov w27, #0x0",
"cset w20, eq",
"rmif x20, #63, #NZCV"
]
},
"psrlw mm0, 0": {

10
unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
View File

@ -14,25 +14,23 @@
},
"Instructions": {
"ucomisd xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": "0x66 0x0f 0x2e",
"ExpectedArm64ASM": [
"fcmp d16, d17",
"mov w27, #0x0",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"comisd xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": "0x66 0x0f 0x2f",
"ExpectedArm64ASM": [
"fcmp d16, d17",
"mov w27, #0x0",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"pmovmskb eax, xmm0": {

52
unittests/InstructionCountCI/FlagM/Secondary_REP.json
View File

@ -23,9 +23,9 @@
"addp v0.8b, v0.8b, v0.8b",
"umov w20, v0.b[0]",
"bfxil x4, x20, #0, #16",
"tst w20, w20",
"mov w26, #0x1",
"mov w27, #0x0"
"mov w27, #0x0",
"cmp w20, #0x0 (0)",
"mov w26, #0x1"
]
},
"popcnt eax, ebx": {
@ -36,9 +36,9 @@
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
"tst w4, w4",
"mov w26, #0x1",
"mov w27, #0x0"
"mov w27, #0x0",
"cmp w4, #0x0 (0)",
"mov w26, #0x1"
]
},
"popcnt rax, rbx": {
@ -49,13 +49,13 @@
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
"tst w4, w4",
"mov w26, #0x1",
"mov w27, #0x0"
"mov w27, #0x0",
"cmp w4, #0x0 (0)",
"mov w26, #0x1"
]
},
"tzcnt ax, bx": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 7,
"Comment": "0xf3 0x0f 0xbc",
"ExpectedArm64ASM": [
"rbit w20, w7",
@ -63,31 +63,34 @@
"clz w20, w20",
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"eor x20, x20, #0x10",
"rmif x20, #3, #nzCv"
]
},
"tzcnt eax, ebx": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "0xf3 0x0f 0xbc",
"ExpectedArm64ASM": [
"rbit w4, w7",
"clz w4, w4",
"tst w4, w4",
"rmif x4, #4, #nzCv"
"cmp w4, #0x0 (0)",
"eor x20, x4, #0x20",
"rmif x20, #4, #nzCv"
]
},
"tzcnt rax, rbx": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "0xf3 0x0f 0xbc",
"ExpectedArm64ASM": [
"rbit x4, x7",
"clz x4, x4",
"tst x4, x4",
"rmif x4, #5, #nzCv"
"cmp x4, #0x0 (0)",
"eor x20, x4, #0x40",
"rmif x20, #5, #nzCv"
]
},
"lzcnt ax, bx": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 7,
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"lsl w20, w7, #16",
@ -95,25 +98,28 @@
"clz w20, w20",
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"eor x20, x20, #0x10",
"rmif x20, #3, #nzCv"
]
},
"lzcnt eax, ebx": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"clz w4, w7",
"tst w4, w4",
"rmif x4, #4, #nzCv"
"cmp w4, #0x0 (0)",
"eor x20, x4, #0x20",
"rmif x20, #4, #nzCv"
]
},
"lzcnt rax, rbx": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"clz x4, x7",
"tst x4, x4",
"rmif x4, #5, #nzCv"
"cmp x4, #0x0 (0)",
"eor x20, x4, #0x40",
"rmif x20, #5, #nzCv"
]
}
}

20
unittests/InstructionCountCI/FlagM/VEX_map1.json
View File

@ -15,7 +15,7 @@
},
"Instructions": {
"vucomiss xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b00 0x2e 128-bit"
],
@ -23,12 +23,11 @@
"fcmp s16, s17",
"mov w27, #0x0",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"vucomisd xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0x2e 128-bit"
],
@ -36,12 +35,11 @@
"fcmp d16, d17",
"mov w27, #0x0",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"vcomiss xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b00 0x2f 128-bit"
],
@ -49,12 +47,11 @@
"fcmp s16, s17",
"mov w27, #0x0",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"vcomisd xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0x2f 128-bit"
],
@ -62,8 +59,7 @@
"fcmp d16, d17",
"mov w27, #0x0",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"vpmovmskb rax, xmm0": {

40
unittests/InstructionCountCI/FlagM/VEX_map2.json
View File

@ -31,8 +31,8 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
]
},
@ -55,8 +55,8 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
]
},
@ -79,8 +79,8 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
]
},
@ -103,8 +103,8 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
]
},
@ -123,8 +123,8 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
]
},
@ -143,8 +143,8 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"rmif x21, #63, #nzCv"
]
},
@ -351,7 +351,7 @@
],
"ExpectedArm64ASM": [
"bic w26, w5, w7",
"tst w26, w26",
"cmp w26, #0x0 (0)",
"mov x4, x26"
]
},
@ -362,7 +362,7 @@
],
"ExpectedArm64ASM": [
"bic x26, x5, x7",
"tst x26, x26",
"cmp x26, #0x0 (0)",
"mov x4, x26"
]
},
@ -377,8 +377,8 @@
"bic w20, w7, w20",
"tst x5, #0xe0",
"csel w4, w7, w20, ne",
"cset w20, ne",
"tst w4, w4",
"cset w20, eq",
"cmp w4, #0x0 (0)",
"rmif x20, #63, #nzCv"
]
},
@ -393,8 +393,8 @@
"bic x20, x7, x20",
"tst x5, #0xc0",
"csel x4, x7, x20, ne",
"cset w20, ne",
"tst x4, x4",
"cset w20, eq",
"cmp x4, #0x0 (0)",
"rmif x20, #63, #nzCv"
]
},
@ -459,7 +459,7 @@
"bic w22, w20, w22",
"cmp w21, #0x1f (31)",
"csel w4, w22, w20, ls",
"tst w4, w4"
"cmp w4, #0x0 (0)"
]
},
"bextr rax, rbx, rcx": {
@ -479,7 +479,7 @@
"bic x22, x20, x22",
"cmp x21, #0x3f (63)",
"csel x4, x22, x20, ls",
"tst x4, x4"
"cmp x4, #0x0 (0)"
]
}
}

24
unittests/InstructionCountCI/FlagM/VEX_map_group.json
View File

@ -20,8 +20,8 @@
"sub w20, w7, #0x1 (1)",
"and w4, w20, w7",
"cmp x7, #0x0 (0)",
"cset x20, eq",
"tst w4, w4",
"cset x20, ne",
"cmp w4, #0x0 (0)",
"rmif x20, #63, #nzCv"
]
},
@ -34,8 +34,8 @@
"sub x20, x7, #0x1 (1)",
"and x4, x20, x7",
"cmp x7, #0x0 (0)",
"cset x20, eq",
"tst x4, x4",
"cset x20, ne",
"cmp x4, #0x0 (0)",
"rmif x20, #63, #nzCv"
]
},
@ -48,8 +48,8 @@
"sub w20, w7, #0x1 (1)",
"eor w4, w20, w7",
"cmp x7, #0x0 (0)",
"cset x20, eq",
"tst w4, w4",
"cset x20, ne",
"cmp w4, #0x0 (0)",
"rmif x20, #63, #nzCv"
]
},
@ -62,8 +62,8 @@
"sub x20, x7, #0x1 (1)",
"eor x4, x20, x7",
"cmp x7, #0x0 (0)",
"cset x20, eq",
"tst x4, x4",
"cset x20, ne",
"cmp x4, #0x0 (0)",
"rmif x20, #63, #nzCv"
]
},
@ -75,8 +75,8 @@
"ExpectedArm64ASM": [
"neg w20, w7",
"and w4, w7, w20",
"tst w4, w4",
"cset w20, ne",
"cmp w4, #0x0 (0)",
"cset w20, eq",
"rmif x20, #63, #nzCv"
]
},
@ -88,8 +88,8 @@
"ExpectedArm64ASM": [
"neg x20, x7",
"and x4, x7, x20",
"tst x4, x4",
"cset w20, ne",
"cmp x4, #0x0 (0)",
"cset w20, eq",
"rmif x20, #63, #nzCv"
]
}

46
unittests/InstructionCountCI/FlagM/x87-HalfLife.json
View File

@ -13,7 +13,7 @@
},
"Instructions": {
"Block1": {
"ExpectedInstructionCount": 1368,
"ExpectedInstructionCount": 1369,
"x86Insts": [
"sub esp,0x2c",
"mov ecx,dword [esp + 0x34]",
@ -1425,6 +1425,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"mov w22, #0x1",
@ -1458,7 +1459,7 @@
]
},
"Block2": {
"ExpectedInstructionCount": 551,
"ExpectedInstructionCount": 552,
"x86Insts": [
"sub esp,0x1c",
"mov edx,dword [esp + 0x20]",
@ -1601,11 +1602,11 @@
"ubfx x22, x22, #2, #1",
"orr w23, w23, w22",
"orr w22, w24, w22",
"eor x23, x23, #0x1",
"rmif x23, #63, #nzCv",
"rmif x22, #62, #nZcv",
"mov w22, #0x1",
"csetm x23, hs",
"csel x23, x20, x23, eq",
"csetm x23, ls",
"dup v4.2d, x23",
"bit v2.16b, v3.16b, v4.16b",
"ldr s3, [x6, #4]",
@ -1704,10 +1705,10 @@
"ubfx x23, x23, #2, #1",
"orr w24, w24, w23",
"orr w23, w25, w23",
"eor x24, x24, #0x1",
"rmif x24, #63, #nzCv",
"rmif x23, #62, #nZcv",
"csetm x23, hs",
"csel x23, x20, x23, eq",
"csetm x23, ls",
"dup v5.2d, x23",
"bit v3.16b, v4.16b, v5.16b",
"mov w23, #0x8",
@ -1801,16 +1802,16 @@
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x16, [sp], #16",
"ldp x17, x30, [sp], #16",
"mov x21, x0",
"ubfx x24, x21, #1, #1",
"ubfx x25, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w24, w24, w21",
"orr w21, w25, w21",
"rmif x24, #63, #nzCv",
"rmif x21, #62, #nZcv",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x24, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w20, w24, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x20, #62, #nZcv",
"csetm x20, ls",
"dup v6.2d, x20",
"bit v4.16b, v5.16b, v6.16b",
"mrs x0, nzcv",
@ -2025,6 +2026,7 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w24, w24, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x24, #62, #nZcv",
"eor w26, w20, #0x1",
@ -2899,7 +2901,7 @@
]
},
"Block4": {
"ExpectedInstructionCount": 206,
"ExpectedInstructionCount": 205,
"x86Insts": [
"push ebp",
"push edi",
@ -2962,7 +2964,6 @@
"str w10, [x8, #-4]!",
"str w7, [x8, #-4]!",
"subs w26, w8, #0x4c (76)",
"cfinv",
"mov x27, x8",
"mov x8, x26",
"ldr w4, [x8, #104]",
@ -4158,12 +4159,12 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x22, #62, #nZcv",
"mov w21, #0x1",
"eor w26, w20, #0x1",
"cset x20, lo",
"csel x20, x20, xzr, ne",
"cset x20, hi",
"strb w20, [x8, #48]",
"ldrb w4, [x8, #48]",
"add w20, w10, #0x4 (4)",
@ -4193,7 +4194,7 @@
]
},
"Block6": {
"ExpectedInstructionCount": 924,
"ExpectedInstructionCount": 925,
"x86Insts": [
"push ebp",
"push edi",
@ -5126,6 +5127,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"mov w22, #0x1",
@ -6756,7 +6758,7 @@
"ldr w4, [x20, #20]",
"str w4, [x8, #156]",
"mov w26, #0x0",
"tst w26, w26",
"cmp w26, #0x0 (0)",
"mov x4, x26",
"mov w20, #0x869c",
"movk w20, #0x5, lsl #16",

15
unittests/InstructionCountCI/FlagM/x87-Oblivion.json
View File

@ -13,7 +13,7 @@
},
"Instructions": {
"Block1": {
"ExpectedInstructionCount": 25782,
"ExpectedInstructionCount": 25781,
"x86Insts": [
"sub esp,0x118",
"fld dword [ecx + 0x1084]",
@ -26707,13 +26707,12 @@
"ldr w20, [x5, #4096]",
"eor w27, w20, w5",
"subs w26, w20, w5",
"cfinv",
"add w4, w5, #0x800 (2048)",
"strb wzr, [x28, #1298]"
]
},
"Block2": {
"ExpectedInstructionCount": 16635,
"ExpectedInstructionCount": 16636,
"x86Insts": [
"mov eax,dword [ebp + 0x8]",
"fld dword [eax + 0x40]",
@ -43981,6 +43980,7 @@
"mov x8, x9",
"ldr w9, [x8]",
"add x8, x8, #0x4 (4)",
"cfinv",
"strb wzr, [x28, #1298]"
]
},
@ -58298,7 +58298,7 @@
]
},
"Block5": {
"ExpectedInstructionCount": 284,
"ExpectedInstructionCount": 283,
"x86Insts": [
"mov ebx,dword [eax + 0x68]",
"fld dword [esi + 0x2c]",
@ -58675,7 +58675,6 @@
"ldr w4, [x9, #104]",
"mvn w27, w8",
"subs w26, w8, #0x14 (20)",
"cfinv",
"mov x8, x26",
"add w20, w8, #0x10 (16)",
"str s2, [x20]",
@ -59337,7 +59336,7 @@
]
},
"Block7": {
"ExpectedInstructionCount": 7397,
"ExpectedInstructionCount": 7396,
"x86Insts": [
"fld dword [ecx + 0xc]",
"fld dword [ecx + 0x18]",
@ -64925,7 +64924,6 @@
"add w4, w4, #0x18 (24)",
"add w5, w5, #0x4 (4)",
"subs w26, w6, #0x1 (1)",
"cfinv",
"mov x27, x6",
"mov x6, x26",
"add w12, w8, #0x44 (68)",
@ -66955,7 +66953,7 @@
]
},
"Block8": {
"ExpectedInstructionCount": 6590,
"ExpectedInstructionCount": 6589,
"x86Insts": [
"movzx eax,word [esi + edx*0x8]",
"fld dword [esi + edx*0x8 + 0x4]",
@ -71719,7 +71717,6 @@
"ldr w21, [x8, #28]",
"eor w27, w6, w21",
"subs w26, w6, w21",
"cfinv",
"ldr s2, [x8, #196]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",

27
unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
View File

@ -13,7 +13,7 @@
},
"Instructions": {
"Block1": {
"ExpectedInstructionCount": 16357,
"ExpectedInstructionCount": 16358,
"x86Insts": [
"sub esp,0x88",
"fld dword [ecx + 0x4]",
@ -16891,13 +16891,14 @@
"fmov s2, s0",
"str s2, [x20]",
"adds w26, w8, #0x88 (136)",
"cfinv",
"mov x27, x8",
"mov x8, x26",
"strb wzr, [x28, #1298]"
]
},
"Block2": {
"ExpectedInstructionCount": 14021,
"ExpectedInstructionCount": 14022,
"x86Insts": [
"sub esp,0x90",
"fld dword [ecx + 0x4]",
@ -31347,6 +31348,7 @@
"str s2, [x20]",
"mvn w27, w8",
"adds w26, w8, #0x90 (144)",
"cfinv",
"mov x8, x26",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
@ -31359,7 +31361,7 @@
]
},
"Block3": {
"ExpectedInstructionCount": 118,
"ExpectedInstructionCount": 119,
"x86Insts": [
"mov eax,dword [ebp + 0xffffff44]",
"mov ecx,dword [eax + 0x4]",
@ -32179,6 +32181,7 @@
"movk w21, #0x819, lsl #16",
"add w21, w20, w21",
"str w20, [x8, #-4]!",
"cfinv",
"ldr x0, [x28, #2272]",
"and x3, x21, #0xfffff",
"add x0, x0, x3, lsl #4",
@ -32186,7 +32189,7 @@
]
},
"Block4": {
"ExpectedInstructionCount": 12313,
"ExpectedInstructionCount": 12312,
"x86Insts": [
"mov ebp,dword [esp + 0x64]",
"fadd dword [ebp + 0x8]",
@ -43530,7 +43533,6 @@
"orr w21, w21, w23",
"strb w21, [x28, #1298]",
"subs w9, w9, #0x10 (16)",
"cfinv",
"ldr s2, [x8, #24]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
@ -44857,7 +44859,7 @@
]
},
"Block5": {
"ExpectedInstructionCount": 12248,
"ExpectedInstructionCount": 12247,
"x86Insts": [
"mov ebp,dword [esp + 0x64]",
"fadd dword [ebp + 0x8]",
@ -56331,7 +56333,6 @@
"orr w21, w21, w23",
"strb w21, [x28, #1298]",
"subs w7, w7, #0x10 (16)",
"cfinv",
"cset w21, hs",
"subs w26, w9, #0x1 (1)",
"rmif x21, #63, #nzCv",
@ -65449,7 +65450,7 @@
]
},
"Block7": {
"ExpectedInstructionCount": 7583,
"ExpectedInstructionCount": 7582,
"x86Insts": [
"push ebp",
"mov ebp,esp",
@ -65875,7 +65876,6 @@
"mov x9, x8",
"str w7, [x8, #-4]!",
"subs w26, w8, #0x84 (132)",
"cfinv",
"mov x27, x8",
"mov x8, x26",
"ldr w7, [x9, #8]",
@ -73457,7 +73457,7 @@
]
},
"Block8": {
"ExpectedInstructionCount": 8522,
"ExpectedInstructionCount": 8523,
"x86Insts": [
"fadd dword [esp + 0x40]",
"lea edx,[ecx + ecx*0x2]",
@ -82213,11 +82213,12 @@
"add x8, x8, #0x4 (4)",
"mvn w27, w8",
"adds w26, w8, #0x74 (116)",
"cfinv",
"mov x8, x26"
]
},
"Block9": {
"ExpectedInstructionCount": 8441,
"ExpectedInstructionCount": 8442,
"x86Insts": [
"fadd dword [esp + 0x40]",
"lea edx,[ecx + ecx*0x2]",
@ -90883,11 +90884,12 @@
"add x8, x8, #0x4 (4)",
"mvn w27, w8",
"adds w26, w8, #0x74 (116)",
"cfinv",
"mov x8, x26"
]
},
"Block10": {
"ExpectedInstructionCount": 6382,
"ExpectedInstructionCount": 6383,
"x86Insts": [
"push ebp",
"mov ebp,esp",
@ -97681,6 +97683,7 @@
"movk w21, #0x816, lsl #16",
"add w21, w20, w21",
"str w20, [x8, #-4]!",
"cfinv",
"ldrb w20, [x28, #1019]",
"add w20, w20, #0x5 (5)",
"and w20, w20, #0x7",

216
unittests/InstructionCountCI/FlagM/x87.json
View File

@ -5965,7 +5965,7 @@
"0xda 11b 0xc0 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
@ -5983,7 +5983,7 @@
"0xda 11b 0xc1 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x1 (1)",
@ -6003,7 +6003,7 @@
"0xda 11b 0xc2 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x2 (2)",
@ -6023,7 +6023,7 @@
"0xda 11b 0xc3 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x3 (3)",
@ -6043,7 +6043,7 @@
"0xda 11b 0xc4 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x4 (4)",
@ -6063,7 +6063,7 @@
"0xda 11b 0xc5 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x5 (5)",
@ -6083,7 +6083,7 @@
"0xda 11b 0xc6 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x6 (6)",
@ -6103,7 +6103,7 @@
"0xda 11b 0xc7 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x7 (7)",
@ -6276,14 +6276,12 @@
]
},
"fcmovbe st0, st0": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 10,
"Comment": [
"0xda 11b 0xd0 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
@ -6296,14 +6294,12 @@
]
},
"fcmovbe st0, st1": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd1 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x1 (1)",
@ -6318,14 +6314,12 @@
]
},
"fcmovbe st0, st2": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd2 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x2 (2)",
@ -6340,14 +6334,12 @@
]
},
"fcmovbe st0, st3": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd3 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x3 (3)",
@ -6362,14 +6354,12 @@
]
},
"fcmovbe st0, st4": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd4 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x4 (4)",
@ -6384,14 +6374,12 @@
]
},
"fcmovbe st0, st5": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd5 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x5 (5)",
@ -6406,14 +6394,12 @@
]
},
"fcmovbe st0, st6": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd6 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x6 (6)",
@ -6428,14 +6414,12 @@
]
},
"fcmovbe st0, st7": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd7 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x7 (7)",
@ -6943,7 +6927,7 @@
"0xdb 11b 0xc0 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
@ -6961,7 +6945,7 @@
"0xdb 11b 0xc1 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x1 (1)",
@ -6981,7 +6965,7 @@
"0xdb 11b 0xc2 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x2 (2)",
@ -7001,7 +6985,7 @@
"0xdb 11b 0xc3 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x3 (3)",
@ -7021,7 +7005,7 @@
"0xdb 11b 0xc4 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x4 (4)",
@ -7041,7 +7025,7 @@
"0xdb 11b 0xc5 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x5 (5)",
@ -7061,7 +7045,7 @@
"0xdb 11b 0xc6 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x6 (6)",
@ -7081,7 +7065,7 @@
"0xdb 11b 0xc7 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x7 (7)",
@ -7254,13 +7238,12 @@
]
},
"fcmovnbe st0, st0": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"0xdb 11b 0xd0 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
@ -7273,13 +7256,12 @@
]
},
"fcmovnbe st0, st1": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd1 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x1 (1)",
@ -7294,13 +7276,12 @@
]
},
"fcmovnbe st0, st2": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd2 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x2 (2)",
@ -7315,13 +7296,12 @@
]
},
"fcmovnbe st0, st3": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd3 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x3 (3)",
@ -7336,13 +7316,12 @@
]
},
"fcmovnbe st0, st4": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd4 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x4 (4)",
@ -7357,13 +7336,12 @@
]
},
"fcmovnbe st0, st5": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd5 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x5 (5)",
@ -7378,13 +7356,12 @@
]
},
"fcmovnbe st0, st6": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd6 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x6 (6)",
@ -7399,13 +7376,12 @@
]
},
"fcmovnbe st0, st7": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd7 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x7 (7)",
@ -7649,7 +7625,7 @@
]
},
"fucomi st0, st0": {
"ExpectedInstructionCount": 41,
"ExpectedInstructionCount": 42,
"Comment": [
"0xdb 11b 0xe8 /5"
],
@ -7692,13 +7668,14 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x22, #62, #nZcv",
"eor w26, w20, #0x1"
]
},
"fucomi st0, st1": {
"ExpectedInstructionCount": 43,
"ExpectedInstructionCount": 44,
"Comment": [
"0xdb 11b 0xe9 /5"
],
@ -7743,13 +7720,14 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x22, #62, #nZcv",
"eor w26, w20, #0x1"
]
},
"fucomi st0, st2": {
"ExpectedInstructionCount": 43,
"ExpectedInstructionCount": 44,
"Comment": [
"0xdb 11b 0xea /5"
],
@ -7794,13 +7772,14 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x22, #62, #nZcv",
"eor w26, w20, #0x1"
]
},
"fucomi st0, st3": {
"ExpectedInstructionCount": 43,
"ExpectedInstructionCount": 44,
"Comment": [
"0xdb 11b 0xeb /5"
],
@ -7845,13 +7824,14 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x22, #62, #nZcv",
"eor w26, w20, #0x1"
]
},
"fucomi st0, st4": {
"ExpectedInstructionCount": 43,
"ExpectedInstructionCount": 44,
"Comment": [
"0xdb 11b 0xec /5"
],
@ -7896,13 +7876,14 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x22, #62, #nZcv",
"eor w26, w20, #0x1"
]
},
"fucomi st0, st5": {
"ExpectedInstructionCount": 43,
"ExpectedInstructionCount": 44,
"Comment": [
"0xdb 11b 0xed /5"
],
@ -7947,13 +7928,14 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x22, #62, #nZcv",
"eor w26, w20, #0x1"
]
},
"fucomi st0, st6": {
"ExpectedInstructionCount": 43,
"ExpectedInstructionCount": 44,
"Comment": [
"0xdb 11b 0xee /5"
],
@ -7998,13 +7980,14 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x22, #62, #nZcv",
"eor w26, w20, #0x1"
]
},
"fucomi st0, st7": {
"ExpectedInstructionCount": 43,
"ExpectedInstructionCount": 44,
"Comment": [
"0xdb 11b 0xef /5"
],
@ -8049,13 +8032,14 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x22, #62, #nZcv",
"eor w26, w20, #0x1"
]
},
"fcomi st0, st0": {
"ExpectedInstructionCount": 41,
"ExpectedInstructionCount": 42,
"Comment": [
"0xdb 11b 0xf0 /6"
],
@ -8098,13 +8082,14 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x22, #62, #nZcv",
"eor w26, w20, #0x1"
]
},
"fcomi st0, st1": {
"ExpectedInstructionCount": 43,
"ExpectedInstructionCount": 44,
"Comment": [
"0xdb 11b 0xf1 /6"
],
@ -8149,13 +8134,14 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x22, #62, #nZcv",
"eor w26, w20, #0x1"
]
},
"fcomi st0, st2": {
"ExpectedInstructionCount": 43,
"ExpectedInstructionCount": 44,
"Comment": [
"0xdb 11b 0xf2 /6"
],
@ -8200,13 +8186,14 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x22, #62, #nZcv",
"eor w26, w20, #0x1"
]
},
"fcomi st0, st3": {
"ExpectedInstructionCount": 43,
"ExpectedInstructionCount": 44,
"Comment": [
"0xdb 11b 0xf3 /6"
],
@ -8251,13 +8238,14 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x22, #62, #nZcv",
"eor w26, w20, #0x1"
]
},
"fcomi st0, st4": {
"ExpectedInstructionCount": 43,
"ExpectedInstructionCount": 44,
"Comment": [
"0xdb 11b 0xf4 /6"
],
@ -8302,13 +8290,14 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x22, #62, #nZcv",
"eor w26, w20, #0x1"
]
},
"fcomi st0, st5": {
"ExpectedInstructionCount": 43,
"ExpectedInstructionCount": 44,
"Comment": [
"0xdb 11b 0xf5 /6"
],
@ -8353,13 +8342,14 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x22, #62, #nZcv",
"eor w26, w20, #0x1"
]
},
"fcomi st0, st6": {
"ExpectedInstructionCount": 43,
"ExpectedInstructionCount": 44,
"Comment": [
"0xdb 11b 0xf6 /6"
],
@ -8404,13 +8394,14 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x22, #62, #nZcv",
"eor w26, w20, #0x1"
]
},
"fcomi st0, st7": {
"ExpectedInstructionCount": 43,
"ExpectedInstructionCount": 44,
"Comment": [
"0xdb 11b 0xf7 /6"
],
@ -8455,6 +8446,7 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"rmif x21, #63, #nzCv",
"rmif x22, #62, #nZcv",
"eor w26, w20, #0x1"
@ -16944,7 +16936,7 @@
]
},
"fucomip st0": {
"ExpectedInstructionCount": 49,
"ExpectedInstructionCount": 50,
"Comment": [
"0xdf 11b 0xe8 /5"
],
@ -16987,6 +16979,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"mov w22, #0x1",
@ -17001,7 +16994,7 @@
]
},
"fucomip st1": {
"ExpectedInstructionCount": 51,
"ExpectedInstructionCount": 52,
"Comment": [
"0xdf 11b 0xe9 /5"
],
@ -17047,6 +17040,7 @@
"ubfx x22, x22, #2, #1",
"orr w23, w23, w22",
"orr w24, w24, w22",
"eor x23, x23, #0x1",
"rmif x23, #63, #nzCv",
"rmif x24, #62, #nZcv",
"eor w26, w22, #0x1",
@ -17060,7 +17054,7 @@
]
},
"fucomip st2": {
"ExpectedInstructionCount": 51,
"ExpectedInstructionCount": 52,
"Comment": [
"0xdf 11b 0xea /5"
],
@ -17105,6 +17099,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"mov w22, #0x1",
@ -17119,7 +17114,7 @@
]
},
"fucomip st3": {
"ExpectedInstructionCount": 51,
"ExpectedInstructionCount": 52,
"Comment": [
"0xdf 11b 0xeb /5"
],
@ -17164,6 +17159,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"mov w22, #0x1",
@ -17178,7 +17174,7 @@
]
},
"fucomip st4": {
"ExpectedInstructionCount": 51,
"ExpectedInstructionCount": 52,
"Comment": [
"0xdf 11b 0xec /5"
],
@ -17223,6 +17219,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"mov w22, #0x1",
@ -17237,7 +17234,7 @@
]
},
"fucomip st5": {
"ExpectedInstructionCount": 51,
"ExpectedInstructionCount": 52,
"Comment": [
"0xdf 11b 0xed /5"
],
@ -17282,6 +17279,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"mov w22, #0x1",
@ -17296,7 +17294,7 @@
]
},
"fucomip st6": {
"ExpectedInstructionCount": 51,
"ExpectedInstructionCount": 52,
"Comment": [
"0xdf 11b 0xee /5"
],
@ -17341,6 +17339,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"mov w22, #0x1",
@ -17355,7 +17354,7 @@
]
},
"fucomip st7": {
"ExpectedInstructionCount": 51,
"ExpectedInstructionCount": 52,
"Comment": [
"0xdf 11b 0xef /5"
],
@ -17400,6 +17399,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"mov w22, #0x1",
@ -17414,7 +17414,7 @@
]
},
"fcomip st0": {
"ExpectedInstructionCount": 49,
"ExpectedInstructionCount": 50,
"Comment": [
"0xdf 11b 0xf0 /6"
],
@ -17457,6 +17457,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"mov w22, #0x1",
@ -17471,7 +17472,7 @@
]
},
"fcomip st1": {
"ExpectedInstructionCount": 51,
"ExpectedInstructionCount": 52,
"Comment": [
"0xdf 11b 0xf1 /6"
],
@ -17517,6 +17518,7 @@
"ubfx x22, x22, #2, #1",
"orr w23, w23, w22",
"orr w24, w24, w22",
"eor x23, x23, #0x1",
"rmif x23, #63, #nzCv",
"rmif x24, #62, #nZcv",
"eor w26, w22, #0x1",
@ -17530,7 +17532,7 @@
]
},
"fcomip st2": {
"ExpectedInstructionCount": 51,
"ExpectedInstructionCount": 52,
"Comment": [
"0xdf 11b 0xf2 /6"
],
@ -17575,6 +17577,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"mov w22, #0x1",
@ -17589,7 +17592,7 @@
]
},
"fcomip st3": {
"ExpectedInstructionCount": 51,
"ExpectedInstructionCount": 52,
"Comment": [
"0xdf 11b 0xf3 /6"
],
@ -17634,6 +17637,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"mov w22, #0x1",
@ -17648,7 +17652,7 @@
]
},
"fcomip st4": {
"ExpectedInstructionCount": 51,
"ExpectedInstructionCount": 52,
"Comment": [
"0xdf 11b 0xf4 /6"
],
@ -17693,6 +17697,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"mov w22, #0x1",
@ -17707,7 +17712,7 @@
]
},
"fcomip st5": {
"ExpectedInstructionCount": 51,
"ExpectedInstructionCount": 52,
"Comment": [
"0xdf 11b 0xf5 /6"
],
@ -17752,6 +17757,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"mov w22, #0x1",
@ -17766,7 +17772,7 @@
]
},
"fcomip st6": {
"ExpectedInstructionCount": 51,
"ExpectedInstructionCount": 52,
"Comment": [
"0xdf 11b 0xf6 /6"
],
@ -17811,6 +17817,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"mov w22, #0x1",
@ -17825,7 +17832,7 @@
]
},
"fcomip st7": {
"ExpectedInstructionCount": 51,
"ExpectedInstructionCount": 52,
"Comment": [
"0xdf 11b 0xf7 /6"
],
@ -17870,6 +17877,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"mov w22, #0x1",

248
unittests/InstructionCountCI/FlagM/x87_f64.json
View File

@ -3316,7 +3316,7 @@
"0xda 11b 0xc0 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
@ -3334,7 +3334,7 @@
"0xda 11b 0xc1 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x1 (1)",
@ -3354,7 +3354,7 @@
"0xda 11b 0xc2 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x2 (2)",
@ -3374,7 +3374,7 @@
"0xda 11b 0xc3 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x3 (3)",
@ -3394,7 +3394,7 @@
"0xda 11b 0xc4 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x4 (4)",
@ -3414,7 +3414,7 @@
"0xda 11b 0xc5 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x5 (5)",
@ -3434,7 +3434,7 @@
"0xda 11b 0xc6 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x6 (6)",
@ -3454,7 +3454,7 @@
"0xda 11b 0xc7 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x7 (7)",
@ -3627,14 +3627,12 @@
]
},
"fcmovbe st0, st0": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 10,
"Comment": [
"0xda 11b 0xd0 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
@ -3647,14 +3645,12 @@
]
},
"fcmovbe st0, st1": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd1 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x1 (1)",
@ -3669,14 +3665,12 @@
]
},
"fcmovbe st0, st2": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd2 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x2 (2)",
@ -3691,14 +3685,12 @@
]
},
"fcmovbe st0, st3": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd3 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x3 (3)",
@ -3713,14 +3705,12 @@
]
},
"fcmovbe st0, st4": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd4 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x4 (4)",
@ -3735,14 +3725,12 @@
]
},
"fcmovbe st0, st5": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd5 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x5 (5)",
@ -3757,14 +3745,12 @@
]
},
"fcmovbe st0, st6": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd6 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x6 (6)",
@ -3779,14 +3765,12 @@
]
},
"fcmovbe st0, st7": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd7 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x7 (7)",
@ -4224,7 +4208,7 @@
"0xdb 11b 0xc0 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
@ -4242,7 +4226,7 @@
"0xdb 11b 0xc1 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x1 (1)",
@ -4262,7 +4246,7 @@
"0xdb 11b 0xc2 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x2 (2)",
@ -4282,7 +4266,7 @@
"0xdb 11b 0xc3 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x3 (3)",
@ -4302,7 +4286,7 @@
"0xdb 11b 0xc4 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x4 (4)",
@ -4322,7 +4306,7 @@
"0xdb 11b 0xc5 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x5 (5)",
@ -4342,7 +4326,7 @@
"0xdb 11b 0xc6 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x6 (6)",
@ -4362,7 +4346,7 @@
"0xdb 11b 0xc7 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x7 (7)",
@ -4535,13 +4519,12 @@
]
},
"fcmovnbe st0, st0": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"0xdb 11b 0xd0 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
@ -4554,13 +4537,12 @@
]
},
"fcmovnbe st0, st1": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd1 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x1 (1)",
@ -4575,13 +4557,12 @@
]
},
"fcmovnbe st0, st2": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd2 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x2 (2)",
@ -4596,13 +4577,12 @@
]
},
"fcmovnbe st0, st3": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd3 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x3 (3)",
@ -4617,13 +4597,12 @@
]
},
"fcmovnbe st0, st4": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd4 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x4 (4)",
@ -4638,13 +4617,12 @@
]
},
"fcmovnbe st0, st5": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd5 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x5 (5)",
@ -4659,13 +4637,12 @@
]
},
"fcmovnbe st0, st6": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd6 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x6 (6)",
@ -4680,13 +4657,12 @@
]
},
"fcmovnbe st0, st7": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd7 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x7 (7)",
@ -4938,7 +4914,7 @@
]
},
"fucomi st0, st0": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Comment": [
"0xdb 11b 0xe8 /5"
],
@ -4950,12 +4926,11 @@
"ldr d3, [x0, #1040]",
"fcmp d3, d2",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"fucomi st0, st1": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"0xdb 11b 0xe9 /5"
],
@ -4969,12 +4944,11 @@
"ldr d3, [x0, #1040]",
"fcmp d3, d2",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"fucomi st0, st2": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"0xdb 11b 0xea /5"
],
@ -4988,12 +4962,11 @@
"ldr d3, [x0, #1040]",
"fcmp d3, d2",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"fucomi st0, st3": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"0xdb 11b 0xeb /5"
],
@ -5007,12 +4980,11 @@
"ldr d3, [x0, #1040]",
"fcmp d3, d2",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"fucomi st0, st4": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"0xdb 11b 0xec /5"
],
@ -5026,12 +4998,11 @@
"ldr d3, [x0, #1040]",
"fcmp d3, d2",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"fucomi st0, st5": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"0xdb 11b 0xed /5"
],
@ -5045,12 +5016,11 @@
"ldr d3, [x0, #1040]",
"fcmp d3, d2",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"fucomi st0, st6": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"0xdb 11b 0xee /5"
],
@ -5064,12 +5034,11 @@
"ldr d3, [x0, #1040]",
"fcmp d3, d2",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"fucomi st0, st7": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"0xdb 11b 0xef /5"
],
@ -5083,12 +5052,11 @@
"ldr d3, [x0, #1040]",
"fcmp d3, d2",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"fcomi st0, st0": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Comment": [
"0xdb 11b 0xf0 /6"
],
@ -5100,12 +5068,11 @@
"ldr d3, [x0, #1040]",
"fcmp d3, d2",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"fcomi st0, st1": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"0xdb 11b 0xf1 /6"
],
@ -5119,12 +5086,11 @@
"ldr d3, [x0, #1040]",
"fcmp d3, d2",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"fcomi st0, st2": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"0xdb 11b 0xf2 /6"
],
@ -5138,12 +5104,11 @@
"ldr d3, [x0, #1040]",
"fcmp d3, d2",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"fcomi st0, st3": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"0xdb 11b 0xf3 /6"
],
@ -5157,12 +5122,11 @@
"ldr d3, [x0, #1040]",
"fcmp d3, d2",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"fcomi st0, st4": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"0xdb 11b 0xf4 /6"
],
@ -5176,12 +5140,11 @@
"ldr d3, [x0, #1040]",
"fcmp d3, d2",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"fcomi st0, st5": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"0xdb 11b 0xf5 /6"
],
@ -5195,12 +5158,11 @@
"ldr d3, [x0, #1040]",
"fcmp d3, d2",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"fcomi st0, st6": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"0xdb 11b 0xf6 /6"
],
@ -5214,12 +5176,11 @@
"ldr d3, [x0, #1040]",
"fcmp d3, d2",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"fcomi st0, st7": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"0xdb 11b 0xf7 /6"
],
@ -5233,8 +5194,7 @@
"ldr d3, [x0, #1040]",
"fcmp d3, d2",
"cset w26, vc",
"axflag",
"cfinv"
"axflag"
]
},
"fadd qword [rax]": {
@ -9710,7 +9670,7 @@
]
},
"fucomip st0": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 16,
"Comment": [
"0xdf 11b 0xe8 /5"
],
@ -9724,7 +9684,6 @@
"mov w21, #0x1",
"cset w26, vc",
"axflag",
"cfinv",
"ldrb w22, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
@ -9735,7 +9694,7 @@
]
},
"fucomip st1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": [
"0xdf 11b 0xe9 /5"
],
@ -9751,7 +9710,6 @@
"fcmp d3, d2",
"cset w26, vc",
"axflag",
"cfinv",
"ldrb w22, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
@ -9762,7 +9720,7 @@
]
},
"fucomip st2": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": [
"0xdf 11b 0xea /5"
],
@ -9778,7 +9736,6 @@
"mov w21, #0x1",
"cset w26, vc",
"axflag",
"cfinv",
"ldrb w22, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
@ -9789,7 +9746,7 @@
]
},
"fucomip st3": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": [
"0xdf 11b 0xeb /5"
],
@ -9805,7 +9762,6 @@
"mov w21, #0x1",
"cset w26, vc",
"axflag",
"cfinv",
"ldrb w22, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
@ -9816,7 +9772,7 @@
]
},
"fucomip st4": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": [
"0xdf 11b 0xec /5"
],
@ -9832,7 +9788,6 @@
"mov w21, #0x1",
"cset w26, vc",
"axflag",
"cfinv",
"ldrb w22, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
@ -9843,7 +9798,7 @@
]
},
"fucomip st5": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": [
"0xdf 11b 0xed /5"
],
@ -9859,7 +9814,6 @@
"mov w21, #0x1",
"cset w26, vc",
"axflag",
"cfinv",
"ldrb w22, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
@ -9870,7 +9824,7 @@
]
},
"fucomip st6": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": [
"0xdf 11b 0xee /5"
],
@ -9886,7 +9840,6 @@
"mov w21, #0x1",
"cset w26, vc",
"axflag",
"cfinv",
"ldrb w22, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
@ -9897,7 +9850,7 @@
]
},
"fucomip st7": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": [
"0xdf 11b 0xef /5"
],
@ -9913,7 +9866,6 @@
"mov w21, #0x1",
"cset w26, vc",
"axflag",
"cfinv",
"ldrb w22, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
@ -9924,7 +9876,7 @@
]
},
"fcomip st0": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 16,
"Comment": [
"0xdf 11b 0xf0 /6"
],
@ -9938,7 +9890,6 @@
"mov w21, #0x1",
"cset w26, vc",
"axflag",
"cfinv",
"ldrb w22, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
@ -9949,7 +9900,7 @@
]
},
"fcomip st1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": [
"0xdf 11b 0xf1 /6"
],
@ -9965,7 +9916,6 @@
"fcmp d3, d2",
"cset w26, vc",
"axflag",
"cfinv",
"ldrb w22, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
@ -9976,7 +9926,7 @@
]
},
"fcomip st2": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": [
"0xdf 11b 0xf2 /6"
],
@ -9992,7 +9942,6 @@
"mov w21, #0x1",
"cset w26, vc",
"axflag",
"cfinv",
"ldrb w22, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
@ -10003,7 +9952,7 @@
]
},
"fcomip st3": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": [
"0xdf 11b 0xf3 /6"
],
@ -10019,7 +9968,6 @@
"mov w21, #0x1",
"cset w26, vc",
"axflag",
"cfinv",
"ldrb w22, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
@ -10030,7 +9978,7 @@
]
},
"fcomip st4": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": [
"0xdf 11b 0xf4 /6"
],
@ -10046,7 +9994,6 @@
"mov w21, #0x1",
"cset w26, vc",
"axflag",
"cfinv",
"ldrb w22, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
@ -10057,7 +10004,7 @@
]
},
"fcomip st5": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": [
"0xdf 11b 0xf5 /6"
],
@ -10073,7 +10020,6 @@
"mov w21, #0x1",
"cset w26, vc",
"axflag",
"cfinv",
"ldrb w22, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
@ -10084,7 +10030,7 @@
]
},
"fcomip st6": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": [
"0xdf 11b 0xf6 /6"
],
@ -10100,7 +10046,6 @@
"mov w21, #0x1",
"cset w26, vc",
"axflag",
"cfinv",
"ldrb w22, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
@ -10111,7 +10056,7 @@
]
},
"fcomip st7": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": [
"0xdf 11b 0xf7 /6"
],
@ -10127,7 +10072,6 @@
"mov w21, #0x1",
"cset w26, vc",
"axflag",
"cfinv",
"ldrb w22, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w22, w21",

16
unittests/InstructionCountCI/H0F38.json
View File

@ -404,10 +404,10 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"orr w20, w20, w21, lsl #29",
"bfi w20, w21, #29, #1",
"msr nzcv, x20"
]
},
@ -858,12 +858,12 @@
]
},
"adcx eax, ebx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 15,
"Comment": [
"0x66 0x0f 0x38 0xf6"
],
"ExpectedArm64ASM": [
"cset w20, hs",
"cset w20, lo",
"mov w21, w7",
"mov w22, w4",
"add w23, w21, w20",
@ -875,17 +875,18 @@
"cset x21, ls",
"cmp x20, #0x1 (1)",
"csel x20, x21, x23, eq",
"eor x20, x20, #0x1",
"bfi w22, w20, #29, #1",
"msr nzcv, x22"
]
},
"adcx rax, rbx": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 13,
"Comment": [
"0x66 REX.W 0x0f 0x38 0xf6"
],
"ExpectedArm64ASM": [
"cset w20, hs",
"cset w20, lo",
"add x21, x7, x20",
"add x4, x4, x21",
"mrs x21, nzcv",
@ -895,6 +896,7 @@
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
"eor x20, x20, #0x1",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]

1213
unittests/InstructionCountCI/Primary.json
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1109
unittests/InstructionCountCI/PrimaryGroup.json
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File diff suppressed because it is too large Load Diff

59
unittests/InstructionCountCI/Primary_32Bit.json
View File

@ -95,14 +95,14 @@
"ubfx w23, w23, #4, #1",
"orr x22, x23, x22",
"cmp x20, #0x99 (153)",
"cset x23, hi",
"orr x21, x21, x23",
"cset x23, ls",
"and x21, x21, x23",
"add x23, x20, #0x6 (6)",
"cmp x22, #0x0 (0)",
"csel x20, x23, x20, ne",
"add x23, x20, #0x60 (96)",
"cmp x21, #0x0 (0)",
"csel x26, x23, x20, ne",
"csel x26, x23, x20, eq",
"bfxil w4, w26, #0, #8",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
@ -112,11 +112,11 @@
]
},
"das": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 27,
"Comment": "0x2f",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"cset w21, hs",
"cset w21, lo",
"and x22, x20, #0xf",
"cmp x22, #0x9 (9)",
"cset x22, hi",
@ -137,14 +137,15 @@
"csel x26, x24, x20, ne",
"bfxil w4, w26, #0, #8",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"orr w20, w20, w23, lsl #29",
"eor x20, x23, #0x1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"eor w27, w26, w22, lsl #4",
"msr nzcv, x20"
]
},
"aaa": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 15,
"Comment": "0x37",
"ExpectedArm64ASM": [
"and x20, x4, #0xf",
@ -153,18 +154,19 @@
"eor w21, w27, w26",
"ubfx w21, w21, #4, #1",
"orr x20, x21, x20",
"lsl x21, x20, #29",
"eor x21, x20, #0x1",
"lsl x21, x21, #29",
"eor w27, w26, w20, lsl #4",
"msr nzcv, x21",
"add w20, w4, #0x106 (262)",
"csel w20, w20, w4, hs",
"csel w20, w20, w4, lo",
"mov w21, #0xff0f",
"and w20, w20, w21",
"bfxil w4, w20, #0, #16"
]
},
"aas": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 15,
"Comment": "0x3f",
"ExpectedArm64ASM": [
"and x20, x4, #0xf",
@ -173,11 +175,12 @@
"eor w21, w27, w26",
"ubfx w21, w21, #4, #1",
"orr x20, x21, x20",
"lsl x21, x20, #29",
"eor x21, x20, #0x1",
"lsl x21, x21, #29",
"eor w27, w26, w20, lsl #4",
"msr nzcv, x21",
"sub w20, w4, #0x106 (262)",
"csel w20, w20, w4, hs",
"csel w20, w20, w4, lo",
"mov w21, #0xff0f",
"and w20, w20, w21",
"bfxil w4, w20, #0, #16"
@ -328,7 +331,7 @@
]
},
"aam": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 11,
"Comment": "0xd4",
"ExpectedArm64ASM": [
"uxtb w20, w4",
@ -338,11 +341,14 @@
"msub x20, x2, x21, x20",
"add x26, x20, x22, lsl #8",
"bfxil w4, w26, #0, #16",
"cmn wzr, w26, lsl #24"
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"aad": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 10,
"Comment": "0xd5",
"ExpectedArm64ASM": [
"lsr w20, w4, #8",
@ -351,11 +357,14 @@
"add x20, x4, x20",
"and x26, x20, #0xff",
"bfxil w4, w26, #0, #16",
"cmn wzr, w26, lsl #24"
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"db 0xd4, 0x40": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 11,
"Comment": [
"aam with a different immediate byte base",
"0xd4"
@ -368,11 +377,14 @@
"msub x20, x2, x21, x20",
"add x26, x20, x22, lsl #8",
"bfxil w4, w26, #0, #16",
"cmn wzr, w26, lsl #24"
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"db 0xd5, 0x40": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 9,
"Comment": [
"aad with a different immediate byte base",
"0xd5"
@ -383,14 +395,17 @@
"add x20, x4, x20",
"and x26, x20, #0xff",
"bfxil w4, w26, #0, #16",
"cmn wzr, w26, lsl #24"
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"salc": {
"ExpectedInstructionCount": 2,
"Comment": "0xd6",
"ExpectedArm64ASM": [
"csetm w20, hs",
"csetm w20, lo",
"bfxil w4, w20, #0, #8"
]
}

12
unittests/InstructionCountCI/SSE42_Strings.json
View File

@ -36,7 +36,7 @@
},
"Instructions": {
"pcmpestrm xmm0, xmm1, 0_0_00_00_00b": {
"ExpectedInstructionCount": 35,
"ExpectedInstructionCount": 36,
"Comment": [
"0x66 0x0f 0x3A 0x60"
],
@ -75,11 +75,12 @@
"uxth w0, w20",
"fmov s16, w0",
"mov w26, #0x1",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"pcmpestri xmm0, xmm1, 0_0_00_00_00b": {
"ExpectedInstructionCount": 42,
"ExpectedInstructionCount": 43,
"Comment": [
"0x66 0x0f 0x3A 0x61"
],
@ -125,11 +126,12 @@
"cmp x21, #0x0 (0)",
"csel x5, x22, x23, eq",
"mov w26, #0x1",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"pcmpistrm xmm0, xmm1, 0_0_00_00_00b": {
"ExpectedInstructionCount": 33,
"ExpectedInstructionCount": 34,
"Comment": [
"0x66 0x0f 0x3A 0x62"
],
@ -166,11 +168,12 @@
"uxth w0, w20",
"fmov s16, w0",
"mov w26, #0x1",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"pcmpistri xmm0, xmm1, 0_0_00_00_00b": {
"ExpectedInstructionCount": 40,
"ExpectedInstructionCount": 41,
"Comment": [
"0x66 0x0f 0x3A 0x63"
],
@ -214,6 +217,7 @@
"cmp x21, #0x0 (0)",
"csel x5, x22, x23, eq",
"mov w26, #0x1",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
}

425
unittests/InstructionCountCI/Secondary.json
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306
unittests/InstructionCountCI/SecondaryGroup.json
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File diff suppressed because it is too large Load Diff

12
unittests/InstructionCountCI/Secondary_OpSize.json
View File

@ -148,13 +148,13 @@
"fcmp d16, d17",
"mov w27, #0x0",
"cset w20, eq",
"cset w21, lo",
"cset w21, hs",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -165,13 +165,13 @@
"fcmp d16, d17",
"mov w27, #0x0",
"cset w20, eq",
"cset w21, lo",
"cset w21, hs",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},

68
unittests/InstructionCountCI/Secondary_REP.json
View File

@ -409,9 +409,9 @@
"addp v0.8b, v0.8b, v0.8b",
"umov w20, v0.b[0]",
"bfxil x4, x20, #0, #16",
"tst w20, w20",
"mov w26, #0x1",
"mov w27, #0x0"
"mov w27, #0x0",
"cmp w20, #0x0 (0)",
"mov w26, #0x1"
]
},
"popcnt eax, ebx": {
@ -422,9 +422,9 @@
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
"tst w4, w4",
"mov w26, #0x1",
"mov w27, #0x0"
"mov w27, #0x0",
"cmp w4, #0x0 (0)",
"mov w26, #0x1"
]
},
"popcnt rax, rbx": {
@ -435,13 +435,13 @@
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
"tst w4, w4",
"mov w26, #0x1",
"mov w27, #0x0"
"mov w27, #0x0",
"cmp w4, #0x0 (0)",
"mov w26, #0x1"
]
},
"tzcnt ax, bx": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 10,
"Comment": "0xf3 0x0f 0xbc",
"ExpectedArm64ASM": [
"rbit w20, w7",
@ -449,6 +449,7 @@
"clz w20, w20",
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"eor x20, x20, #0x10",
"ubfx x20, x20, #4, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
@ -456,33 +457,35 @@
]
},
"tzcnt eax, ebx": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 8,
"Comment": "0xf3 0x0f 0xbc",
"ExpectedArm64ASM": [
"rbit w4, w7",
"clz w4, w4",
"tst w4, w4",
"ubfx x20, x4, #5, #1",
"cmp w4, #0x0 (0)",
"eor x20, x4, #0x20",
"ubfx x20, x20, #5, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"tzcnt rax, rbx": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 8,
"Comment": "0xf3 0x0f 0xbc",
"ExpectedArm64ASM": [
"rbit x4, x7",
"clz x4, x4",
"tst x4, x4",
"ubfx x20, x4, #6, #1",
"cmp x4, #0x0 (0)",
"eor x20, x4, #0x40",
"ubfx x20, x20, #6, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lzcnt ax, bx": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 10,
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"lsl w20, w7, #16",
@ -490,6 +493,7 @@
"clz w20, w20",
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"eor x20, x20, #0x10",
"ubfx x20, x20, #4, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
@ -497,27 +501,29 @@
]
},
"lzcnt eax, ebx": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 7,
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"clz w4, w7",
"tst w4, w4",
"ubfx x20, x4, #5, #1",
"cmp w4, #0x0 (0)",
"eor x20, x4, #0x20",
"ubfx x20, x20, #5, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lzcnt rax, rbx": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 7,
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"clz x4, x7",
"tst x4, x4",
"ubfx x20, x4, #6, #1",
"cmp x4, #0x0 (0)",
"eor x20, x4, #0x40",
"ubfx x20, x20, #6, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"cmpss xmm0, xmm1, 0": {

24
unittests/InstructionCountCI/VEX_map1.json
View File

@ -3361,13 +3361,13 @@
"fcmp s16, s17",
"mov w27, #0x0",
"cset w20, eq",
"cset w21, lo",
"cset w21, hs",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -3380,13 +3380,13 @@
"fcmp d16, d17",
"mov w27, #0x0",
"cset w20, eq",
"cset w21, lo",
"cset w21, hs",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -3399,13 +3399,13 @@
"fcmp s16, s17",
"mov w27, #0x0",
"cset w20, eq",
"cset w21, lo",
"cset w21, hs",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -3418,13 +3418,13 @@
"fcmp d16, d17",
"mov w27, #0x0",
"cset w20, eq",
"cset w21, lo",
"cset w21, hs",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},

60
unittests/InstructionCountCI/VEX_map2.json
View File

@ -519,10 +519,10 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"orr w20, w20, w21, lsl #29",
"bfi w20, w21, #29, #1",
"msr nzcv, x20"
]
},
@ -545,10 +545,10 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"orr w20, w20, w21, lsl #29",
"bfi w20, w21, #29, #1",
"msr nzcv, x20"
]
},
@ -571,10 +571,10 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"orr w20, w20, w21, lsl #29",
"bfi w20, w21, #29, #1",
"msr nzcv, x20"
]
},
@ -597,10 +597,10 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"orr w20, w20, w21, lsl #29",
"bfi w20, w21, #29, #1",
"msr nzcv, x20"
]
},
@ -677,10 +677,10 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"orr w20, w20, w21, lsl #29",
"bfi w20, w21, #29, #1",
"msr nzcv, x20"
]
},
@ -699,10 +699,10 @@
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"tst w20, w20",
"cset x21, ne",
"cmp w20, #0x0 (0)",
"mrs x20, nzcv",
"orr w20, w20, w21, lsl #29",
"bfi w20, w21, #29, #1",
"msr nzcv, x20"
]
},
@ -4901,7 +4901,7 @@
],
"ExpectedArm64ASM": [
"bic w26, w5, w7",
"tst w26, w26",
"cmp w26, #0x0 (0)",
"mov x4, x26"
]
},
@ -4912,7 +4912,7 @@
],
"ExpectedArm64ASM": [
"bic x26, x5, x7",
"tst x26, x26",
"cmp x26, #0x0 (0)",
"mov x4, x26"
]
},
@ -4927,11 +4927,11 @@
"bic w20, w7, w20",
"tst x5, #0xe0",
"csel w4, w7, w20, ne",
"cset w20, ne",
"tst w4, w4",
"cset w20, eq",
"cmp w4, #0x0 (0)",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"bzhi rax, rbx, rcx": {
@ -4945,11 +4945,11 @@
"bic x20, x7, x20",
"tst x5, #0xc0",
"csel x4, x7, x20, ne",
"cset w20, ne",
"tst x4, x4",
"cset w20, eq",
"cmp x4, #0x0 (0)",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"pext eax, ebx, ecx": {
@ -5125,7 +5125,7 @@
"bic w22, w20, w22",
"cmp w21, #0x1f (31)",
"csel w4, w22, w20, ls",
"tst w4, w4"
"cmp w4, #0x0 (0)"
]
},
"bextr rax, rbx, rcx": {
@ -5145,7 +5145,7 @@
"bic x22, x20, x22",
"cmp x21, #0x3f (63)",
"csel x4, x22, x20, ls",
"tst x4, x4"
"cmp x4, #0x0 (0)"
]
},
"shlx eax, ebx, ecx": {

48
unittests/InstructionCountCI/VEX_map_group.json
View File

@ -616,11 +616,11 @@
"sub w20, w7, #0x1 (1)",
"and w4, w20, w7",
"cmp x7, #0x0 (0)",
"cset x20, eq",
"tst w4, w4",
"cset x20, ne",
"cmp w4, #0x0 (0)",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"blsr rax, rbx": {
@ -632,11 +632,11 @@
"sub x20, x7, #0x1 (1)",
"and x4, x20, x7",
"cmp x7, #0x0 (0)",
"cset x20, eq",
"tst x4, x4",
"cset x20, ne",
"cmp x4, #0x0 (0)",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"blsmsk eax, ebx": {
@ -648,11 +648,11 @@
"sub w20, w7, #0x1 (1)",
"eor w4, w20, w7",
"cmp x7, #0x0 (0)",
"cset x20, eq",
"tst w4, w4",
"cset x20, ne",
"cmp w4, #0x0 (0)",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"blsmsk rax, rbx": {
@ -664,11 +664,11 @@
"sub x20, x7, #0x1 (1)",
"eor x4, x20, x7",
"cmp x7, #0x0 (0)",
"cset x20, eq",
"tst x4, x4",
"cset x20, ne",
"cmp x4, #0x0 (0)",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"blsi eax, ebx": {
@ -679,11 +679,11 @@
"ExpectedArm64ASM": [
"neg w20, w7",
"and w4, w7, w20",
"tst w4, w4",
"cset w20, ne",
"cmp w4, #0x0 (0)",
"cset w20, eq",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"blsi rax, rbx": {
@ -694,11 +694,11 @@
"ExpectedArm64ASM": [
"neg x20, x7",
"and x4, x7, x20",
"tst x4, x4",
"cset w20, ne",
"cmp x4, #0x0 (0)",
"cset w20, eq",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
}
}

216
unittests/InstructionCountCI/x87.json
View File

@ -5964,7 +5964,7 @@
"0xda 11b 0xc0 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
@ -5982,7 +5982,7 @@
"0xda 11b 0xc1 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x1 (1)",
@ -6002,7 +6002,7 @@
"0xda 11b 0xc2 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x2 (2)",
@ -6022,7 +6022,7 @@
"0xda 11b 0xc3 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x3 (3)",
@ -6042,7 +6042,7 @@
"0xda 11b 0xc4 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x4 (4)",
@ -6062,7 +6062,7 @@
"0xda 11b 0xc5 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x5 (5)",
@ -6082,7 +6082,7 @@
"0xda 11b 0xc6 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x6 (6)",
@ -6102,7 +6102,7 @@
"0xda 11b 0xc7 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x7 (7)",
@ -6275,14 +6275,12 @@
]
},
"fcmovbe st0, st0": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 10,
"Comment": [
"0xda 11b 0xd0 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
@ -6295,14 +6293,12 @@
]
},
"fcmovbe st0, st1": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd1 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x1 (1)",
@ -6317,14 +6313,12 @@
]
},
"fcmovbe st0, st2": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd2 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x2 (2)",
@ -6339,14 +6333,12 @@
]
},
"fcmovbe st0, st3": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd3 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x3 (3)",
@ -6361,14 +6353,12 @@
]
},
"fcmovbe st0, st4": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd4 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x4 (4)",
@ -6383,14 +6373,12 @@
]
},
"fcmovbe st0, st5": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd5 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x5 (5)",
@ -6405,14 +6393,12 @@
]
},
"fcmovbe st0, st6": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd6 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x6 (6)",
@ -6427,14 +6413,12 @@
]
},
"fcmovbe st0, st7": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd7 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x7 (7)",
@ -6942,7 +6926,7 @@
"0xdb 11b 0xc0 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
@ -6960,7 +6944,7 @@
"0xdb 11b 0xc1 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x1 (1)",
@ -6980,7 +6964,7 @@
"0xdb 11b 0xc2 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x2 (2)",
@ -7000,7 +6984,7 @@
"0xdb 11b 0xc3 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x3 (3)",
@ -7020,7 +7004,7 @@
"0xdb 11b 0xc4 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x4 (4)",
@ -7040,7 +7024,7 @@
"0xdb 11b 0xc5 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x5 (5)",
@ -7060,7 +7044,7 @@
"0xdb 11b 0xc6 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x6 (6)",
@ -7080,7 +7064,7 @@
"0xdb 11b 0xc7 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x7 (7)",
@ -7253,13 +7237,12 @@
]
},
"fcmovnbe st0, st0": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"0xdb 11b 0xd0 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
@ -7272,13 +7255,12 @@
]
},
"fcmovnbe st0, st1": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd1 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x1 (1)",
@ -7293,13 +7275,12 @@
]
},
"fcmovnbe st0, st2": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd2 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x2 (2)",
@ -7314,13 +7295,12 @@
]
},
"fcmovnbe st0, st3": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd3 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x3 (3)",
@ -7335,13 +7315,12 @@
]
},
"fcmovnbe st0, st4": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd4 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x4 (4)",
@ -7356,13 +7335,12 @@
]
},
"fcmovnbe st0, st5": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd5 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x5 (5)",
@ -7377,13 +7355,12 @@
]
},
"fcmovnbe st0, st6": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd6 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x6 (6)",
@ -7398,13 +7375,12 @@
]
},
"fcmovnbe st0, st7": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd7 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x7 (7)",
@ -7648,7 +7624,7 @@
]
},
"fucomi st0, st0": {
"ExpectedInstructionCount": 42,
"ExpectedInstructionCount": 43,
"Comment": [
"0xdb 11b 0xe8 /5"
],
@ -7691,6 +7667,7 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w26, w20, #0x1",
@ -7698,7 +7675,7 @@
]
},
"fucomi st0, st1": {
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 45,
"Comment": [
"0xdb 11b 0xe9 /5"
],
@ -7743,6 +7720,7 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w26, w20, #0x1",
@ -7750,7 +7728,7 @@
]
},
"fucomi st0, st2": {
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 45,
"Comment": [
"0xdb 11b 0xea /5"
],
@ -7795,6 +7773,7 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w26, w20, #0x1",
@ -7802,7 +7781,7 @@
]
},
"fucomi st0, st3": {
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 45,
"Comment": [
"0xdb 11b 0xeb /5"
],
@ -7847,6 +7826,7 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w26, w20, #0x1",
@ -7854,7 +7834,7 @@
]
},
"fucomi st0, st4": {
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 45,
"Comment": [
"0xdb 11b 0xec /5"
],
@ -7899,6 +7879,7 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w26, w20, #0x1",
@ -7906,7 +7887,7 @@
]
},
"fucomi st0, st5": {
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 45,
"Comment": [
"0xdb 11b 0xed /5"
],
@ -7951,6 +7932,7 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w26, w20, #0x1",
@ -7958,7 +7940,7 @@
]
},
"fucomi st0, st6": {
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 45,
"Comment": [
"0xdb 11b 0xee /5"
],
@ -8003,6 +7985,7 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w26, w20, #0x1",
@ -8010,7 +7993,7 @@
]
},
"fucomi st0, st7": {
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 45,
"Comment": [
"0xdb 11b 0xef /5"
],
@ -8055,6 +8038,7 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w26, w20, #0x1",
@ -8062,7 +8046,7 @@
]
},
"fcomi st0, st0": {
"ExpectedInstructionCount": 42,
"ExpectedInstructionCount": 43,
"Comment": [
"0xdb 11b 0xf0 /6"
],
@ -8105,6 +8089,7 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w26, w20, #0x1",
@ -8112,7 +8097,7 @@
]
},
"fcomi st0, st1": {
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 45,
"Comment": [
"0xdb 11b 0xf1 /6"
],
@ -8157,6 +8142,7 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w26, w20, #0x1",
@ -8164,7 +8150,7 @@
]
},
"fcomi st0, st2": {
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 45,
"Comment": [
"0xdb 11b 0xf2 /6"
],
@ -8209,6 +8195,7 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w26, w20, #0x1",
@ -8216,7 +8203,7 @@
]
},
"fcomi st0, st3": {
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 45,
"Comment": [
"0xdb 11b 0xf3 /6"
],
@ -8261,6 +8248,7 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w26, w20, #0x1",
@ -8268,7 +8256,7 @@
]
},
"fcomi st0, st4": {
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 45,
"Comment": [
"0xdb 11b 0xf4 /6"
],
@ -8313,6 +8301,7 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w26, w20, #0x1",
@ -8320,7 +8309,7 @@
]
},
"fcomi st0, st5": {
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 45,
"Comment": [
"0xdb 11b 0xf5 /6"
],
@ -8365,6 +8354,7 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w26, w20, #0x1",
@ -8372,7 +8362,7 @@
]
},
"fcomi st0, st6": {
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 45,
"Comment": [
"0xdb 11b 0xf6 /6"
],
@ -8417,6 +8407,7 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w26, w20, #0x1",
@ -8424,7 +8415,7 @@
]
},
"fcomi st0, st7": {
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 45,
"Comment": [
"0xdb 11b 0xf7 /6"
],
@ -8469,6 +8460,7 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w26, w20, #0x1",
@ -16787,7 +16779,7 @@
]
},
"fucomip st0": {
"ExpectedInstructionCount": 50,
"ExpectedInstructionCount": 51,
"Comment": [
"0xdf 11b 0xe8 /5"
],
@ -16830,6 +16822,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
@ -16845,7 +16838,7 @@
]
},
"fucomip st1": {
"ExpectedInstructionCount": 52,
"ExpectedInstructionCount": 53,
"Comment": [
"0xdf 11b 0xe9 /5"
],
@ -16891,6 +16884,7 @@
"ubfx x22, x22, #2, #1",
"orr w23, w23, w22",
"orr w24, w24, w22",
"eor x23, x23, #0x1",
"lsl x23, x23, #29",
"orr w23, w23, w24, lsl #30",
"eor w26, w22, #0x1",
@ -16905,7 +16899,7 @@
]
},
"fucomip st2": {
"ExpectedInstructionCount": 52,
"ExpectedInstructionCount": 53,
"Comment": [
"0xdf 11b 0xea /5"
],
@ -16950,6 +16944,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
@ -16965,7 +16960,7 @@
]
},
"fucomip st3": {
"ExpectedInstructionCount": 52,
"ExpectedInstructionCount": 53,
"Comment": [
"0xdf 11b 0xeb /5"
],
@ -17010,6 +17005,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
@ -17025,7 +17021,7 @@
]
},
"fucomip st4": {
"ExpectedInstructionCount": 52,
"ExpectedInstructionCount": 53,
"Comment": [
"0xdf 11b 0xec /5"
],
@ -17070,6 +17066,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
@ -17085,7 +17082,7 @@
]
},
"fucomip st5": {
"ExpectedInstructionCount": 52,
"ExpectedInstructionCount": 53,
"Comment": [
"0xdf 11b 0xed /5"
],
@ -17130,6 +17127,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
@ -17145,7 +17143,7 @@
]
},
"fucomip st6": {
"ExpectedInstructionCount": 52,
"ExpectedInstructionCount": 53,
"Comment": [
"0xdf 11b 0xee /5"
],
@ -17190,6 +17188,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
@ -17205,7 +17204,7 @@
]
},
"fucomip st7": {
"ExpectedInstructionCount": 52,
"ExpectedInstructionCount": 53,
"Comment": [
"0xdf 11b 0xef /5"
],
@ -17250,6 +17249,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
@ -17265,7 +17265,7 @@
]
},
"fcomip st0": {
"ExpectedInstructionCount": 50,
"ExpectedInstructionCount": 51,
"Comment": [
"0xdf 11b 0xf0 /6"
],
@ -17308,6 +17308,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
@ -17323,7 +17324,7 @@
]
},
"fcomip st1": {
"ExpectedInstructionCount": 52,
"ExpectedInstructionCount": 53,
"Comment": [
"0xdf 11b 0xf1 /6"
],
@ -17369,6 +17370,7 @@
"ubfx x22, x22, #2, #1",
"orr w23, w23, w22",
"orr w24, w24, w22",
"eor x23, x23, #0x1",
"lsl x23, x23, #29",
"orr w23, w23, w24, lsl #30",
"eor w26, w22, #0x1",
@ -17383,7 +17385,7 @@
]
},
"fcomip st2": {
"ExpectedInstructionCount": 52,
"ExpectedInstructionCount": 53,
"Comment": [
"0xdf 11b 0xf2 /6"
],
@ -17428,6 +17430,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
@ -17443,7 +17446,7 @@
]
},
"fcomip st3": {
"ExpectedInstructionCount": 52,
"ExpectedInstructionCount": 53,
"Comment": [
"0xdf 11b 0xf3 /6"
],
@ -17488,6 +17491,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
@ -17503,7 +17507,7 @@
]
},
"fcomip st4": {
"ExpectedInstructionCount": 52,
"ExpectedInstructionCount": 53,
"Comment": [
"0xdf 11b 0xf4 /6"
],
@ -17548,6 +17552,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
@ -17563,7 +17568,7 @@
]
},
"fcomip st5": {
"ExpectedInstructionCount": 52,
"ExpectedInstructionCount": 53,
"Comment": [
"0xdf 11b 0xf5 /6"
],
@ -17608,6 +17613,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
@ -17623,7 +17629,7 @@
]
},
"fcomip st6": {
"ExpectedInstructionCount": 52,
"ExpectedInstructionCount": 53,
"Comment": [
"0xdf 11b 0xf6 /6"
],
@ -17668,6 +17674,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
@ -17683,7 +17690,7 @@
]
},
"fcomip st7": {
"ExpectedInstructionCount": 52,
"ExpectedInstructionCount": 53,
"Comment": [
"0xdf 11b 0xf7 /6"
],
@ -17728,6 +17735,7 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",

248
unittests/InstructionCountCI/x87_f64.json
View File

@ -3336,7 +3336,7 @@
"0xda 11b 0xc0 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
@ -3354,7 +3354,7 @@
"0xda 11b 0xc1 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x1 (1)",
@ -3374,7 +3374,7 @@
"0xda 11b 0xc2 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x2 (2)",
@ -3394,7 +3394,7 @@
"0xda 11b 0xc3 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x3 (3)",
@ -3414,7 +3414,7 @@
"0xda 11b 0xc4 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x4 (4)",
@ -3434,7 +3434,7 @@
"0xda 11b 0xc5 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x5 (5)",
@ -3454,7 +3454,7 @@
"0xda 11b 0xc6 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x6 (6)",
@ -3474,7 +3474,7 @@
"0xda 11b 0xc7 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x7 (7)",
@ -3647,14 +3647,12 @@
]
},
"fcmovbe st0, st0": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 10,
"Comment": [
"0xda 11b 0xd0 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
@ -3667,14 +3665,12 @@
]
},
"fcmovbe st0, st1": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd1 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x1 (1)",
@ -3689,14 +3685,12 @@
]
},
"fcmovbe st0, st2": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd2 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x2 (2)",
@ -3711,14 +3705,12 @@
]
},
"fcmovbe st0, st3": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd3 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x3 (3)",
@ -3733,14 +3725,12 @@
]
},
"fcmovbe st0, st4": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd4 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x4 (4)",
@ -3755,14 +3745,12 @@
]
},
"fcmovbe st0, st5": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd5 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x5 (5)",
@ -3777,14 +3765,12 @@
]
},
"fcmovbe st0, st6": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd6 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x6 (6)",
@ -3799,14 +3785,12 @@
]
},
"fcmovbe st0, st7": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xda 11b 0xd7 /0"
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"csetm x21, hs",
"csel x20, x20, x21, eq",
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x7 (7)",
@ -4245,7 +4229,7 @@
"0xdb 11b 0xc0 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
@ -4263,7 +4247,7 @@
"0xdb 11b 0xc1 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x1 (1)",
@ -4283,7 +4267,7 @@
"0xdb 11b 0xc2 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x2 (2)",
@ -4303,7 +4287,7 @@
"0xdb 11b 0xc3 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x3 (3)",
@ -4323,7 +4307,7 @@
"0xdb 11b 0xc4 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x4 (4)",
@ -4343,7 +4327,7 @@
"0xdb 11b 0xc5 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x5 (5)",
@ -4363,7 +4347,7 @@
"0xdb 11b 0xc6 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x6 (6)",
@ -4383,7 +4367,7 @@
"0xdb 11b 0xc7 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x7 (7)",
@ -4556,13 +4540,12 @@
]
},
"fcmovnbe st0, st0": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"0xdb 11b 0xd0 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
@ -4575,13 +4558,12 @@
]
},
"fcmovnbe st0, st1": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd1 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x1 (1)",
@ -4596,13 +4578,12 @@
]
},
"fcmovnbe st0, st2": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd2 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x2 (2)",
@ -4617,13 +4598,12 @@
]
},
"fcmovnbe st0, st3": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd3 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x3 (3)",
@ -4638,13 +4618,12 @@
]
},
"fcmovnbe st0, st4": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd4 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x4 (4)",
@ -4659,13 +4638,12 @@
]
},
"fcmovnbe st0, st5": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd5 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x5 (5)",
@ -4680,13 +4658,12 @@
]
},
"fcmovnbe st0, st6": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd6 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x6 (6)",
@ -4701,13 +4678,12 @@
]
},
"fcmovnbe st0, st7": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": [
"0xdb 11b 0xd7 /2"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"csel x20, x20, xzr, ne",
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x7 (7)",
@ -4973,11 +4949,11 @@
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -4998,11 +4974,11 @@
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -5023,11 +4999,11 @@
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -5048,11 +5024,11 @@
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -5073,11 +5049,11 @@
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -5098,11 +5074,11 @@
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -5123,11 +5099,11 @@
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -5148,11 +5124,11 @@
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -5171,11 +5147,11 @@
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -5196,11 +5172,11 @@
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -5221,11 +5197,11 @@
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -5246,11 +5222,11 @@
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -5271,11 +5247,11 @@
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -5296,11 +5272,11 @@
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -5321,11 +5297,11 @@
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -5346,11 +5322,11 @@
"cset w20, eq",
"cset w21, lo",
"cset w22, vs",
"orr w21, w21, w22",
"cset w26, vc",
"and w21, w21, w26",
"lsl x21, x21, #29",
"orr w20, w20, w22",
"orr w20, w21, w20, lsl #30",
"eor w26, w22, #0x1",
"msr nzcv, x20"
]
},
@ -9863,11 +9839,11 @@
"cset w22, eq",
"cset w23, lo",
"cset w24, vs",
"orr w23, w23, w24",
"cset w26, vc",
"and w23, w23, w26",
"lsl x23, x23, #29",
"orr w22, w22, w24",
"orr w22, w23, w22, lsl #30",
"eor w26, w24, #0x1",
"ldrb w23, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w23, w21",
@ -9896,11 +9872,11 @@
"cset w22, eq",
"cset w23, lo",
"cset w24, vs",
"orr w23, w23, w24",
"cset w26, vc",
"and w23, w23, w26",
"lsl x23, x23, #29",
"orr w22, w22, w24",
"orr w22, w23, w22, lsl #30",
"eor w26, w24, #0x1",
"ldrb w23, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w23, w21",
@ -9929,11 +9905,11 @@
"cset w22, eq",
"cset w23, lo",
"cset w24, vs",
"orr w23, w23, w24",
"cset w26, vc",
"and w23, w23, w26",
"lsl x23, x23, #29",
"orr w22, w22, w24",
"orr w22, w23, w22, lsl #30",
"eor w26, w24, #0x1",
"ldrb w23, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w23, w21",
@ -9962,11 +9938,11 @@
"cset w22, eq",
"cset w23, lo",
"cset w24, vs",
"orr w23, w23, w24",
"cset w26, vc",
"and w23, w23, w26",
"lsl x23, x23, #29",
"orr w22, w22, w24",
"orr w22, w23, w22, lsl #30",
"eor w26, w24, #0x1",
"ldrb w23, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w23, w21",
@ -9995,11 +9971,11 @@
"cset w22, eq",
"cset w23, lo",
"cset w24, vs",
"orr w23, w23, w24",
"cset w26, vc",
"and w23, w23, w26",
"lsl x23, x23, #29",
"orr w22, w22, w24",
"orr w22, w23, w22, lsl #30",
"eor w26, w24, #0x1",
"ldrb w23, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w23, w21",
@ -10028,11 +10004,11 @@
"cset w22, eq",
"cset w23, lo",
"cset w24, vs",
"orr w23, w23, w24",
"cset w26, vc",
"and w23, w23, w26",
"lsl x23, x23, #29",
"orr w22, w22, w24",
"orr w22, w23, w22, lsl #30",
"eor w26, w24, #0x1",
"ldrb w23, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w23, w21",
@ -10061,11 +10037,11 @@
"cset w22, eq",
"cset w23, lo",
"cset w24, vs",
"orr w23, w23, w24",
"cset w26, vc",
"and w23, w23, w26",
"lsl x23, x23, #29",
"orr w22, w22, w24",
"orr w22, w23, w22, lsl #30",
"eor w26, w24, #0x1",
"ldrb w23, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w23, w21",
@ -10094,11 +10070,11 @@
"cset w22, eq",
"cset w23, lo",
"cset w24, vs",
"orr w23, w23, w24",
"cset w26, vc",
"and w23, w23, w26",
"lsl x23, x23, #29",
"orr w22, w22, w24",
"orr w22, w23, w22, lsl #30",
"eor w26, w24, #0x1",
"ldrb w23, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w23, w21",
@ -10125,11 +10101,11 @@
"cset w22, eq",
"cset w23, lo",
"cset w24, vs",
"orr w23, w23, w24",
"cset w26, vc",
"and w23, w23, w26",
"lsl x23, x23, #29",
"orr w22, w22, w24",
"orr w22, w23, w22, lsl #30",
"eor w26, w24, #0x1",
"ldrb w23, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w23, w21",
@ -10158,11 +10134,11 @@
"cset w22, eq",
"cset w23, lo",
"cset w24, vs",
"orr w23, w23, w24",
"cset w26, vc",
"and w23, w23, w26",
"lsl x23, x23, #29",
"orr w22, w22, w24",
"orr w22, w23, w22, lsl #30",
"eor w26, w24, #0x1",
"ldrb w23, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w23, w21",
@ -10191,11 +10167,11 @@
"cset w22, eq",
"cset w23, lo",
"cset w24, vs",
"orr w23, w23, w24",
"cset w26, vc",
"and w23, w23, w26",
"lsl x23, x23, #29",
"orr w22, w22, w24",
"orr w22, w23, w22, lsl #30",
"eor w26, w24, #0x1",
"ldrb w23, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w23, w21",
@ -10224,11 +10200,11 @@
"cset w22, eq",
"cset w23, lo",
"cset w24, vs",
"orr w23, w23, w24",
"cset w26, vc",
"and w23, w23, w26",
"lsl x23, x23, #29",
"orr w22, w22, w24",
"orr w22, w23, w22, lsl #30",
"eor w26, w24, #0x1",
"ldrb w23, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w23, w21",
@ -10257,11 +10233,11 @@
"cset w22, eq",
"cset w23, lo",
"cset w24, vs",
"orr w23, w23, w24",
"cset w26, vc",
"and w23, w23, w26",
"lsl x23, x23, #29",
"orr w22, w22, w24",
"orr w22, w23, w22, lsl #30",
"eor w26, w24, #0x1",
"ldrb w23, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w23, w21",
@ -10290,11 +10266,11 @@
"cset w22, eq",
"cset w23, lo",
"cset w24, vs",
"orr w23, w23, w24",
"cset w26, vc",
"and w23, w23, w26",
"lsl x23, x23, #29",
"orr w22, w22, w24",
"orr w22, w23, w22, lsl #30",
"eor w26, w24, #0x1",
"ldrb w23, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w23, w21",
@ -10323,11 +10299,11 @@
"cset w22, eq",
"cset w23, lo",
"cset w24, vs",
"orr w23, w23, w24",
"cset w26, vc",
"and w23, w23, w26",
"lsl x23, x23, #29",
"orr w22, w22, w24",
"orr w22, w23, w22, lsl #30",
"eor w26, w24, #0x1",
"ldrb w23, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w23, w21",
@ -10356,11 +10332,11 @@
"cset w22, eq",
"cset w23, lo",
"cset w24, vs",
"orr w23, w23, w24",
"cset w26, vc",
"and w23, w23, w26",
"lsl x23, x23, #29",
"orr w22, w22, w24",
"orr w22, w23, w22, lsl #30",
"eor w26, w24, #0x1",
"ldrb w23, [x28, #1298]",
"lsl w21, w21, w20",
"bic w21, w23, w21",