FEX-Emu/FEX
1
0
Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2025-02-21 23:31:24 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Arm64: Preserve NZCV in VInsertElement

Browse Source 
So we don't need to mark VInsertElement as implicit clobber in the common case.
Only afects sve256 which doesn't exist yet.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig 2023-10-23 09:59:51 -04:00
parent e455996dbd
commit 42259974c4
1 changed files with 7 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
View File

@ -3694,9 +3694,16 @@ DEF_OP(VInsElement) {
} else {
const auto UpperBound = 16 >> FEXCore::ilog2(ElementSize);
const auto TargetElement = static_cast<int>(DestIdx) - UpperBound;
// FIXME: We should rework this op to avoid the NZCV spill/fill dance.
mrs(TMP1, ARMEmitter::SystemRegister::NZCV);
index(SubRegSize, VTMP1.Z(), -UpperBound, 1);
cmpeq(SubRegSize, Predicate, PRED_TMP_32B.Zeroing(), VTMP1.Z(), TargetElement);
mov(SubRegSize, Dst.Z(), Predicate.Merging(), VTMP2.Z());
// Restore NZCV
msr(ARMEmitter::SystemRegister::NZCV, TMP1);
}
}
else {