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ARMEmitter: Handle SVE FP multiply-add long group

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Lioncache 2023-08-09 14:59:50 -04:00
parent 48a3271fbc
commit 444961ad79
2 changed files with 73 additions and 2 deletions
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40
External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl vendored
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@ -2171,8 +2171,32 @@ public:
// SVE Floating Point Widening Multiply-Add // SVE Floating Point Widening Multiply-Add
// SVE BFloat16 floating-point dot product // SVE BFloat16 floating-point dot product
// XXX: // XXX:
// SVE floating-point multiply-add long // SVE floating-point multiply-add long
// XXX: void fmlalb(SubRegSize dstsize, ZRegister zda, ZRegister zn, ZRegister zm) {
SVEFPMultiplyAddLong(0, 0, 0, dstsize, zda, zn, zm);
}
void fmlalt(SubRegSize dstsize, ZRegister zda, ZRegister zn, ZRegister zm) {
SVEFPMultiplyAddLong(0, 0, 1, dstsize, zda, zn, zm);
}
void fmlslb(SubRegSize dstsize, ZRegister zda, ZRegister zn, ZRegister zm) {
SVEFPMultiplyAddLong(0, 1, 0, dstsize, zda, zn, zm);
}
void fmlslt(SubRegSize dstsize, ZRegister zda, ZRegister zn, ZRegister zm) {
SVEFPMultiplyAddLong(0, 1, 1, dstsize, zda, zn, zm);
}
void bfmlalb(SubRegSize dstsize, ZRegister zda, ZRegister zn, ZRegister zm) {
SVEFPMultiplyAddLong(1, 0, 0, dstsize, zda, zn, zm);
}
void bfmlalt(SubRegSize dstsize, ZRegister zda, ZRegister zn, ZRegister zm) {
SVEFPMultiplyAddLong(1, 0, 1, dstsize, zda, zn, zm);
}
void bfmlslb(SubRegSize dstsize, ZRegister zda, ZRegister zn, ZRegister zm) {
SVEFPMultiplyAddLong(1, 1, 0, dstsize, zda, zn, zm);
}
void bfmlslt(SubRegSize dstsize, ZRegister zda, ZRegister zn, ZRegister zm) {
SVEFPMultiplyAddLong(1, 1, 1, dstsize, zda, zn, zm);
}
// SVE Floating Point Arithmetic - Predicated // SVE Floating Point Arithmetic - Predicated
void ftmad(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm, uint32_t imm) { void ftmad(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm, uint32_t imm) {
@ -4589,6 +4613,20 @@ private:
dc32(Inst); dc32(Inst);
} }
void SVEFPMultiplyAddLong(uint32_t o2, uint32_t op, uint32_t T, SubRegSize dstsize,
ZRegister zda, ZRegister zn, ZRegister zm) {
LOGMAN_THROW_AA_FMT(dstsize == SubRegSize::i32Bit, "Destination size must be 32-bit.");
uint32_t Instr = 0b0110'0100'1010'0000'1000'0000'0000'0000;
Instr |= o2 << 22;
Instr |= zm.Idx() << 16;
Instr |= op << 13;
Instr |= T << 10;
Instr |= zn.Idx() << 5;
Instr |= zda.Idx();
dc32(Instr);
}
void SVEFPMatrixMultiplyAccumulate(SubRegSize size, ZRegister zda, ZRegister zn, ZRegister zm) { void SVEFPMatrixMultiplyAccumulate(SubRegSize size, ZRegister zda, ZRegister zn, ZRegister zm) {
LOGMAN_THROW_AA_FMT(size == SubRegSize::i32Bit || size == SubRegSize::i64Bit, LOGMAN_THROW_AA_FMT(size == SubRegSize::i32Bit || size == SubRegSize::i64Bit,
"SubRegSize must be 32-bit or 64-bit"); "SubRegSize must be 32-bit or 64-bit");

35
External/FEXCore/unittests/Emitter/SVE_Tests.cpp vendored
View File

@ -3301,7 +3301,40 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE BFloat16 floating-point do
// TODO: Implement in emitter. // TODO: Implement in emitter.
} }
TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE floating-point multiply-add long") { TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE floating-point multiply-add long") {
// TODO: Implement in emitter. TEST_SINGLE(fmlalb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "fmlalb z30.s, z29.h, z28.h");
TEST_SINGLE(fmlalb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "fmlalb z30.s, z29.h, z28.h");
TEST_SINGLE(fmlalb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "fmlalb z30.s, z29.h, z28.h");
TEST_SINGLE(fmlalt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "fmlalt z30.s, z29.h, z28.h");
TEST_SINGLE(fmlalt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "fmlalt z30.s, z29.h, z28.h");
TEST_SINGLE(fmlalt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "fmlalt z30.s, z29.h, z28.h");
TEST_SINGLE(fmlslb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "fmlslb z30.s, z29.h, z28.h");
TEST_SINGLE(fmlslb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "fmlslb z30.s, z29.h, z28.h");
TEST_SINGLE(fmlslb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "fmlslb z30.s, z29.h, z28.h");
TEST_SINGLE(fmlslt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "fmlslt z30.s, z29.h, z28.h");
TEST_SINGLE(fmlslt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "fmlslt z30.s, z29.h, z28.h");
TEST_SINGLE(fmlslt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "fmlslt z30.s, z29.h, z28.h");
// XXX: vixl's diassembler doesn't support these. Re-enable when it does
// or upon switching disassemblers.
// TEST_SINGLE(bfmlalb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bfmlalb z30.s, z29.h, z28.h");
// TEST_SINGLE(bfmlalb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bfmlalb z30.s, z29.h, z28.h");
// TEST_SINGLE(bfmlalb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bfmlalb z30.s, z29.h, z28.h");
// TEST_SINGLE(bfmlalt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bfmlalt z30.s, z29.h, z28.h");
// TEST_SINGLE(bfmlalt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bfmlalt z30.s, z29.h, z28.h");
// TEST_SINGLE(bfmlalt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bfmlalt z30.s, z29.h, z28.h");
// TEST_SINGLE(bfmlalb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bfmlslb z30.s, z29.h, z28.h");
// TEST_SINGLE(bfmlalb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bfmlslb z30.s, z29.h, z28.h");
// TEST_SINGLE(bfmlalb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bfmlslb z30.s, z29.h, z28.h");
// TEST_SINGLE(bfmlslt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bfmlslt z30.s, z29.h, z28.h");
// TEST_SINGLE(bfmlslt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bfmlslt z30.s, z29.h, z28.h");
// TEST_SINGLE(bfmlslt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bfmlslt z30.s, z29.h, z28.h");
} }
TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE floating-point arithmetic (predicated)") { TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE floating-point arithmetic (predicated)") {
TEST_SINGLE(ftmad(SubRegSize::i16Bit, ZReg::z30, ZReg::z30, ZReg::z28, 7), "ftmad z30.h, z30.h, z28.h, #7"); TEST_SINGLE(ftmad(SubRegSize::i16Bit, ZReg::z30, ZReg::z30, ZReg::z28, 7), "ftmad z30.h, z30.h, z28.h, #7");