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OpcodeDispatcher: Handle VPSRLQ (vector)

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Also mark VPMOVMSKB as UNDEC, since it's not implemented yet.
This commit is contained in:
lioncash 2022-12-16 22:10:52 +00:00
parent b6e82965df
commit 47b21fa758
4 changed files with 82 additions and 2 deletions
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1
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp vendored
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@ -5914,6 +5914,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
{OPD(1, 0b01, 0xD1), 1, &OpDispatchBuilder::VPSRLDOp<2>},
{OPD(1, 0b01, 0xD2), 1, &OpDispatchBuilder::VPSRLDOp<4>},
{OPD(1, 0b01, 0xD3), 1, &OpDispatchBuilder::VPSRLDOp<8>},
{OPD(1, 0b01, 0xD4), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VADD, 8>},
{OPD(1, 0b01, 0xD6), 1, &OpDispatchBuilder::MOVQOp},
{OPD(1, 0b01, 0xD7), 1, &OpDispatchBuilder::UnimplementedOp},

2
External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp vendored
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@ -1310,6 +1310,8 @@ template
void OpDispatchBuilder::VPSRLDOp<2>(OpcodeArgs);
template
void OpDispatchBuilder::VPSRLDOp<4>(OpcodeArgs);
template
void OpDispatchBuilder::VPSRLDOp<8>(OpcodeArgs);
template<size_t ElementSize>
void OpDispatchBuilder::PSRLI(OpcodeArgs) {

4
External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp vendored
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@ -204,11 +204,11 @@ void InitializeVEXTables() {
{OPD(1, 0b01, 0xD1), 1, X86InstInfo{"VPSRLW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b01, 0xD2), 1, X86InstInfo{"VPSRLD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b01, 0xD3), 1, X86InstInfo{"VPSRLQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b01, 0xD3), 1, X86InstInfo{"VPSRLQ", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b01, 0xD4), 1, X86InstInfo{"VPADDQ", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b01, 0xD5), 1, X86InstInfo{"VPMULLW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b01, 0xD6), 1, X86InstInfo{"VMOVQ", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b01, 0xD7), 1, X86InstInfo{"VPMOVMSKB", TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_DST_GPR | FLAGS_SF_MOD_REG_ONLY, 0, nullptr}},
{OPD(1, 0b01, 0xD7), 1, X86InstInfo{"VPMOVMSKB", TYPE_UNDEC, FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_DST_GPR | FLAGS_SF_MOD_REG_ONLY, 0, nullptr}},
{OPD(1, 0b01, 0xD8), 1, X86InstInfo{"VPSUBUSB", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b01, 0xD9), 1, X86InstInfo{"VPSUBUSW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},

77
unittests/ASM/VEX/vpsrlq.asm Normal file
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@ -0,0 +1,77 @@
%ifdef CONFIG
{
"HostFeatures": ["AVX"],
"RegData": {
"XMM1": ["0x20A121A222A323A4", "0x28A929AA2AAB2BAC", "0x0000000000000000", "0x0000000000000000"],
"XMM2": ["0x0041424344454647", "0x0051525354555657", "0x0000000000000000", "0x0000000000000000"],
"XMM3": ["0x0000414243444546", "0x0000515253545556", "0x0000000000000000", "0x0000000000000000"],
"XMM4": ["0x0000000041424344", "0x0000000051525354", "0x0000000000000000", "0x0000000000000000"],
"XMM5": ["0x0000000000000000", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
"XMM6": ["0x20A121A222A323A4", "0x28A929AA2AAB2BAC", "0x20A121A222A323A4", "0x28A929AA2AAB2BAC"],
"XMM7": ["0x0041424344454647", "0x0051525354555657", "0x0041424344454647", "0x0051525354555657"],
"XMM8": ["0x0000414243444546", "0x0000515253545556", "0x0000414243444546", "0x0000515253545556"],
"XMM9": ["0x0000000041424344", "0x0000000051525354", "0x0000000041424344", "0x0000000051525354"],
"XMM10": ["0x0000000000000000", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
"XMM12": ["0x20A121A222A323A4", "0x28A929AA2AAB2BAC", "0x0000000000000000", "0x0000000000000000"],
"XMM13": ["0x20A121A222A323A4", "0x28A929AA2AAB2BAC", "0x20A121A222A323A4", "0x28A929AA2AAB2BAC"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
lea rdx, [rel .data]
vmovapd ymm0, [rdx]
vpsrlq xmm1, xmm0, [rdx + 32 * 1]
vpsrlq xmm2, xmm0, [rdx + 32 * 2]
vpsrlq xmm3, xmm0, [rdx + 32 * 3]
vpsrlq xmm4, xmm0, [rdx + 32 * 4]
vpsrlq xmm5, xmm0, [rdx + 32 * 5]
vpsrlq ymm6, ymm0, [rdx + 32 * 1]
vpsrlq ymm7, ymm0, [rdx + 32 * 2]
vpsrlq ymm8, ymm0, [rdx + 32 * 3]
vpsrlq ymm9, ymm0, [rdx + 32 * 4]
vpsrlq ymm10, ymm0, [rdx + 32 * 5]
vmovapd ymm11, [rdx + 32]
vpsrlw xmm12, xmm0, xmm11
vpsrlw ymm13, ymm0, xmm11
hlt
align 32
.data:
dq 0x4142434445464748
dq 0x5152535455565758
dq 0x4142434445464748
dq 0x5152535455565758
dq 0x0000000000000001
dq 0x0000000000000000
dq 0x0000000000000000
dq 0x0000000000000000
dq 0x0000000000000008
dq 0x0000000000000000
dq 0x0000000000000000
dq 0x0000000000000000
dq 0x0000000000000010
dq 0x0000000000000000
dq 0x0000000000000000
dq 0x0000000000000000
dq 0x0000000000000020
dq 0x0000000000000000
dq 0x0000000000000000
dq 0x0000000000000000
dq 0x0000000000000040
dq 0x0000000000000000
dq 0x0000000000000000
dq 0x0000000000000000