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RegisterAllocationPass: drop prewritable check

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always true.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig 2024-05-08 14:24:41 -04:00
parent 47242dc190
commit 4d503d3155
1 changed files with 1 additions and 15 deletions
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16
FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
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@ -461,20 +461,6 @@ void ConstrainedRAPass::CalculateLiveRange(FEXCore::IR::IRListView* IR) {
}
void ConstrainedRAPass::OptimizeStaticRegisters(FEXCore::IR::IRListView* IR) {
// Helpers
// Is an OP_STOREREGISTER eligible to write directly to the SRA reg?
auto IsPreWritable = [this](uint8_t Size, RegisterClassType Class) {
LOGMAN_THROW_A_FMT(Class == GPRClass || Class == FPRClass, "Unexpected class {}", Class);
if (Class == GPRClass) {
return Size == 8 || Size == 4;
} else if (Class == FPRClass) {
return Size == 16 || (Size == 32 && SupportsAVX);
}
return false; // Unknown
};
auto GprSize = Graph->Set.Classes[GPRFixedClass.Val].PhysicalCount;
auto MapsSize = Graph->Set.Classes[GPRFixedClass.Val].PhysicalCount + Graph->Set.Classes[FPRFixedClass.Val].PhysicalCount;
StaticMaps.resize(MapsSize);
@ -516,7 +502,7 @@ void ConstrainedRAPass::OptimizeStaticRegisters(FEXCore::IR::IRListView* IR) {
const auto OpID = Op->Value.ID();
auto& OpLiveRange = LiveRanges[OpID.Value];
if (IsPreWritable(IROp->Size, Op->Class) && OpLiveRange.PrefferedRegister.IsInvalid() && !OpLiveRange.Global) {
if (OpLiveRange.PrefferedRegister.IsInvalid() && !OpLiveRange.Global) {
// Pre-write and sra-allocate in the defining node - this might be undone if a read before the actual store happens
SRA_DEBUG("Prewritting ssa{} (Store in ssa{})\n", OpID, Node);
OpLiveRange.PrefferedRegister = GetRegForSRA(Op->Class, Op->Reg);