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Extends PSHUFB unit tests to ensure correct behaviour
Explicitly testign bits being set in the reserved bits
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36
unittests/ASM/H0F38/66_00_2.asm
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36
unittests/ASM/H0F38/66_00_2.asm
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%ifdef CONFIG
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{
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"RegData": {
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"XMM0": ["0x5858585858585858", "0x5858585858585858"],
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"XMM1": ["0x0", "0x0"]
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}
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}
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%endif
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mov rdx, 0xe0000000
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mov rax, 0x4142434445464748
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mov [rdx + 8 * 0], rax
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mov rax, 0x5152535455565758
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mov [rdx + 8 * 1], rax
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movaps xmm0, [rdx + 8 * 0]
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movaps xmm1, [rdx + 8 * 0]
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lea rdx, [rel .data]
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pshufb xmm0, [rdx + 8 * 0]
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pshufb xmm1, [rdx + 8 * 2]
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hlt
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align 8
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.data:
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; Test bits with trash data in reserved bits to ensure it is ignored
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; Select single element
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dq 0x7878787878787878
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dq 0x7878787878787878
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; Clear element
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dq 0xF0F0F0F0F0F0F0F0
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dq 0xF0F0F0F0F0F0F0F0
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28
unittests/ASM/H0F38/XX_00_2.asm
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28
unittests/ASM/H0F38/XX_00_2.asm
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%ifdef CONFIG
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{
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"RegData": {
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"MM0": "0x4444444444444444",
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"MM1": "0x0"
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}
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}
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%endif
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lea rdx, [rel .data]
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movq mm0, [rdx + 8 * 0]
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movq mm1, [rdx + 8 * 0]
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pshufb mm0, [rdx + 8 * 1]
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pshufb mm1, [rdx + 8 * 2]
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hlt
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align 8
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.data:
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; Incoming vector
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dq 0x4142434445464748
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; Test bits with trash data in reserved bits to ensure it is ignored
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; Select single element
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dq 0x7C7C7C7C7C7C7C7C
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; Clear element
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dq 0xF8F8F8F8F8F8F8F8
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