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https://github.com/FEX-Emu/FEX.git
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json_ir_generator: stop prefixing arguments
stop prefixing the arguments when we generate allocate ops (in particular), this is more convenient and simpler. in exchange we need to prefix Op to avoid a collision on fcmpscalarinsert which has an argument named Op, but that's a local change at least. came up when experimenting with new IR, but I think this is probably a win by itself. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig
parent
d507f4c9b1
commit
587b924de9
@ -207,7 +207,7 @@ def parse_ops(ops):
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(OpArg.Type == "GPR" or
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OpArg.Type == "GPRPair" or
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OpArg.Type == "FPR")):
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OpDef.EmitValidation.append("GetOpRegClass({}) == InvalidClass || WalkFindRegClass({}) == {}Class".format(NameWithPrefix, NameWithPrefix, OpArg.Type))
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OpDef.EmitValidation.append(f"GetOpRegClass({ArgName}) == InvalidClass || WalkFindRegClass({ArgName}) == {OpArg.Type}Class")
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OpArg.Name = ArgName
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OpArg.NameWithPrefix = NameWithPrefix
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@ -268,12 +268,8 @@ def parse_ops(ops):
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for i in range(len(OpDef.EmitValidation)):
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# Patch up all the argument names
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for Arg in OpDef.Arguments:
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if Arg.Temporary:
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# Temporary ops just replace all instances no prefix variant
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OpDef.EmitValidation[i] = OpDef.EmitValidation[i].replace(Arg.NameWithPrefix, Arg.Name)
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else:
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# All other ops replace $ with _ variant for argument passed in
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OpDef.EmitValidation[i] = OpDef.EmitValidation[i].replace(Arg.NameWithPrefix, "_{}".format(Arg.Name))
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# Temporary ops just replace all instances no prefix variant
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OpDef.EmitValidation[i] = OpDef.EmitValidation[i].replace(Arg.NameWithPrefix, Arg.Name)
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#OpDef.print()
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@ -668,11 +664,11 @@ def print_ir_allocator_helpers():
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output_file.write("{} {}".format(CType, arg.Name));
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elif arg.IsSSA:
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# SSA value
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output_file.write("OrderedNode *_{}".format(arg.Name))
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output_file.write("OrderedNode *{}".format(arg.Name))
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else:
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# User defined op that is stored
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CType = IRTypesToCXX[arg.Type].CXXName
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output_file.write("{} _{}".format(CType, arg.Name));
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output_file.write("{} {}".format(CType, arg.Name));
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if arg.DefaultInitializer != None:
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output_file.write(" = {}".format(arg.DefaultInitializer))
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@ -691,23 +687,23 @@ def print_ir_allocator_helpers():
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if op.LoweredX87:
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output_file.write("\t\tRecordX87Use();\n")
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output_file.write("\t\tauto Op = AllocateOp<IROp_{}, IROps::OP_{}>();\n".format(op.Name, op.Name.upper()))
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output_file.write("\t\tauto _Op = AllocateOp<IROp_{}, IROps::OP_{}>();\n".format(op.Name, op.Name.upper()))
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if op.SSAArgNum != 0:
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output_file.write("\t\tauto ListDataBegin = DualListData.ListBegin();\n")
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for arg in op.Arguments:
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if arg.IsSSA:
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output_file.write("\t\tOp.first->{} = _{}->Wrapped(ListDataBegin);\n".format(arg.Name, arg.Name))
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output_file.write("\t\t_Op.first->{} = {}->Wrapped(ListDataBegin);\n".format(arg.Name, arg.Name))
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if op.SSAArgNum != 0:
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for arg in op.Arguments:
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if arg.IsSSA:
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output_file.write("\t\t_{}->AddUse();\n".format(arg.Name))
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output_file.write("\t\t{}->AddUse();\n".format(arg.Name))
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if len(op.Arguments) != 0:
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for arg in op.Arguments:
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if not arg.Temporary and not arg.IsSSA:
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output_file.write("\t\tOp.first->{} = _{};\n".format(arg.Name, arg.Name))
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output_file.write("\t\t_Op.first->{} = {};\n".format(arg.Name, arg.Name))
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if (op.HasDest):
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# We can only infer a size if we have arguments
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@ -717,22 +713,22 @@ def print_ir_allocator_helpers():
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if len(op.Arguments) != 0:
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for arg in op.Arguments:
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if arg.IsSSA:
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output_file.write("\t\tuint8_t Size{} = GetOpSize(_{});\n".format(arg.Name, arg.Name))
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output_file.write("\t\tuint8_t Size{} = GetOpSize({});\n".format(arg.Name, arg.Name))
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for arg in op.Arguments:
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if arg.IsSSA:
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output_file.write("\t\tInferSize = std::max(InferSize, Size{});\n".format(arg.Name))
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output_file.write("\t\tOp.first->Header.Size = InferSize;\n")
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output_file.write("\t\t_Op.first->Header.Size = InferSize;\n")
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# Some ops without a destination still need an operating size
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# Effectively reusing the destination size value for operation size
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if op.DestSize != None:
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output_file.write("\t\tOp.first->Header.Size = {};\n".format(op.DestSize))
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output_file.write("\t\t_Op.first->Header.Size = {};\n".format(op.DestSize))
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if op.NumElements == None:
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output_file.write("\t\tOp.first->Header.ElementSize = Op.first->Header.Size / ({});\n".format(1))
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output_file.write("\t\t_Op.first->Header.ElementSize = _Op.first->Header.Size / ({});\n".format(1))
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else:
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output_file.write("\t\tOp.first->Header.ElementSize = Op.first->Header.Size / ({});\n".format(op.NumElements))
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output_file.write("\t\t_Op.first->Header.ElementSize = _Op.first->Header.Size / ({});\n".format(op.NumElements))
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# Insert validation here
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if op.EmitValidation != None:
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@ -743,7 +739,7 @@ def print_ir_allocator_helpers():
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output_file.write("\tLOGMAN_THROW_A_FMT({}, \"{}\");\n".format(Validation, Sanitized))
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output_file.write("\t\t#endif\n")
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output_file.write("\t\treturn Op;\n")
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output_file.write("\t\treturn _Op;\n")
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output_file.write("\t}\n\n")
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output_file.write("#undef IROP_ALLOCATE_HELPERS\n")
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@ -286,7 +286,7 @@
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"Desc": ["Exits the current JIT function with a target RIP"
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],
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"HasSideEffects": true,
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"DestSize": "GetOpSize(_NewRIP)"
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"DestSize": "GetOpSize(NewRIP)"
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},
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"Break BreakDefinition:$Reason": {
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"HasSideEffects": true
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@ -648,7 +648,7 @@
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"Desc": ["Does a cacheline prefetch operation"
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],
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"EmitValidation": [
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"_CacheLevel > 0 && _CacheLevel < 4"
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"CacheLevel > 0 && CacheLevel < 4"
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],
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"HasSideEffects": true,
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"DestSize": "8"
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@ -661,7 +661,7 @@
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"HasSideEffects": true,
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"DestSize": "RegisterSize",
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"EmitValidation": [
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"_Offset % RegisterSize == 0",
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"Offset % RegisterSize == 0",
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"RegisterSize == FEXCore::IR::OpSize::i128Bit || RegisterSize == FEXCore::IR::OpSize::i256Bit"
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]
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},
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@ -673,7 +673,7 @@
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"HasSideEffects": true,
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"DestSize": "RegisterSize",
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"EmitValidation": [
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"_Offset % RegisterSize == 0",
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"Offset % RegisterSize == 0",
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"RegisterSize == FEXCore::IR::OpSize::i128Bit"
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]
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},
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@ -685,7 +685,7 @@
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"HasSideEffects": true,
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"DestSize": "RegisterSize",
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"EmitValidation": [
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"_Offset % RegisterSize == 0",
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"Offset % RegisterSize == 0",
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"RegisterSize == FEXCore::IR::OpSize::i128Bit || RegisterSize == FEXCore::IR::OpSize::i256Bit"
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]
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}
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@ -1068,7 +1068,7 @@
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"DestSize": "Size",
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"EmitValidation": [
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"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit",
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"_Shift != ShiftType::ROR"
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"Shift != ShiftType::ROR"
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]
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},
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"GPR = AddWithFlags OpSize:#Size, GPR:$Src1, GPR:$Src2": {
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@ -1168,7 +1168,7 @@
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"DestSize": "Size",
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"EmitValidation": [
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"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit",
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"_Shift != ShiftType::ROR"
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"Shift != ShiftType::ROR"
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]
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},
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"GPR = SubWithFlags OpSize:#Size, GPR:$Src1, GPR:$Src2": {
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@ -1453,7 +1453,7 @@
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"DestSize": "ResultSize",
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"ImplicitFlagClobber": true,
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"EmitValidation": [
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"_CompareSize == FEXCore::IR::OpSize::i32Bit || _CompareSize == FEXCore::IR::OpSize::i64Bit || _CompareSize == FEXCore::IR::OpSize::i128Bit",
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"CompareSize == FEXCore::IR::OpSize::i32Bit || CompareSize == FEXCore::IR::OpSize::i64Bit || CompareSize == FEXCore::IR::OpSize::i128Bit",
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"ResultSize == FEXCore::IR::OpSize::i32Bit || ResultSize == FEXCore::IR::OpSize::i64Bit",
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"WalkFindRegClass($Cmp1) == WalkFindRegClass($Cmp2)"
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]
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