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OpcodeDispatcher: Implement MULX

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This commit is contained in:
lioncash 2021-11-12 09:10:36 -05:00
parent c6662a46b5
commit 59469705e4
4 changed files with 54 additions and 1 deletions
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16
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp vendored
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@ -2372,6 +2372,21 @@ void OpDispatchBuilder::RORX(OpcodeArgs) {
StoreResult(GPRClass, Op, Result, -1);
}
void OpDispatchBuilder::MULX(OpcodeArgs) {
// RDX is the implied source operand in the instruction
const auto RDXOffset = offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RDX]);
const auto OperandSize = GetSrcSize(Op);
OrderedNode* Src1 = LoadSource(GPRClass, Op, Op->Src[1], Op->Flags, -1);
OrderedNode* Src2 = _LoadContext(OperandSize, RDXOffset, GPRClass);
OrderedNode* ResultLo = _UMul(Src1, Src2);
OrderedNode* ResultHi = _UMulH(Src1, Src2);
StoreResult(GPRClass, Op, Op->Src[0], ResultLo, -1);
StoreResult(GPRClass, Op, Op->Dest, ResultHi, -1);
}
void OpDispatchBuilder::ADXOp(OpcodeArgs) {
// Handles ADCX and ADOX
@ -6079,6 +6094,7 @@ constexpr uint16_t PF_F2 = 3;
{OPD(2, 0b01, 0x79), 1, &OpDispatchBuilder::UnimplementedOp},
{OPD(2, 0b00, 0xF2), 1, &OpDispatchBuilder::ANDNBMIOp},
{OPD(2, 0b11, 0xF6), 1, &OpDispatchBuilder::MULX},
{OPD(2, 0b00, 0xF7), 1, &OpDispatchBuilder::BEXTRBMIOp},
{OPD(2, 0b01, 0xF7), 1, &OpDispatchBuilder::BMI2Shift},
{OPD(2, 0b10, 0xF7), 1, &OpDispatchBuilder::BMI2Shift},

1
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h vendored
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@ -335,6 +335,7 @@ public:
// BMI2 Ops
void BMI2Shift(OpcodeArgs);
void MULX(OpcodeArgs);
void RORX(OpcodeArgs);
// ADX Ops

2
External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp vendored
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@ -397,7 +397,7 @@ void InitializeVEXTables() {
{OPD(2, 0b01, 0xF5), 1, X86InstInfo{"PEXT", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(2, 0b11, 0xF5), 1, X86InstInfo{"PDEP", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(2, 0b11, 0xF6), 1, X86InstInfo{"MULX", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(2, 0b11, 0xF6), 1, X86InstInfo{"MULX", TYPE_INST, FLAGS_MODRM | FLAGS_VEX_1ST_SRC, 0, nullptr}},
{OPD(2, 0b00, 0xF7), 1, X86InstInfo{"BEXTR", TYPE_INST, FLAGS_MODRM | FLAGS_VEX_2ND_SRC, 0, nullptr}},
{OPD(2, 0b01, 0xF7), 1, X86InstInfo{"SHLX", TYPE_INST, FLAGS_MODRM | FLAGS_VEX_2ND_SRC, 0, nullptr}},

36
unittests/ASM/VEX/mulx.asm Normal file
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@ -0,0 +1,36 @@
%ifdef CONFIG
{
"RegData": {
"RAX": "0xFFFFFFFFFFFFFFFE",
"RBX": "4",
"RCX": "4",
"RDX": "0xFFFFFFFE",
"RSI": "1",
"RDI": "1"
}
}
%endif
; Test low
mov rbx, 2
mov rdx, 2
mulx rax, rbx, rbx
; Test high
mov rcx, -1
mov rdx, -1
mulx rax, rdi, rcx
; 32-bit
; Test low
mov ecx, 2
mov edx, 2
mulx edx, ecx, ecx
; Test high
mov esi, -1
mov edx, -1
mulx edx, esi, esi
hlt