mirror of
https://github.com/FEX-Emu/FEX.git
synced 2025-02-25 01:01:20 +00:00
OpcodeDispatcher: Don't mask small add/sub carries
For the GPR result, the masking already happens as part of the bfi. So the only point of masking is for the flag calculation. But actually, every flag except carry will ignore the upper bits anyway. And the carry calculation actually WANTS the upper bit as a faster impl. Deletes a pile of code both in FEX and the output :-) ADC/SBC could probably get similar treatment later. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig
parent
5eed24a242
commit
5facb21d30
@ -322,7 +322,6 @@ void OpDispatchBuilder::CallbackReturnOp(OpcodeArgs) {
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}
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void OpDispatchBuilder::SecondaryALUOp(OpcodeArgs) {
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bool RequiresMask = false;
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FEXCore::IR::IROps IROp;
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#define OPD(group, prefix, Reg) (((group - FEXCore::X86Tables::TYPE_GROUP_1) << 6) | (prefix) << 3 | (Reg))
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switch (Op->OP) {
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@ -330,7 +329,6 @@ void OpDispatchBuilder::SecondaryALUOp(OpcodeArgs) {
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case OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x81), 0):
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case OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x83), 0):
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IROp = FEXCore::IR::IROps::OP_ADD;
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RequiresMask = true;
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break;
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case OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x80), 1):
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case OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x81), 1):
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@ -346,7 +344,6 @@ void OpDispatchBuilder::SecondaryALUOp(OpcodeArgs) {
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case OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x81), 5):
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case OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x83), 5):
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IROp = FEXCore::IR::IROps::OP_SUB;
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RequiresMask = true;
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break;
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case OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x80), 6):
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case OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x81), 6):
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@ -411,11 +408,6 @@ void OpDispatchBuilder::SecondaryALUOp(OpcodeArgs) {
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StoreResult(GPRClass, Op, Result, -1);
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}
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// Store result masks, but we need to
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if (RequiresMask && Size < 4) {
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Result = _Bfe(IR::SizeToOpSize(std::max<uint8_t>(4u, Size)), Size * 8, 0, Result);
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}
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// Flags set
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{
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switch (IROp) {
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@ -1452,10 +1444,6 @@ void OpDispatchBuilder::CMPOp(OpcodeArgs) {
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auto ALUOp = _Sub(Size == 8 ? OpSize::i64Bit : OpSize::i32Bit, Dest, Src);
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OrderedNode *Result = ALUOp;
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if (Size < 4) {
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Result = _Bfe(IR::SizeToOpSize(std::max<uint8_t>(4u, Size)), Size * 8, 0, ALUOp);
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}
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GenerateFlags_SUB(Op, Result, Dest, Src);
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flagsOp = SelectionFlag::CMP;
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@ -3427,10 +3415,6 @@ void OpDispatchBuilder::XADDOp(OpcodeArgs) {
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// Calculated value gets stored in dst (order is important if dst is same as src)
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StoreResult(GPRClass, Op, Result, -1);
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if (Size < 32) {
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Result = _Bfe(OpSize::i32Bit, Size, 0, Result);
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}
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GenerateFlags_ADD(Op, Result, Dest, Src);
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}
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else {
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@ -3440,10 +3424,6 @@ void OpDispatchBuilder::XADDOp(OpcodeArgs) {
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StoreResult(GPRClass, Op, Op->Src[0], Before, -1);
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Result = _Add(OpSize, Before, Src); // Seperate result just for flags
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if (Size < 32) {
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Result = _Bfe(OpSize::i32Bit, Size, 0, Result);
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}
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GenerateFlags_ADD(Op, Result, Before, Src);
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}
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}
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@ -3859,9 +3839,6 @@ void OpDispatchBuilder::INCOp(OpcodeArgs) {
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StoreResult(GPRClass, Op, Result, -1);
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}
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if (Size < 32) {
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Result = _Bfe(OpSize::i32Bit, Size, 0, Result);
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}
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GenerateFlags_ADD(Op, Result, Dest, OneConst, false);
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}
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@ -3892,9 +3869,6 @@ void OpDispatchBuilder::DECOp(OpcodeArgs) {
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if (!IsLocked) {
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StoreResult(GPRClass, Op, Result, -1);
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}
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if (Size < 32) {
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Result = _Bfe(OpSize::i32Bit, Size, 0, Result);
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}
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GenerateFlags_SUB(Op, Result, Dest, OneConst, false);
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}
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@ -4032,9 +4006,6 @@ void OpDispatchBuilder::CMPSOp(OpcodeArgs) {
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auto Src2 = _LoadMemAutoTSO(GPRClass, Size, Dest_RSI, Size);
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OrderedNode* Result = _Sub(Size == 8 ? OpSize::i64Bit : OpSize::i32Bit, Src2, Src1);
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if (Size < 4)
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Result = _Bfe(OpSize::i32Bit, Size * 8, 0, Result);
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GenerateFlags_SUB(Op, Result, Src2, Src1);
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auto DF = GetRFLAG(FEXCore::X86State::RFLAG_DF_LOC);
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@ -4094,9 +4065,6 @@ void OpDispatchBuilder::CMPSOp(OpcodeArgs) {
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auto Src2 = _LoadMem(GPRClass, Size, Dest_RSI, Size);
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OrderedNode* Result = _Sub(Size == 8 ? OpSize::i64Bit : OpSize::i32Bit, Src2, Src1);
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if (Size < 4)
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Result = _Bfe(OpSize::i32Bit, Size * 8, 0, Result);
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GenerateFlags_SUB(Op, Result, Src2, Src1);
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// Calculate flags early.
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@ -4259,8 +4227,6 @@ void OpDispatchBuilder::SCASOp(OpcodeArgs) {
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auto Src2 = _LoadMemAutoTSO(GPRClass, Size, Dest_RDI, Size);
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OrderedNode* Result = _Sub(Size == 8 ? OpSize::i64Bit : OpSize::i32Bit, Src1, Src2);
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if (Size < 4)
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Result = _Bfe(OpSize::i32Bit, Size * 8, 0, Result);
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GenerateFlags_SUB(Op, Result, Src1, Src2);
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auto SizeConst = _Constant(Size);
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@ -4322,9 +4288,6 @@ void OpDispatchBuilder::SCASOp(OpcodeArgs) {
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auto Src2 = _LoadMemAutoTSO(GPRClass, Size, Dest_RDI, Size);
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OrderedNode* Result = _Sub(Size == 8 ? OpSize::i64Bit : OpSize::i32Bit, Src1, Src2);
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if (Size < 4)
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Result = _Bfe(OpSize::i32Bit, Size * 8, 0, Result);
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GenerateFlags_SUB(Op, Result, Src1, Src2);
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// Calculate flags early.
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@ -4435,9 +4398,6 @@ void OpDispatchBuilder::NEGOp(OpcodeArgs) {
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StoreResult(GPRClass, Op, Result, -1);
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}
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if (Size < 4)
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Result = _Bfe(OpSize::i32Bit, Size * 8, 0, Result);
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GenerateFlags_SUB(Op, Result, ZeroConst, Dest);
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}
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@ -4672,13 +4632,7 @@ void OpDispatchBuilder::CMPXCHGOp(OpcodeArgs) {
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StoreResult(GPRClass, Op, DestResult, -1);
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}
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const auto Size = GetDstBitSize(Op);
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OrderedNode *Result = _Sub(IR::SizeToOpSize(GPRSize), Src3Lower, CASResult);
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if (Size < 32) {
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Result = _Bfe(OpSize::i64Bit, Size, 0, Result);
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}
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GenerateFlags_SUB(Op, Result, Src3Lower, CASResult);
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}
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else {
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@ -4721,10 +4675,6 @@ void OpDispatchBuilder::CMPXCHGOp(OpcodeArgs) {
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const auto Size = GetDstBitSize(Op);
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OrderedNode *Result = _Sub(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Src3Lower, CASResult);
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if (Size < 32) {
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Result = _Bfe(OpSize::i32Bit, Size, 0, Result);
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}
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GenerateFlags_SUB(Op, Result, Src3Lower, CASResult);
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}
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}
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@ -5476,7 +5426,7 @@ void OpDispatchBuilder::MOVGPRNTOp(OpcodeArgs) {
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StoreResult(GPRClass, Op, Src, 1, MemoryAccessType::ACCESS_STREAM);
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}
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void OpDispatchBuilder::ALUOpImpl(OpcodeArgs, FEXCore::IR::IROps ALUIROp, FEXCore::IR::IROps AtomicFetchOp, bool RequiresMask) {
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void OpDispatchBuilder::ALUOpImpl(OpcodeArgs, FEXCore::IR::IROps ALUIROp, FEXCore::IR::IROps AtomicFetchOp) {
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auto Size = GetDstSize(Op);
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const auto OpSize = Size == 8 ? OpSize::i64Bit : OpSize::i32Bit;
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@ -5527,10 +5477,6 @@ void OpDispatchBuilder::ALUOpImpl(OpcodeArgs, FEXCore::IR::IROps ALUIROp, FEXCor
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StoreResult(GPRClass, Op, Result, -1);
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}
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if (RequiresMask && Size < 4) {
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Result = _Bfe(OpSize::i32Bit, Size * 8, 0, Result);
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}
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// Flags set
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{
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switch (ALUIROp) {
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@ -5551,9 +5497,9 @@ void OpDispatchBuilder::ALUOpImpl(OpcodeArgs, FEXCore::IR::IROps ALUIROp, FEXCor
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}
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}
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template<FEXCore::IR::IROps ALUIROp, FEXCore::IR::IROps AtomicFetchOp, bool RequiresMask>
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template<FEXCore::IR::IROps ALUIROp, FEXCore::IR::IROps AtomicFetchOp>
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void OpDispatchBuilder::ALUOp(OpcodeArgs) {
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ALUOpImpl(Op, ALUIROp, AtomicFetchOp, RequiresMask);
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ALUOpImpl(Op, ALUIROp, AtomicFetchOp);
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}
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void OpDispatchBuilder::INTOp(OpcodeArgs) {
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@ -6342,19 +6288,19 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
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void InstallOpcodeHandlers(Context::OperatingMode Mode) {
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constexpr std::tuple<uint8_t, uint8_t, X86Tables::OpDispatchPtr> BaseOpTable[] = {
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// Instructions
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{0x00, 6, &OpDispatchBuilder::ALUOp<FEXCore::IR::IROps::OP_ADD, FEXCore::IR::IROps::OP_ATOMICFETCHADD, true>},
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{0x00, 6, &OpDispatchBuilder::ALUOp<FEXCore::IR::IROps::OP_ADD, FEXCore::IR::IROps::OP_ATOMICFETCHADD>},
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{0x08, 6, &OpDispatchBuilder::ALUOp<FEXCore::IR::IROps::OP_OR, FEXCore::IR::IROps::OP_ATOMICFETCHOR, false>},
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{0x08, 6, &OpDispatchBuilder::ALUOp<FEXCore::IR::IROps::OP_OR, FEXCore::IR::IROps::OP_ATOMICFETCHOR>},
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{0x10, 6, &OpDispatchBuilder::ADCOp<0>},
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{0x18, 6, &OpDispatchBuilder::SBBOp<0, true>},
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{0x20, 6, &OpDispatchBuilder::ALUOp<FEXCore::IR::IROps::OP_AND, FEXCore::IR::IROps::OP_ATOMICFETCHAND, false>},
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{0x20, 6, &OpDispatchBuilder::ALUOp<FEXCore::IR::IROps::OP_AND, FEXCore::IR::IROps::OP_ATOMICFETCHAND>},
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{0x28, 6, &OpDispatchBuilder::ALUOp<FEXCore::IR::IROps::OP_SUB, FEXCore::IR::IROps::OP_ATOMICFETCHSUB, true>},
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{0x28, 6, &OpDispatchBuilder::ALUOp<FEXCore::IR::IROps::OP_SUB, FEXCore::IR::IROps::OP_ATOMICFETCHSUB>},
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{0x30, 6, &OpDispatchBuilder::ALUOp<FEXCore::IR::IROps::OP_XOR, FEXCore::IR::IROps::OP_ATOMICFETCHXOR, false>},
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{0x30, 6, &OpDispatchBuilder::ALUOp<FEXCore::IR::IROps::OP_XOR, FEXCore::IR::IROps::OP_ATOMICFETCHXOR>},
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{0x38, 6, &OpDispatchBuilder::CMPOp<0>},
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{0x50, 8, &OpDispatchBuilder::PUSHREGOp},
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@ -187,7 +187,7 @@ public:
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void MOVGPRNTOp(OpcodeArgs);
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void MOVVectorOp(OpcodeArgs);
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void MOVVectorNTOp(OpcodeArgs);
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template<FEXCore::IR::IROps ALUIROp, FEXCore::IR::IROps AtomicFetchOp, bool RequiresMask>
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template<FEXCore::IR::IROps ALUIROp, FEXCore::IR::IROps AtomicFetchOp>
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void ALUOp(OpcodeArgs);
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void INTOp(OpcodeArgs);
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void SyscallOp(OpcodeArgs);
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@ -881,7 +881,7 @@ private:
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// Used during new op bringup
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bool ShouldDump{false};
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void ALUOpImpl(OpcodeArgs, FEXCore::IR::IROps ALUIROp, FEXCore::IR::IROps AtomicFetchOp, bool RequiresMask);
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void ALUOpImpl(OpcodeArgs, FEXCore::IR::IROps ALUIROp, FEXCore::IR::IROps AtomicFetchOp);
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// Opcode helpers for generalizing behavior across VEX and non-VEX variants.
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@ -556,8 +556,6 @@ void OpDispatchBuilder::CalculateFlags_SBB(uint8_t SrcSize, OrderedNode *Res, Or
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}
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void OpDispatchBuilder::CalculateFlags_SUB(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF) {
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auto Zero = _Constant(0);
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auto One = _Constant(1);
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auto OpSize = SrcSize == 8 ? OpSize::i64Bit : OpSize::i32Bit;
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CalculateAF(OpSize, Res, Src1, Src2);
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@ -576,10 +574,9 @@ void OpDispatchBuilder::CalculateFlags_SUB(uint8_t SrcSize, OrderedNode *Res, Or
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// CF
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if (UpdateCF) {
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auto SelectOp = _Select(FEXCore::IR::COND_ULT,
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Src1, Src2, One, Zero);
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SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(SelectOp);
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// Grab carry bit from unmasked output.
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auto Bfe = _Bfe(OpSize::i32Bit, 1, SrcSize * 8, Res);
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SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(Bfe);
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}
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CalculateOF(SrcSize, Res, Src1, Src2, true);
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@ -591,8 +588,6 @@ void OpDispatchBuilder::CalculateFlags_SUB(uint8_t SrcSize, OrderedNode *Res, Or
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}
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void OpDispatchBuilder::CalculateFlags_ADD(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF) {
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auto Zero = _Constant(0);
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auto One = _Constant(1);
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auto OpSize = SrcSize == 8 ? OpSize::i64Bit : OpSize::i32Bit;
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CalculateAF(OpSize, Res, Src1, Src2);
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@ -610,9 +605,9 @@ void OpDispatchBuilder::CalculateFlags_ADD(uint8_t SrcSize, OrderedNode *Res, Or
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// CF
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if (UpdateCF) {
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auto SelectOp = _Select(FEXCore::IR::COND_ULT, Res, Src2, One, Zero);
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SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(SelectOp);
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// Grab carry bit from unmasked output
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auto Bfe = _Bfe(OpSize::i32Bit, 1, SrcSize * 8, Res);
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SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(Bfe);
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}
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CalculateOF(SrcSize, Res, Src1, Src2, false);
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