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Update InstCountCI

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This commit is contained in:
Billy Laws 2024-05-06 17:36:55 +00:00
parent bd24364c1b
commit 61cd835754
15 changed files with 44 additions and 44 deletions
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4
unittests/InstructionCountCI/Crypto/H0F3A.json
View File

@ -55,7 +55,7 @@
"0x66 0x0f 0x3a 0xdf"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2160]",
"ldr q2, [x28, #2176]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
@ -68,7 +68,7 @@
"0x66 0x0f 0x3a 0xdf"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2160]",
"ldr q2, [x28, #2176]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",

2
unittests/InstructionCountCI/FlagM/Secondary.json
View File

@ -1612,7 +1612,7 @@
"Comment": "0x0f 0xd7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #2272]",
"ldr d3, [x28, #2288]",
"cmlt v2.16b, v2.16b, #0",
"and v2.16b, v2.16b, v3.16b",
"addp v2.16b, v2.16b, v2.16b",

2
unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
View File

@ -38,7 +38,7 @@
"ExpectedInstructionCount": 7,
"Comment": "0x66 0x0f 0xd7",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2272]",
"ldr q2, [x28, #2288]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",

2
unittests/InstructionCountCI/FlagM/VEX_map1.json
View File

@ -72,7 +72,7 @@
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2272]",
"ldr q2, [x28, #2288]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",

16
unittests/InstructionCountCI/FlagM/x87.json
View File

@ -4516,7 +4516,7 @@
"orr w21, w22, w21",
"strb w21, [x28, #1026]",
"strb w20, [x28, #747]",
"ldr q2, [x28, #2304]",
"ldr q2, [x28, #2320]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #768]"
]
@ -4536,7 +4536,7 @@
"orr w21, w22, w21",
"strb w21, [x28, #1026]",
"strb w20, [x28, #747]",
"ldr q2, [x28, #2320]",
"ldr q2, [x28, #2336]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #768]"
]
@ -4556,7 +4556,7 @@
"orr w21, w22, w21",
"strb w21, [x28, #1026]",
"strb w20, [x28, #747]",
"ldr q2, [x28, #2336]",
"ldr q2, [x28, #2352]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #768]"
]
@ -4576,7 +4576,7 @@
"orr w21, w22, w21",
"strb w21, [x28, #1026]",
"strb w20, [x28, #747]",
"ldr q2, [x28, #2352]",
"ldr q2, [x28, #2368]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #768]"
]
@ -4596,7 +4596,7 @@
"orr w21, w22, w21",
"strb w21, [x28, #1026]",
"strb w20, [x28, #747]",
"ldr q2, [x28, #2368]",
"ldr q2, [x28, #2384]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #768]"
]
@ -4616,7 +4616,7 @@
"orr w21, w22, w21",
"strb w21, [x28, #1026]",
"strb w20, [x28, #747]",
"ldr q2, [x28, #2384]",
"ldr q2, [x28, #2400]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #768]"
]
@ -4780,7 +4780,7 @@
"eor v2.16b, v2.16b, v2.16b",
"mov v2.d[0], x0",
"mov v2.h[4], w1",
"ldr q3, [x28, #2304]",
"ldr q3, [x28, #2320]",
"mov w21, #0x0",
"strb w21, [x28, #746]",
"add x0, x28, x20, lsl #4",
@ -5062,7 +5062,7 @@
"ldr q2, [x0, #768]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #768]",
"ldr q4, [x28, #2304]",
"ldr q4, [x28, #2320]",
"mrs x0, nzcv",
"str w0, [x28, #728]",
"stp x4, x5, [x28, #8]",

2
unittests/InstructionCountCI/H0F38.json
View File

@ -624,7 +624,7 @@
"0x66 0x0f 0x38 0x41"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2048]",
"ldr q2, [x28, #2064]",
"zip1 v3.8h, v2.8h, v17.8h",
"zip2 v2.8h, v2.8h, v17.8h",
"umin v2.4s, v3.4s, v2.4s",

12
unittests/InstructionCountCI/H0F3A.json
View File

@ -315,7 +315,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2176]",
"ldr q2, [x28, #2192]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@ -325,7 +325,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2192]",
"ldr q2, [x28, #2208]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@ -344,7 +344,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2208]",
"ldr q2, [x28, #2224]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@ -364,7 +364,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2224]",
"ldr q2, [x28, #2240]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@ -383,7 +383,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2240]",
"ldr q2, [x28, #2256]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@ -393,7 +393,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2256]",
"ldr q2, [x28, #2272]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},

8
unittests/InstructionCountCI/PrimaryGroup.json
View File

@ -2856,7 +2856,7 @@
"mov x0, x6",
"mov x1, x20",
"mov x2, x7",
"ldr x3, [x28, #2432]",
"ldr x3, [x28, #2448]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
@ -2867,7 +2867,7 @@
"mov x0, x6",
"mov x1, x20",
"mov x2, x7",
"ldr x3, [x28, #2448]",
"ldr x3, [x28, #2464]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
@ -2928,7 +2928,7 @@
"mov x0, x6",
"mov x1, x20",
"mov x2, x7",
"ldr x3, [x28, #2440]",
"ldr x3, [x28, #2456]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
@ -2941,7 +2941,7 @@
"mov x0, x6",
"mov x1, x20",
"mov x2, x7",
"ldr x3, [x28, #2456]",
"ldr x3, [x28, #2472]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",

6
unittests/InstructionCountCI/Secondary.json
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@ -646,7 +646,7 @@
"Comment": "0x0f 0x50",
"ExpectedArm64ASM": [
"ushr v2.4s, v16.4s, #31",
"ldr q3, [x28, #2144]",
"ldr q3, [x28, #2160]",
"ushl v2.4s, v2.4s, v3.4s",
"addv s2, v2.4s",
"mov w4, v2.s[0]"
@ -657,7 +657,7 @@
"Comment": "0x0f 0x50",
"ExpectedArm64ASM": [
"ushr v2.4s, v16.4s, #31",
"ldr q3, [x28, #2144]",
"ldr q3, [x28, #2160]",
"ushl v2.4s, v2.4s, v3.4s",
"addv s2, v2.4s",
"mov w4, v2.s[0]"
@ -3425,7 +3425,7 @@
"Comment": "0x0f 0xd7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #2272]",
"ldr d3, [x28, #2288]",
"cmlt v2.16b, v2.16b, #0",
"and v2.16b, v2.16b, v3.16b",
"addp v2.16b, v2.16b, v2.16b",

4
unittests/InstructionCountCI/Secondary_OpSize.json
View File

@ -1014,7 +1014,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0x66 0x0f 0xd0",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2112]",
"ldr q2, [x28, #2128]",
"eor v2.16b, v17.16b, v2.16b",
"fadd v16.2d, v16.2d, v2.2d"
]
@ -1070,7 +1070,7 @@
"ExpectedInstructionCount": 7,
"Comment": "0x66 0x0f 0xd7",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2272]",
"ldr q2, [x28, #2288]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",

2
unittests/InstructionCountCI/Secondary_REPNE.json
View File

@ -452,7 +452,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0xf2 0x0f 0xd0",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2080]",
"ldr q2, [x28, #2096]",
"eor v2.16b, v17.16b, v2.16b",
"fadd v16.4s, v16.4s, v2.4s"
]

6
unittests/InstructionCountCI/VEX_map1.json
View File

@ -4338,7 +4338,7 @@
"Map 1 0b01 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2112]",
"ldr q2, [x28, #2128]",
"eor v2.16b, v18.16b, v2.16b",
"fadd v16.2d, v17.2d, v2.2d"
]
@ -4361,7 +4361,7 @@
"Map 1 0b11 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2080]",
"ldr q2, [x28, #2096]",
"eor v2.16b, v18.16b, v2.16b",
"fadd v16.4s, v17.4s, v2.4s"
]
@ -4498,7 +4498,7 @@
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2272]",
"ldr q2, [x28, #2288]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",

2
unittests/InstructionCountCI/VEX_map2.json
View File

@ -1575,7 +1575,7 @@
"Map 2 0b01 0x41 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2048]",
"ldr q2, [x28, #2064]",
"zip1 v3.8h, v2.8h, v17.8h",
"zip2 v2.8h, v2.8h, v17.8h",
"umin v2.4s, v3.4s, v2.4s",

4
unittests/InstructionCountCI/VEX_map3.json
View File

@ -4799,7 +4799,7 @@
"Map 3 0b01 0xdf 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2160]",
"ldr q2, [x28, #2176]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
@ -4812,7 +4812,7 @@
"Map 3 0b01 0xdf 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2160]",
"ldr q2, [x28, #2176]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",

16
unittests/InstructionCountCI/x87.json
View File

@ -4515,7 +4515,7 @@
"orr w21, w22, w21",
"strb w21, [x28, #1026]",
"strb w20, [x28, #747]",
"ldr q2, [x28, #2304]",
"ldr q2, [x28, #2320]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #768]"
]
@ -4535,7 +4535,7 @@
"orr w21, w22, w21",
"strb w21, [x28, #1026]",
"strb w20, [x28, #747]",
"ldr q2, [x28, #2320]",
"ldr q2, [x28, #2336]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #768]"
]
@ -4555,7 +4555,7 @@
"orr w21, w22, w21",
"strb w21, [x28, #1026]",
"strb w20, [x28, #747]",
"ldr q2, [x28, #2336]",
"ldr q2, [x28, #2352]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #768]"
]
@ -4575,7 +4575,7 @@
"orr w21, w22, w21",
"strb w21, [x28, #1026]",
"strb w20, [x28, #747]",
"ldr q2, [x28, #2352]",
"ldr q2, [x28, #2368]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #768]"
]
@ -4595,7 +4595,7 @@
"orr w21, w22, w21",
"strb w21, [x28, #1026]",
"strb w20, [x28, #747]",
"ldr q2, [x28, #2368]",
"ldr q2, [x28, #2384]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #768]"
]
@ -4615,7 +4615,7 @@
"orr w21, w22, w21",
"strb w21, [x28, #1026]",
"strb w20, [x28, #747]",
"ldr q2, [x28, #2384]",
"ldr q2, [x28, #2400]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #768]"
]
@ -4779,7 +4779,7 @@
"eor v2.16b, v2.16b, v2.16b",
"mov v2.d[0], x0",
"mov v2.h[4], w1",
"ldr q3, [x28, #2304]",
"ldr q3, [x28, #2320]",
"mov w21, #0x0",
"strb w21, [x28, #746]",
"add x0, x28, x20, lsl #4",
@ -5061,7 +5061,7 @@
"ldr q2, [x0, #768]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #768]",
"ldr q4, [x28, #2304]",
"ldr q4, [x28, #2320]",
"mrs x0, nzcv",
"str w0, [x28, #728]",
"stp x4, x5, [x28, #8]",