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OpcodeDispatcher: Handle VPERMPS

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With the VPERMD work in place, this is trivial to support.
This commit is contained in:
Lioncache 2023-02-20 16:48:25 -05:00
parent b2c333c383
commit 65b9dcd20b
3 changed files with 53 additions and 1 deletions
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1
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp vendored
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@ -5972,6 +5972,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
{OPD(2, 0b01, 0x0A), 1, &OpDispatchBuilder::VPSIGN<4>},
{OPD(2, 0b01, 0x0B), 1, &OpDispatchBuilder::VPMULHRSWOp},
{OPD(2, 0b01, 0x16), 1, &OpDispatchBuilder::VPERMDOp},
{OPD(2, 0b01, 0x17), 1, &OpDispatchBuilder::PTestOp},
{OPD(2, 0b01, 0x18), 1, &OpDispatchBuilder::VBROADCASTOp<4>},
{OPD(2, 0b01, 0x19), 1, &OpDispatchBuilder::VBROADCASTOp<8>},

2
External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp vendored
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@ -278,7 +278,7 @@ void InitializeVEXTables() {
{OPD(2, 0b01, 0x0F), 1, X86InstInfo{"VTESTPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(2, 0b01, 0x13), 1, X86InstInfo{"VCVTPH2PS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(2, 0b01, 0x16), 1, X86InstInfo{"VPERMPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(2, 0b01, 0x16), 1, X86InstInfo{"VPERMPS", TYPE_INST, GenFlagsSameSize(SIZE_256BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(2, 0b01, 0x17), 1, X86InstInfo{"VPTEST", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(2, 0b01, 0x18), 1, X86InstInfo{"VBROADCASTSS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},

51
unittests/ASM/VEX/vpermps.asm Normal file
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@ -0,0 +1,51 @@
%ifdef CONFIG
{
"HostFeatures": ["AVX"],
"RegData": {
"XMM0": ["0x0000000600000007", "0x0000000400000005", "0x0000000200000003", "0x0000000000000001"],
"XMM1": ["0x0000000500000005", "0x0000000500000005", "0x0000000500000005", "0x0000000500000005"],
"XMM2": ["0xFFFFFFF0FFFFFFF1", "0xFFFFFFF2FFFFFFF3", "0xFFFFFFF4FFFFFFF5", "0xFFFFFFF6FFFFFFF7"],
"XMM3": ["0x8888888899999999", "0xAAAAAAAABBBBBBBB", "0xCCCCCCCCDDDDDDDD", "0xEEEEEEEEFFFFFFFF"],
"XMM4": ["0xBBBBBBBBBBBBBBBB", "0xBBBBBBBBBBBBBBBB", "0xBBBBBBBBBBBBBBBB", "0xBBBBBBBBBBBBBBBB"],
"XMM5": ["0xEEEEEEEEFFFFFFFF", "0xCCCCCCCCDDDDDDDD", "0xAAAAAAAABBBBBBBB", "0x8888888899999999"]
}
}
%endif
lea rdx, [rel .data]
vmovapd ymm0, [rel .invert]
vmovapd ymm1, [rel .select_elem_5]
vmovapd ymm2, [rel .reverse_quadwords]
vpermps ymm3, ymm0, [rel .data]
vpermps ymm4, ymm1, [rel .data]
vpermps ymm5, ymm2, [rel .data]
hlt
align 32
.data:
dq 0xFFFFFFFFEEEEEEEE
dq 0xDDDDDDDDCCCCCCCC
dq 0xBBBBBBBBAAAAAAAA
dq 0x9999999988888888
.invert:
dq 0x0000000600000007
dq 0x0000000400000005
dq 0x0000000200000003
dq 0x0000000000000001
.select_elem_5:
dq 0x0000000500000005
dq 0x0000000500000005
dq 0x0000000500000005
dq 0x0000000500000005
; Upper bits filled with junk. Should have no impact on operation
.reverse_quadwords:
dq 0xFFFFFFF0FFFFFFF1
dq 0xFFFFFFF2FFFFFFF3
dq 0xFFFFFFF4FFFFFFF5
dq 0xFFFFFFF6FFFFFFF7