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InstCountCI: add flag optimizations tests
Now that lots of instructions have optimal flag calculation in isolation, we need to look at sequences of instructions together. These cases test various interesting cases where concatenating the optimal instruction translations gives something terrible for the whole block. These cases exercise the new flag optimization pass. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig
parent
175a57dd27
commit
69466dce92
267
unittests/InstructionCountCI/FlagM/FlagOpts.json
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267
unittests/InstructionCountCI/FlagM/FlagOpts.json
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{
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"Features": {
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"EnabledHostFeatures": [
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"FLAGM",
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"FLAGM2"
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],
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"DisabledHostFeatures": [
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"SVE128",
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"SVE256"
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]
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},
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"Instructions": {
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"Chained add": {
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"ExpectedInstructionCount": 10,
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"x86Insts": [
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"add rax, rbx",
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"adc rcx, rcx"
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],
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"ExpectedArm64ASM": [
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"mov x20, x4",
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"add x4, x20, x7",
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"cmn x20, x7",
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"mov x20, x5",
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"cset w21, hs",
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"add x21, x20, x21",
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"add x5, x20, x21",
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"mov w27, #0x0",
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"mov x26, x5",
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"adcs xzr, x20, x20"
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]
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},
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"Chained sub": {
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"ExpectedInstructionCount": 13,
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"x86Insts": [
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"sub rax, rbx",
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"sbb rcx, rdx"
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],
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"ExpectedArm64ASM": [
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"mov x20, x4",
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"sub x4, x20, x7",
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"cmp x20, x7",
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"cfinv",
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"cset w20, hs",
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"add x20, x6, x20",
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"mov x21, x5",
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"sub x5, x21, x20",
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"eor x27, x21, x6",
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"mov x26, x5",
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"cfinv",
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"sbcs xzr, x21, x6",
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"cfinv"
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]
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},
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"Inverted add": {
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"ExpectedInstructionCount": 11,
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"x86Insts": [
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"add rax, rbx",
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"adc rcx, rdx",
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"cmc"
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],
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"ExpectedArm64ASM": [
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"mov x20, x4",
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"add x4, x20, x7",
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"cmn x20, x7",
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"cset w20, hs",
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"add x20, x6, x20",
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"mov x21, x5",
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"add x5, x21, x20",
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"eor x27, x21, x6",
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"mov x26, x5",
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"adcs xzr, x21, x6",
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"cfinv"
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]
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},
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"Inverted sub": {
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"ExpectedInstructionCount": 14,
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"x86Insts": [
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"sub rax, rbx",
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"sbb rcx, rcx",
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"cmc"
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],
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"ExpectedArm64ASM": [
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"mov x20, x4",
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"sub x4, x20, x7",
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"cmp x20, x7",
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"cfinv",
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"mov x20, x5",
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"cset w21, hs",
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"add x21, x20, x21",
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"sub x5, x20, x21",
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"mov w27, #0x0",
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"mov x26, x5",
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"cfinv",
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"sbcs xzr, x20, x20",
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"cfinv",
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"cfinv"
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]
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},
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"INC consumed": {
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"ExpectedInstructionCount": 10,
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"x86Insts": [
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"add rax, rbx",
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"inc rax"
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],
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"ExpectedArm64ASM": [
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"mov x20, x4",
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"add x21, x20, x7",
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"mov x4, x21",
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"add x4, x21, #0x1 (1)",
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"cmn x20, x7",
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"mov x27, x21",
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"mov x26, x4",
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"cset w20, hs",
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"cmn x21, #0x1 (1)",
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"rmif x20, #63, #nzCv"
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]
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},
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"INC dead": {
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"ExpectedInstructionCount": 3,
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"x86Insts": [
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"add rax, rbx",
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"inc rax",
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"test rax, rdx"
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],
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"ExpectedArm64ASM": [
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"add x4, x4, x7",
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"add x4, x4, #0x1 (1)",
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"ands x26, x4, x6"
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]
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},
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"DEC consumed": {
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"ExpectedInstructionCount": 11,
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"x86Insts": [
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"sub rax, rbx",
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"dec rax"
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],
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"ExpectedArm64ASM": [
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"mov x20, x4",
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"sub x21, x20, x7",
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"mov x4, x21",
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"sub x4, x21, #0x1 (1)",
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"cmp x20, x7",
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"cfinv",
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"mov x27, x21",
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"mov x26, x4",
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"cset w20, hs",
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"cmp x21, #0x1 (1)",
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"rmif x20, #63, #nzCv"
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]
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},
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"DEC dead": {
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"ExpectedInstructionCount": 3,
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"x86Insts": [
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"sub rax, rbx",
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"dec rax",
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"test rax, rcx"
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],
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"ExpectedArm64ASM": [
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"sub x4, x4, x7",
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"sub x4, x4, #0x1 (1)",
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"ands x26, x4, x5"
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]
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},
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"Variable shift dead": {
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"ExpectedInstructionCount": 2,
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"x86Insts": [
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"sar rax, cl",
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"test rax, rdx"
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],
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"ExpectedArm64ASM": [
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"asr x4, x4, x5",
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"ands x26, x4, x6"
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]
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},
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"Variable rotate-through-carry dead": {
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"ExpectedInstructionCount": 16,
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"x86Insts": [
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"rcr rax, cl",
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"test rax, rdx"
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],
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"ExpectedArm64ASM": [
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"mov x20, x4",
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"lsr x21, x20, x5",
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"cset w22, hs",
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"and x23, x5, #0x3f",
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"cbz x23, #+0x2c",
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"neg x24, x23",
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"lsl x25, x20, x24",
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"orr x21, x21, x25, lsl #1",
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"sub x23, x23, #0x1 (1)",
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"lsr x20, x20, x23",
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"rmif x20, #63, #nzCv",
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"lsl x20, x22, x24",
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"orr x4, x21, x20",
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"eor x20, x4, x4, lsr #1",
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"rmif x20, #62, #nzcV",
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"ands x26, x4, x6"
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]
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},
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"Partial NZCV select (cmp)": {
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"ExpectedInstructionCount": 5,
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"x86Insts": [
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"cmp rax, rbx",
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"setz cl",
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"test cl, cl"
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],
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"ExpectedArm64ASM": [
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"cmp x4, x7",
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"cset x20, eq",
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"bfxil x5, x20, #0, #8",
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"cmn wzr, w5, lsl #24",
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"mov x26, x5"
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]
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},
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"Partial NZCV select (add)": {
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"ExpectedInstructionCount": 7,
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"x86Insts": [
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"add rax, rbx",
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"setz cl",
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"test cl, cl"
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],
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"ExpectedArm64ASM": [
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"mov x20, x4",
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"add x4, x20, x7",
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"cmn x20, x7",
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"cset x20, eq",
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"bfxil x5, x20, #0, #8",
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"cmn wzr, w5, lsl #24",
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"mov x26, x5"
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]
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},
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"AND use only ZF": {
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"ExpectedInstructionCount": 5,
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"x86Insts": [
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"and eax, ebx",
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"setz cl",
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"test cl, cl"
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],
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"ExpectedArm64ASM": [
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"ands w4, w4, w7",
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"cset x20, eq",
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"bfxil x5, x20, #0, #8",
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"mov x26, x5",
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"cmn wzr, w26, lsl #24"
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]
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},
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"AND use only PF": {
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"ExpectedInstructionCount": 9,
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"x86Insts": [
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"and eax, ebx",
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"setp cl",
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"test cl, cl"
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],
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"ExpectedArm64ASM": [
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"and w4, w4, w7",
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"fmov s2, w4",
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"cnt v2.16b, v2.16b",
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"umov w20, v2.b[0]",
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"mvn w20, w20",
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"and x20, x20, #0x1",
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"bfxil x5, x20, #0, #8",
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"mov x26, x5",
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"cmn wzr, w26, lsl #24"
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]
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}
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}
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}
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