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Implements VBSL on AArch64

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This isn't quite optimal without RA constraints
This commit is contained in:
Ryan Houdek 2021-01-26 03:01:48 -08:00
parent 4d98c890e7
commit 6bca290611
1 changed files with 11 additions and 1 deletions
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12
External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp vendored
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@ -909,7 +909,17 @@ DEF_OP(VZip2) {
}
DEF_OP(VBSL) {
LogMan::Msg::A("Unimplemented");
auto Op = IROp->C<IR::IROp_VBSL>();
if (IROp->Size == 16) {
mov(VTMP1.V16B(), GetSrc(Op->Header.Args[0].ID()).V16B());
bsl(VTMP1.V16B(), GetSrc(Op->Header.Args[1].ID()).V16B(), GetSrc(Op->Header.Args[2].ID()).V16B());
mov(GetDst(Node).V16B(), VTMP1.V16B());
}
else {
mov(VTMP1.V8B(), GetSrc(Op->Header.Args[0].ID()).V8B());
bsl(VTMP1.V8B(), GetSrc(Op->Header.Args[1].ID()).V8B(), GetSrc(Op->Header.Args[2].ID()).V8B());
mov(GetDst(Node).V8B(), VTMP1.V8B());
}
}
DEF_OP(VCMPEQ) {