FEX-Emu/FEX
1
0
Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2025-01-09 07:10:39 +00:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity

OpcodeDispatcher: Handle VSHUFPD

Browse Source
This commit is contained in:
Lioncache 2023-02-14 15:42:06 -05:00
parent c5d799df8c
commit 6d87154ac8
5 changed files with 62 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp vendored
View File

@ -5960,6 +5960,8 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
{OPD(1, 0b01, 0xC5), 1, &OpDispatchBuilder::PExtrOp<2>},
{OPD(1, 0b01, 0xC6), 1, &OpDispatchBuilder::VSHUFOp<8>},
{OPD(1, 0b01, 0xD0), 1, &OpDispatchBuilder::VADDSUBPOp<8>},
{OPD(1, 0b11, 0xD0), 1, &OpDispatchBuilder::VADDSUBPOp<4>},

3
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h vendored
View File

@ -525,6 +525,9 @@ public:
template <size_t ElementSize>
void VPSRLIOp(OpcodeArgs);
template <size_t ElementSize>
void VSHUFOp(OpcodeArgs);
void VZEROOp(OpcodeArgs);
// X87 Ops

9
External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp vendored
View File

@ -1162,12 +1162,19 @@ void OpDispatchBuilder::SHUFOp(OpcodeArgs) {
OrderedNode *Result = SHUFOpImpl(Op, ElementSize, Op->Dest, Op->Src[0], Op->Src[1]);
StoreResult(FPRClass, Op, Result, -1);
}
template
void OpDispatchBuilder::SHUFOp<4>(OpcodeArgs);
template
void OpDispatchBuilder::SHUFOp<8>(OpcodeArgs);
template <size_t ElementSize>
void OpDispatchBuilder::VSHUFOp(OpcodeArgs) {
OrderedNode *Result = SHUFOpImpl(Op, ElementSize, Op->Src[0], Op->Src[1], Op->Src[2]);
StoreResult(FPRClass, Op, Result, -1);
}
template
void OpDispatchBuilder::VSHUFOp<8>(OpcodeArgs);
void OpDispatchBuilder::VANDNOp(OpcodeArgs) {
const auto Size = GetSrcSize(Op);
const auto Is128Bit = Size == Core::CPUState::XMM_SSE_REG_SIZE;

2
External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp vendored
View File

@ -106,7 +106,7 @@ void InitializeVEXTables() {
{OPD(1, 0b01, 0xC5), 1, X86InstInfo{"VPEXTRW", TYPE_INST, GenFlagsSizes(SIZE_32BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_REG_ONLY | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(1, 0b00, 0xC6), 1, X86InstInfo{"VSHUFPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b01, 0xC6), 1, X86InstInfo{"VSHUFPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b01, 0xC6), 1, X86InstInfo{"VSHUFPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}},
// The above ops are defined from `Table A-17. VEX Opcode Map 1, Low Nibble = [0h:7h]` of AMD Architecture programmer's manual Volume 3
// This table doesn't state which VEX.pp is for which instruction

48
unittests/ASM/VEX/vshufpd.asm Normal file
View File

@ -0,0 +1,48 @@
%ifdef CONFIG
{
"HostFeatures": ["AVX"],
"RegData": {
"XMM2": ["0x4142434445464748", "0x6162636465666768", "0x0000000000000000", "0x0000000000000000"],
"XMM3": ["0x5152535455565758", "0x6162636465666768", "0x0000000000000000", "0x0000000000000000"],
"XMM4": ["0x4142434445464748", "0x7172737475767778", "0x0000000000000000", "0x0000000000000000"],
"XMM5": ["0x5152535455565758", "0x7172737475767778", "0x0000000000000000", "0x0000000000000000"],
"XMM6": ["0x4142434445464748", "0x6162636465666768", "0x3132333435363738", "0x8182838485868788"],
"XMM7": ["0x4142434445464748", "0x6162636465666768", "0x3132333435363738", "0x9192939495969798"],
"XMM8": ["0x5152535455565758", "0x6162636465666768", "0x2122232425262728", "0x8182838485868788"],
"XMM9": ["0x4142434445464748", "0x7172737475767778", "0x3132333435363738", "0x9192939495969798"],
"XMM10": ["0x4142434445464748", "0x6162636465666768", "0x2122232425262728", "0x9192939495969798"],
"XMM11": ["0x5152535455565758", "0x7172737475767778", "0x2122232425262728", "0x9192939495969798"]
}
}
%endif
lea rdx, [rel .data]
vmovapd ymm0, [rdx]
vmovapd ymm1, [rdx + 32]
vshufpd xmm2, xmm0, xmm1, 0b00
vshufpd xmm3, xmm0, xmm1, 0b01
vshufpd xmm4, xmm0, xmm1, 0b10
vshufpd xmm5, xmm0, xmm1, 0b11
vshufpd ymm6, ymm0, ymm1, 0b0000
vshufpd ymm7, ymm0, ymm1, 0b1000
vshufpd ymm8, ymm0, ymm1, 0b0101
vshufpd ymm9, ymm0, ymm1, 0b1010
vshufpd ymm10, ymm0, ymm1, 0b1100
vshufpd ymm11, ymm0, ymm1, 0b1111
hlt
align 32
.data:
dq 0x4142434445464748
dq 0x5152535455565758
dq 0x3132333435363738
dq 0x2122232425262728
dq 0x6162636465666768
dq 0x7172737475767778
dq 0x8182838485868788
dq 0x9192939495969798