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RAValidation: fix spillregister validation

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It doesn't write to its node. Fixes spurious

  %7: Arg[0] expects reg0 to contain %4, but it actually contains %16

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig 2024-04-19 16:08:27 -04:00
parent 579fb42458
commit 6e0f5eccb3
1 changed files with 3 additions and 1 deletions
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4
FEXCore/Source/Interface/IR/Passes/RAValidation.cpp
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@ -198,7 +198,9 @@ bool RAValidation::Run(IREmitter* IREmit) {
}
// Update BlockState map
BlockRegState.Set(RAData->GetNodeRegister(ID), ID);
if (IROp->Op != OP_SPILLREGISTER) {
BlockRegState.Set(RAData->GetNodeRegister(ID), ID);
}
}
}