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AVX128: Implements support for vector AES instructions

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Ryan Houdek 2024-06-19 02:00:28 -07:00 committed by Alyssa Rosenzweig
parent 4a66d4570e
commit 7532337231
2 changed files with 48 additions and 6 deletions
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6
FEXCore/Source/Interface/Core/OpcodeDispatcher.h
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@ -1123,6 +1123,12 @@ public:
void AVX128_Vector_CVT_Int_To_Float(OpcodeArgs); void AVX128_Vector_CVT_Int_To_Float(OpcodeArgs);
void AVX128_VEXTRACT128(OpcodeArgs); void AVX128_VEXTRACT128(OpcodeArgs);
void AVX128_VAESImc(OpcodeArgs);
void AVX128_VAESEnc(OpcodeArgs);
void AVX128_VAESEncLast(OpcodeArgs);
void AVX128_VAESDec(OpcodeArgs);
void AVX128_VAESDecLast(OpcodeArgs);
void AVX128_VAESKeyGenAssist(OpcodeArgs);
// End of AVX 128-bit implementation // End of AVX 128-bit implementation

48
FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp
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@ -327,11 +327,11 @@ void OpDispatchBuilder::InstallAVX128Handlers() {
// TODO: {OPD(2, 0b01, 0x8C), 1, &OpDispatchBuilder::VPMASKMOVOp<false>}, // TODO: {OPD(2, 0b01, 0x8C), 1, &OpDispatchBuilder::VPMASKMOVOp<false>},
// TODO: {OPD(2, 0b01, 0x8E), 1, &OpDispatchBuilder::VPMASKMOVOp<true>}, // TODO: {OPD(2, 0b01, 0x8E), 1, &OpDispatchBuilder::VPMASKMOVOp<true>},
// TODO: {OPD(2, 0b01, 0xDB), 1, &OpDispatchBuilder::AESImcOp}, {OPD(2, 0b01, 0xDB), 1, &OpDispatchBuilder::AVX128_VAESImc},
// TODO: {OPD(2, 0b01, 0xDC), 1, &OpDispatchBuilder::VAESEncOp}, {OPD(2, 0b01, 0xDC), 1, &OpDispatchBuilder::AVX128_VAESEnc},
// TODO: {OPD(2, 0b01, 0xDD), 1, &OpDispatchBuilder::VAESEncLastOp}, {OPD(2, 0b01, 0xDD), 1, &OpDispatchBuilder::AVX128_VAESEncLast},
// TODO: {OPD(2, 0b01, 0xDE), 1, &OpDispatchBuilder::VAESDecOp}, {OPD(2, 0b01, 0xDE), 1, &OpDispatchBuilder::AVX128_VAESDec},
// TODO: {OPD(2, 0b01, 0xDF), 1, &OpDispatchBuilder::VAESDecLastOp}, {OPD(2, 0b01, 0xDF), 1, &OpDispatchBuilder::AVX128_VAESDecLast},
// TODO: {OPD(3, 0b01, 0x00), 1, &OpDispatchBuilder::VPERMQOp}, // TODO: {OPD(3, 0b01, 0x00), 1, &OpDispatchBuilder::VPERMQOp},
// TODO: {OPD(3, 0b01, 0x01), 1, &OpDispatchBuilder::VPERMQOp}, // TODO: {OPD(3, 0b01, 0x01), 1, &OpDispatchBuilder::VPERMQOp},
@ -377,7 +377,7 @@ void OpDispatchBuilder::InstallAVX128Handlers() {
// TODO: {OPD(3, 0b01, 0x62), 1, &OpDispatchBuilder::VPCMPISTRMOp}, // TODO: {OPD(3, 0b01, 0x62), 1, &OpDispatchBuilder::VPCMPISTRMOp},
// TODO: {OPD(3, 0b01, 0x63), 1, &OpDispatchBuilder::VPCMPISTRIOp}, // TODO: {OPD(3, 0b01, 0x63), 1, &OpDispatchBuilder::VPCMPISTRIOp},
// TODO: {OPD(3, 0b01, 0xDF), 1, &OpDispatchBuilder::AESKeyGenAssist}, {OPD(3, 0b01, 0xDF), 1, &OpDispatchBuilder::AVX128_VAESKeyGenAssist},
}; };
#undef OPD #undef OPD
@ -1618,4 +1618,40 @@ void OpDispatchBuilder::AVX128_VEXTRACT128(OpcodeArgs) {
AVX128_StoreResult_WithOpSize(Op, Op->Dest, Result); AVX128_StoreResult_WithOpSize(Op, Op->Dest, Result);
} }
void OpDispatchBuilder::AVX128_VAESImc(OpcodeArgs) {
///< 128-bit only.
AVX128_VectorUnaryImpl(Op, OpSize::i128Bit, OpSize::i128Bit, [this](size_t, Ref Src) { return _VAESImc(Src); });
}
void OpDispatchBuilder::AVX128_VAESEnc(OpcodeArgs) {
AVX128_VectorTrinaryImpl(Op, GetDstSize(Op), OpSize::i128Bit, LoadZeroVector(OpSize::i128Bit),
[this](size_t, Ref Src1, Ref Src2, Ref Src3) { return _VAESEnc(OpSize::i128Bit, Src1, Src2, Src3); });
}
void OpDispatchBuilder::AVX128_VAESEncLast(OpcodeArgs) {
AVX128_VectorTrinaryImpl(Op, GetDstSize(Op), OpSize::i128Bit, LoadZeroVector(OpSize::i128Bit),
[this](size_t, Ref Src1, Ref Src2, Ref Src3) { return _VAESEncLast(OpSize::i128Bit, Src1, Src2, Src3); });
}
void OpDispatchBuilder::AVX128_VAESDec(OpcodeArgs) {
AVX128_VectorTrinaryImpl(Op, GetDstSize(Op), OpSize::i128Bit, LoadZeroVector(OpSize::i128Bit),
[this](size_t, Ref Src1, Ref Src2, Ref Src3) { return _VAESDec(OpSize::i128Bit, Src1, Src2, Src3); });
}
void OpDispatchBuilder::AVX128_VAESDecLast(OpcodeArgs) {
AVX128_VectorTrinaryImpl(Op, GetDstSize(Op), OpSize::i128Bit, LoadZeroVector(OpSize::i128Bit),
[this](size_t, Ref Src1, Ref Src2, Ref Src3) { return _VAESDecLast(OpSize::i128Bit, Src1, Src2, Src3); });
}
void OpDispatchBuilder::AVX128_VAESKeyGenAssist(OpcodeArgs) {
///< 128-bit only.
const uint64_t RCON = Op->Src[1].Literal();
auto ZeroRegister = LoadZeroVector(OpSize::i128Bit);
auto KeyGenSwizzle = LoadAndCacheNamedVectorConstant(OpSize::i128Bit, NAMED_VECTOR_AESKEYGENASSIST_SWIZZLE);
AVX128_VectorUnaryImpl(Op, OpSize::i128Bit, OpSize::i128Bit, [this, ZeroRegister, KeyGenSwizzle, RCON](size_t, Ref Src) {
return _VAESKeyGenAssist(Src, KeyGenSwizzle, ZeroRegister, RCON);
});
}
} // namespace FEXCore::IR } // namespace FEXCore::IR