mirror of
https://github.com/FEX-Emu/FEX.git
synced 2024-12-11 16:28:21 +00:00
InstCountCI: Update
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig
parent
4c4c6e7807
commit
75644b33df
@ -46,13 +46,12 @@
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]
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},
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"vmovups ymm0, [rax]": {
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"ExpectedInstructionCount": 3,
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b00 0x10 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q16, [x4]",
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"ldr q2, [x4, #16]",
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"ldp q16, q2, [x4]",
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"str q2, [x28, #16]"
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]
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},
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@ -89,13 +88,12 @@
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]
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},
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"vmovupd ymm0, [rax]": {
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"ExpectedInstructionCount": 3,
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b01 0x10 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q16, [x4]",
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"ldr q2, [x4, #16]",
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"ldp q16, q2, [x4]",
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"str q2, [x28, #16]"
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]
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},
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@ -156,14 +154,13 @@
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]
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},
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"vmovups [rax], ymm0": {
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"ExpectedInstructionCount": 3,
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b00 0x11 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q2, [x28, #16]",
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"str q16, [x4]",
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"str q2, [x4, #16]"
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"stp q16, q2, [x4]"
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]
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},
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"vmovupd [rax], xmm0": {
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@ -176,14 +173,13 @@
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]
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},
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"vmovupd [rax], ymm0": {
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"ExpectedInstructionCount": 3,
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b01 0x11 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q2, [x28, #16]",
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"str q16, [x4]",
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"str q2, [x4, #16]"
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"stp q16, q2, [x4]"
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]
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},
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"vmovss [rax], xmm0": {
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@ -272,13 +268,12 @@
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]
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},
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"vmovsldup ymm0, [rax]": {
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"ExpectedInstructionCount": 5,
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b10 0x12 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q2, [x4]",
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"ldr q3, [x4, #16]",
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"ldp q2, q3, [x4]",
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"trn1 v16.4s, v2.4s, v2.4s",
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"trn1 v2.4s, v3.4s, v3.4s",
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"str q2, [x28, #16]"
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@ -297,13 +292,12 @@
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]
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},
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"vmovddup ymm0, [rax]": {
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"ExpectedInstructionCount": 5,
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b11 0x12 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q2, [x4]",
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"ldr q3, [x4, #16]",
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"ldp q2, q3, [x4]",
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"dup v16.2d, v2.d[0]",
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"dup v2.2d, v3.d[0]",
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"str q2, [x28, #16]"
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@ -340,14 +334,13 @@
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]
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},
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"vunpcklps ymm0, ymm1, [rax]": {
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"ExpectedInstructionCount": 6,
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"ExpectedInstructionCount": 5,
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"Comment": [
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"Map 1 0b00 0x14 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q2, [x28, #32]",
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"ldr q3, [x4]",
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"ldr q4, [x4, #16]",
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"ldp q3, q4, [x4]",
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"zip1 v16.4s, v17.4s, v3.4s",
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"zip1 v2.4s, v2.4s, v4.4s",
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"str q2, [x28, #16]"
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@ -366,14 +359,13 @@
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]
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},
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"vunpcklpd ymm0, ymm1, [rax]": {
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"ExpectedInstructionCount": 6,
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"ExpectedInstructionCount": 5,
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"Comment": [
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"Map 1 0b01 0x14 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q2, [x28, #32]",
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"ldr q3, [x4]",
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"ldr q4, [x4, #16]",
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"ldp q3, q4, [x4]",
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"zip1 v16.2d, v17.2d, v3.2d",
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"zip1 v2.2d, v2.2d, v4.2d",
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"str q2, [x28, #16]"
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@ -392,14 +384,13 @@
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]
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},
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"vunpckhps ymm0, ymm1, [rax]": {
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"ExpectedInstructionCount": 6,
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"ExpectedInstructionCount": 5,
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"Comment": [
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"Map 1 0b00 0x15 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q2, [x28, #32]",
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"ldr q3, [x4]",
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"ldr q4, [x4, #16]",
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"ldp q3, q4, [x4]",
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"zip2 v16.4s, v17.4s, v3.4s",
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"zip2 v2.4s, v2.4s, v4.4s",
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"str q2, [x28, #16]"
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@ -418,14 +409,13 @@
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]
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},
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"vunpckhpd ymm0, ymm1, [rax]": {
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"ExpectedInstructionCount": 6,
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"ExpectedInstructionCount": 5,
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"Comment": [
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"Map 1 0b01 0x15 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q2, [x28, #32]",
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"ldr q3, [x4]",
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"ldr q4, [x4, #16]",
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"ldp q3, q4, [x4]",
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"zip2 v16.2d, v17.2d, v3.2d",
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"zip2 v2.2d, v2.2d, v4.2d",
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"str q2, [x28, #16]"
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@ -479,13 +469,12 @@
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]
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},
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"vmovshdup ymm0, [rax]": {
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"ExpectedInstructionCount": 5,
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b10 0x16 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q2, [x4]",
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"ldr q3, [x4, #16]",
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"ldp q2, q3, [x4]",
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"trn2 v16.4s, v2.4s, v2.4s",
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"trn2 v2.4s, v3.4s, v3.4s",
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"str q2, [x28, #16]"
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@ -1634,33 +1623,25 @@
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]
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},
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"vzeroupper": {
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"ExpectedInstructionCount": 17,
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"ExpectedInstructionCount": 9,
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"Comment": [
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"Might be able to use DZ ZVA",
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"Map 1 0b01 0x77 L=0"
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],
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"ExpectedArm64ASM": [
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"movi v2.2d, #0x0",
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"str q2, [x28, #256]",
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"str q2, [x28, #240]",
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"str q2, [x28, #224]",
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"str q2, [x28, #208]",
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"str q2, [x28, #192]",
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"str q2, [x28, #176]",
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"str q2, [x28, #160]",
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"str q2, [x28, #144]",
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"str q2, [x28, #128]",
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"str q2, [x28, #112]",
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"str q2, [x28, #96]",
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"str q2, [x28, #80]",
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"str q2, [x28, #64]",
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"str q2, [x28, #48]",
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"str q2, [x28, #32]",
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"str q2, [x28, #16]"
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"stp q2, q2, [x28, #240]",
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"stp q2, q2, [x28, #208]",
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"stp q2, q2, [x28, #176]",
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"stp q2, q2, [x28, #144]",
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"stp q2, q2, [x28, #112]",
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"stp q2, q2, [x28, #80]",
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"stp q2, q2, [x28, #48]",
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"stp q2, q2, [x28, #16]"
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]
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},
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"vzeroall": {
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"ExpectedInstructionCount": 32,
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"ExpectedInstructionCount": 24,
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"Comment": [
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"Might be able to use DZ ZVA",
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"Map 1 0b01 0x77 L=1"
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@ -1682,22 +1663,14 @@
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"movi v29.2d, #0x0",
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"movi v30.2d, #0x0",
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"movi v31.2d, #0x0",
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"str q31, [x28, #256]",
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"str q31, [x28, #240]",
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"str q31, [x28, #224]",
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"str q31, [x28, #208]",
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"str q31, [x28, #192]",
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"str q31, [x28, #176]",
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"str q31, [x28, #160]",
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"str q31, [x28, #144]",
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"str q31, [x28, #128]",
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"str q31, [x28, #112]",
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"str q31, [x28, #96]",
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"str q31, [x28, #80]",
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"str q31, [x28, #64]",
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"str q31, [x28, #48]",
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"str q31, [x28, #32]",
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"str q31, [x28, #16]"
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"stp q31, q31, [x28, #240]",
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"stp q31, q31, [x28, #208]",
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"stp q31, q31, [x28, #176]",
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"stp q31, q31, [x28, #144]",
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"stp q31, q31, [x28, #112]",
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"stp q31, q31, [x28, #80]",
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"stp q31, q31, [x28, #48]",
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"stp q31, q31, [x28, #16]"
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]
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},
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"vcmpps xmm0, xmm1, xmm2, 0x00": {
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@ -2631,13 +2604,12 @@
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]
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},
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"vmovaps ymm0, [rax]": {
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"ExpectedInstructionCount": 3,
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b00 0x28 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q16, [x4]",
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"ldr q2, [x4, #16]",
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"ldp q16, q2, [x4]",
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"str q2, [x28, #16]"
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]
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},
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@ -2675,13 +2647,12 @@
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]
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},
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"vmovapd ymm0, [rax]": {
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"ExpectedInstructionCount": 3,
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b01 0x28 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q16, [x4]",
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"ldr q2, [x4, #16]",
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"ldp q16, q2, [x4]",
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"str q2, [x28, #16]"
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]
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},
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@ -2717,14 +2688,13 @@
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]
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},
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"vmovaps [rax], ymm0": {
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"ExpectedInstructionCount": 3,
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b00 0x29 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q2, [x28, #16]",
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"str q16, [x4]",
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"str q2, [x4, #16]"
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"stp q16, q2, [x4]"
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]
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},
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"vmovapd [rax], xmm0": {
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@ -2737,14 +2707,13 @@
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]
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},
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"vmovapd [rax], ymm0": {
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"ExpectedInstructionCount": 3,
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"ExpectedInstructionCount": 2,
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"Comment": [
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"Map 1 0b01 0x29 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q2, [x28, #16]",
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"str q16, [x4]",
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"str q2, [x4, #16]"
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"stp q16, q2, [x4]"
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]
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},
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"vcvtsi2ss xmm0, xmm1, eax": {
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@ -3161,13 +3130,12 @@
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]
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},
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"vcvtpd2ps xmm0, yword [rax]": {
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"ExpectedInstructionCount": 8,
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"ExpectedInstructionCount": 7,
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"Comment": [
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"Map 1 0b01 0x5a 128-bit"
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],
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"ExpectedArm64ASM": [
|
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"ldr q2, [x4]",
|
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"ldr q3, [x4, #16]",
|
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"ldp q2, q3, [x4]",
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"fcvtn v2.2s, v2.2d",
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"fcvtn v3.2s, v3.2d",
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"mov v16.16b, v2.16b",
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@ -4005,47 +3973,43 @@
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]
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},
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"vmovdqa ymm0, [rax]": {
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"ExpectedInstructionCount": 3,
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"ExpectedInstructionCount": 2,
|
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"Comment": [
|
||||
"Map 1 0b01 0x7f 128-bit"
|
||||
],
|
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"ExpectedArm64ASM": [
|
||||
"ldr q16, [x4]",
|
||||
"ldr q2, [x4, #16]",
|
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"ldp q16, q2, [x4]",
|
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"str q2, [x28, #16]"
|
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]
|
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},
|
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"vmovdqa [rax], ymm0": {
|
||||
"ExpectedInstructionCount": 3,
|
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"ExpectedInstructionCount": 2,
|
||||
"Comment": [
|
||||
"Map 1 0b01 0x7f 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #16]",
|
||||
"str q16, [x4]",
|
||||
"str q2, [x4, #16]"
|
||||
"stp q16, q2, [x4]"
|
||||
]
|
||||
},
|
||||
"vmovdqu ymm0, [rax]": {
|
||||
"ExpectedInstructionCount": 3,
|
||||
"ExpectedInstructionCount": 2,
|
||||
"Comment": [
|
||||
"Map 1 0b10 0x7f 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q16, [x4]",
|
||||
"ldr q2, [x4, #16]",
|
||||
"ldp q16, q2, [x4]",
|
||||
"str q2, [x28, #16]"
|
||||
]
|
||||
},
|
||||
"vmovdqu [rax], ymm0": {
|
||||
"ExpectedInstructionCount": 3,
|
||||
"ExpectedInstructionCount": 2,
|
||||
"Comment": [
|
||||
"Map 1 0b10 0x7f 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #16]",
|
||||
"str q16, [x4]",
|
||||
"str q2, [x4, #16]"
|
||||
"stp q16, q2, [x4]"
|
||||
]
|
||||
},
|
||||
"vaddsubpd xmm0, xmm1, xmm2": {
|
||||
@ -5178,13 +5142,12 @@
|
||||
]
|
||||
},
|
||||
"vlddqu ymm0, [rax]": {
|
||||
"ExpectedInstructionCount": 3,
|
||||
"ExpectedInstructionCount": 2,
|
||||
"Comment": [
|
||||
"Map 1 0b11 0xf0 256-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q16, [x4]",
|
||||
"ldr q2, [x4, #16]",
|
||||
"ldp q16, q2, [x4]",
|
||||
"str q2, [x28, #16]"
|
||||
]
|
||||
},
|
||||
|
||||
@ -1054,101 +1054,83 @@
|
||||
]
|
||||
},
|
||||
"vmovdqu ymm7,yword [rsi+0x60]": {
|
||||
"ExpectedInstructionCount": 3,
|
||||
"ExpectedInstructionCount": 2,
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q23, [x10, #96]",
|
||||
"ldr q2, [x10, #112]",
|
||||
"ldp q23, q2, [x10, #96]",
|
||||
"str q2, [x28, #128]"
|
||||
]
|
||||
},
|
||||
"vmovdqu ymm7,yword [rsi+0x120]": {
|
||||
"ExpectedInstructionCount": 3,
|
||||
"ExpectedInstructionCount": 2,
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q23, [x10, #288]",
|
||||
"ldr q2, [x10, #304]",
|
||||
"ldp q23, q2, [x10, #288]",
|
||||
"str q2, [x28, #128]"
|
||||
]
|
||||
},
|
||||
"vmovdqu ymm7,yword [rsi-0x60]": {
|
||||
"ExpectedInstructionCount": 3,
|
||||
"ExpectedInstructionCount": 2,
|
||||
"ExpectedArm64ASM": [
|
||||
"ldur q23, [x10, #-96]",
|
||||
"ldur q2, [x10, #-80]",
|
||||
"ldp q23, q2, [x10, #-96]",
|
||||
"str q2, [x28, #128]"
|
||||
]
|
||||
},
|
||||
"vmovdqu ymm7,yword [rsi-0x400]": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 2,
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, #0xfffffffffffffc00",
|
||||
"ldr q23, [x10, x20, sxtx]",
|
||||
"mov x20, #0xfffffffffffffc10",
|
||||
"ldr q2, [x10, x20, sxtx]",
|
||||
"ldp q23, q2, [x10, #-1024]",
|
||||
"str q2, [x28, #128]"
|
||||
]
|
||||
},
|
||||
"vmovdqu ymm7,yword [rsi-0x420]": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, #0xfffffffffffffbe0",
|
||||
"ldr q23, [x10, x20, sxtx]",
|
||||
"mov x20, #0xfffffffffffffbf0",
|
||||
"ldr q2, [x10, x20, sxtx]",
|
||||
"sub x20, x10, #0x420 (1056)",
|
||||
"ldp q23, q2, [x20]",
|
||||
"str q2, [x28, #128]"
|
||||
]
|
||||
},
|
||||
"vmovdqu ymm7,yword [rsi+0x3d0]": {
|
||||
"ExpectedInstructionCount": 3,
|
||||
"ExpectedInstructionCount": 2,
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q23, [x10, #976]",
|
||||
"ldr q2, [x10, #992]",
|
||||
"ldp q23, q2, [x10, #976]",
|
||||
"str q2, [x28, #128]"
|
||||
]
|
||||
},
|
||||
"vmovdqu ymm7,yword [rsi+0x400]": {
|
||||
"ExpectedInstructionCount": 3,
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q23, [x10, #1024]",
|
||||
"ldr q2, [x10, #1040]",
|
||||
"add x20, x10, #0x400 (1024)",
|
||||
"ldp q23, q2, [x20]",
|
||||
"str q2, [x28, #128]"
|
||||
]
|
||||
},
|
||||
"vmovdqa yword [rcx+0x60],ymm1": {
|
||||
"ExpectedInstructionCount": 3,
|
||||
"ExpectedInstructionCount": 2,
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #32]",
|
||||
"str q17, [x5, #96]",
|
||||
"str q2, [x5, #112]"
|
||||
"stp q17, q2, [x5, #96]"
|
||||
]
|
||||
},
|
||||
"vmovdqa yword [rcx+0x3d0],ymm1": {
|
||||
"ExpectedInstructionCount": 3,
|
||||
"ExpectedInstructionCount": 2,
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #32]",
|
||||
"str q17, [x5, #976]",
|
||||
"str q2, [x5, #992]"
|
||||
"stp q17, q2, [x5, #976]"
|
||||
]
|
||||
},
|
||||
"vmovdqa yword [rcx-0x3d0],ymm1": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 2,
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #32]",
|
||||
"mov x20, #0xfffffffffffffc30",
|
||||
"str q17, [x5, x20, sxtx]",
|
||||
"mov x20, #0xfffffffffffffc40",
|
||||
"str q2, [x5, x20, sxtx]"
|
||||
"stp q17, q2, [x5, #-976]"
|
||||
]
|
||||
},
|
||||
"vmovdqa yword [rcx+rsi-0x3d0],ymm1": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #32]",
|
||||
"add x20, x5, x10",
|
||||
"mov x21, #0xfffffffffffffc30",
|
||||
"str q17, [x20, x21, sxtx]",
|
||||
"add x20, x5, x10",
|
||||
"mov x21, #0xfffffffffffffc40",
|
||||
"str q2, [x20, x21, sxtx]"
|
||||
"stp q17, q2, [x20, #-976]"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
||||
@ -429,7 +429,7 @@
|
||||
]
|
||||
},
|
||||
"glibc AVX memcpy block 1": {
|
||||
"ExpectedInstructionCount": 43,
|
||||
"ExpectedInstructionCount": 26,
|
||||
"x86Insts": [
|
||||
"vmovdqu ymm5,yword [rsi+0x20]",
|
||||
"vmovdqu ymm6,yword [rsi+0x40]",
|
||||
@ -453,53 +453,36 @@
|
||||
"cmp rdi,rcx"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q21, [x10, #32]",
|
||||
"ldr q2, [x10, #48]",
|
||||
"ldr q22, [x10, #64]",
|
||||
"ldr q3, [x10, #80]",
|
||||
"ldp q21, q2, [x10, #32]",
|
||||
"ldp q22, q3, [x10, #64]",
|
||||
"sub x20, x11, #0x81 (129)",
|
||||
"add x5, x20, x6",
|
||||
"ldr q23, [x10, #96]",
|
||||
"ldr q4, [x10, #112]",
|
||||
"ldp q23, q4, [x10, #96]",
|
||||
"add x20, x10, x6",
|
||||
"ldur q24, [x20, #-32]",
|
||||
"add x20, x10, x6",
|
||||
"ldur q5, [x20, #-16]",
|
||||
"ldp q24, q5, [x20, #-32]",
|
||||
"sub x10, x10, x11",
|
||||
"and x5, x5, #0xffffffffffffffe0",
|
||||
"add x10, x10, x5",
|
||||
"ldr q17, [x10, #96]",
|
||||
"ldr q6, [x10, #112]",
|
||||
"ldr q18, [x10, #64]",
|
||||
"ldr q7, [x10, #80]",
|
||||
"ldr q19, [x10, #32]",
|
||||
"ldr q8, [x10, #48]",
|
||||
"ldr q20, [x10]",
|
||||
"ldr q9, [x10, #16]",
|
||||
"ldp q17, q6, [x10, #96]",
|
||||
"ldp q18, q7, [x10, #64]",
|
||||
"ldp q19, q8, [x10, #32]",
|
||||
"ldp q20, q9, [x10]",
|
||||
"sub x10, x10, #0x80 (128)",
|
||||
"str q17, [x5, #96]",
|
||||
"str q6, [x5, #112]",
|
||||
"str q18, [x5, #64]",
|
||||
"str q7, [x5, #80]",
|
||||
"str q19, [x5, #32]",
|
||||
"str q8, [x5, #48]",
|
||||
"str q20, [x5]",
|
||||
"str q9, [x5, #16]",
|
||||
"stp q17, q6, [x5, #96]",
|
||||
"stp q18, q7, [x5, #64]",
|
||||
"stp q19, q8, [x5, #32]",
|
||||
"stp q20, q9, [x5]",
|
||||
"sub x5, x5, #0x80 (128)",
|
||||
"eor w27, w11, w5",
|
||||
"subs x26, x11, x5",
|
||||
"str q5, [x28, #144]",
|
||||
"str q4, [x28, #128]",
|
||||
"str q3, [x28, #112]",
|
||||
"str q2, [x28, #96]",
|
||||
"str q9, [x28, #80]",
|
||||
"str q8, [x28, #64]",
|
||||
"str q7, [x28, #48]",
|
||||
"str q6, [x28, #32]"
|
||||
"stp q4, q5, [x28, #128]",
|
||||
"stp q2, q3, [x28, #96]",
|
||||
"stp q8, q9, [x28, #64]",
|
||||
"stp q6, q7, [x28, #32]"
|
||||
]
|
||||
},
|
||||
"glibc AVX memcpy block 2": {
|
||||
"ExpectedInstructionCount": 51,
|
||||
"ExpectedInstructionCount": 31,
|
||||
"x86Insts": [
|
||||
"vmovdqu ymm5,yword [rsi+rdx*1-0x20]",
|
||||
"vmovdqu ymm6,yword [rsi+rdx*1-0x40]",
|
||||
@ -526,56 +509,36 @@
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"add x20, x10, x6",
|
||||
"ldur q21, [x20, #-32]",
|
||||
"ldp q21, q2, [x20, #-32]",
|
||||
"add x20, x10, x6",
|
||||
"ldur q2, [x20, #-16]",
|
||||
"add x20, x10, x6",
|
||||
"ldur q22, [x20, #-64]",
|
||||
"add x20, x10, x6",
|
||||
"ldur q3, [x20, #-48]",
|
||||
"ldp q22, q3, [x20, #-64]",
|
||||
"mov x5, x11",
|
||||
"orr x11, x11, #0x1f",
|
||||
"add x20, x10, x6",
|
||||
"ldur q23, [x20, #-96]",
|
||||
"ldp q23, q4, [x20, #-96]",
|
||||
"add x20, x10, x6",
|
||||
"ldur q4, [x20, #-80]",
|
||||
"add x20, x10, x6",
|
||||
"ldur q24, [x20, #-128]",
|
||||
"add x20, x10, x6",
|
||||
"ldur q5, [x20, #-112]",
|
||||
"ldp q24, q5, [x20, #-128]",
|
||||
"sub x10, x10, x5",
|
||||
"add x11, x11, #0x1 (1)",
|
||||
"add x10, x10, x11",
|
||||
"sub x20, x5, #0x80 (128)",
|
||||
"add x6, x20, x6",
|
||||
"ldr q17, [x10]",
|
||||
"ldr q6, [x10, #16]",
|
||||
"ldr q18, [x10, #32]",
|
||||
"ldr q7, [x10, #48]",
|
||||
"ldr q19, [x10, #64]",
|
||||
"ldr q8, [x10, #80]",
|
||||
"ldr q20, [x10, #96]",
|
||||
"ldr q9, [x10, #112]",
|
||||
"ldp q17, q6, [x10]",
|
||||
"ldp q18, q7, [x10, #32]",
|
||||
"ldp q19, q8, [x10, #64]",
|
||||
"ldp q20, q9, [x10, #96]",
|
||||
"add x10, x10, #0x80 (128)",
|
||||
"str q17, [x11]",
|
||||
"str q6, [x11, #16]",
|
||||
"str q18, [x11, #32]",
|
||||
"str q7, [x11, #48]",
|
||||
"str q19, [x11, #64]",
|
||||
"str q8, [x11, #80]",
|
||||
"str q20, [x11, #96]",
|
||||
"str q9, [x11, #112]",
|
||||
"stp q17, q6, [x11]",
|
||||
"stp q18, q7, [x11, #32]",
|
||||
"stp q19, q8, [x11, #64]",
|
||||
"stp q20, q9, [x11, #96]",
|
||||
"add x11, x11, #0x80 (128)",
|
||||
"eor w27, w6, w11",
|
||||
"subs x26, x6, x11",
|
||||
"str q5, [x28, #144]",
|
||||
"str q4, [x28, #128]",
|
||||
"str q3, [x28, #112]",
|
||||
"str q2, [x28, #96]",
|
||||
"str q9, [x28, #80]",
|
||||
"str q8, [x28, #64]",
|
||||
"str q7, [x28, #48]",
|
||||
"str q6, [x28, #32]"
|
||||
"stp q4, q5, [x28, #128]",
|
||||
"stp q2, q3, [x28, #96]",
|
||||
"stp q8, q9, [x28, #64]",
|
||||
"stp q6, q7, [x28, #32]"
|
||||
]
|
||||
},
|
||||
"bytemark strsift": {
|
||||
|
||||
@ -1216,7 +1216,7 @@
|
||||
]
|
||||
},
|
||||
"fxsave [rax]": {
|
||||
"ExpectedInstructionCount": 52,
|
||||
"ExpectedInstructionCount": 39,
|
||||
"Comment": "GROUP15 0x0F 0xAE /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldrh w20, [x28, #1296]",
|
||||
@ -1235,42 +1235,29 @@
|
||||
"ldrb w20, [x28, #1298]",
|
||||
"strb w20, [x4, #4]",
|
||||
"ldr q2, [x28, #1040]",
|
||||
"str q2, [x4, #32]",
|
||||
"ldr q2, [x28, #1056]",
|
||||
"str q2, [x4, #48]",
|
||||
"ldr q3, [x28, #1056]",
|
||||
"stp q2, q3, [x4, #32]",
|
||||
"ldr q2, [x28, #1072]",
|
||||
"str q2, [x4, #64]",
|
||||
"ldr q2, [x28, #1088]",
|
||||
"str q2, [x4, #80]",
|
||||
"ldr q3, [x28, #1088]",
|
||||
"stp q2, q3, [x4, #64]",
|
||||
"ldr q2, [x28, #1104]",
|
||||
"str q2, [x4, #96]",
|
||||
"ldr q2, [x28, #1120]",
|
||||
"str q2, [x4, #112]",
|
||||
"ldr q3, [x28, #1120]",
|
||||
"stp q2, q3, [x4, #96]",
|
||||
"ldr q2, [x28, #1136]",
|
||||
"str q2, [x4, #128]",
|
||||
"ldr q2, [x28, #1152]",
|
||||
"str q2, [x4, #144]",
|
||||
"str q16, [x4, #160]",
|
||||
"str q17, [x4, #176]",
|
||||
"str q18, [x4, #192]",
|
||||
"str q19, [x4, #208]",
|
||||
"str q20, [x4, #224]",
|
||||
"str q21, [x4, #240]",
|
||||
"str q22, [x4, #256]",
|
||||
"str q23, [x4, #272]",
|
||||
"str q24, [x4, #288]",
|
||||
"str q25, [x4, #304]",
|
||||
"str q26, [x4, #320]",
|
||||
"str q27, [x4, #336]",
|
||||
"str q28, [x4, #352]",
|
||||
"str q29, [x4, #368]",
|
||||
"str q30, [x4, #384]",
|
||||
"str q31, [x4, #400]",
|
||||
"ldr q3, [x28, #1152]",
|
||||
"stp q2, q3, [x4, #128]",
|
||||
"stp q16, q17, [x4, #160]",
|
||||
"stp q18, q19, [x4, #192]",
|
||||
"stp q20, q21, [x4, #224]",
|
||||
"stp q22, q23, [x4, #256]",
|
||||
"stp q24, q25, [x4, #288]",
|
||||
"stp q26, q27, [x4, #320]",
|
||||
"stp q28, q29, [x4, #352]",
|
||||
"stp q30, q31, [x4, #384]",
|
||||
"ldr w20, [x28, #940]",
|
||||
"and w20, w20, #0xffc0",
|
||||
"str w20, [x4, #24]",
|
||||
"mov w20, #0xffff",
|
||||
"str w20, [x4, #28]"
|
||||
"mov w21, #0xffff",
|
||||
"stp w20, w21, [x4, #24]"
|
||||
]
|
||||
},
|
||||
"rdfsbase eax": {
|
||||
@ -1288,7 +1275,7 @@
|
||||
]
|
||||
},
|
||||
"fxrstor [rax]": {
|
||||
"ExpectedInstructionCount": 58,
|
||||
"ExpectedInstructionCount": 46,
|
||||
"Comment": "GROUP15 0x0F 0xAE /1",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldrh w20, [x4]",
|
||||
@ -1305,30 +1292,18 @@
|
||||
"strb w23, [x28, #1018]",
|
||||
"strb w20, [x28, #1022]",
|
||||
"ldrb w20, [x4, #4]",
|
||||
"ldr q2, [x4, #32]",
|
||||
"ldr q3, [x4, #48]",
|
||||
"ldr q4, [x4, #64]",
|
||||
"ldr q5, [x4, #80]",
|
||||
"ldr q6, [x4, #96]",
|
||||
"ldr q7, [x4, #112]",
|
||||
"ldr q8, [x4, #128]",
|
||||
"ldr q9, [x4, #144]",
|
||||
"ldr q16, [x4, #160]",
|
||||
"ldr q17, [x4, #176]",
|
||||
"ldr q18, [x4, #192]",
|
||||
"ldr q19, [x4, #208]",
|
||||
"ldr q20, [x4, #224]",
|
||||
"ldr q21, [x4, #240]",
|
||||
"ldr q22, [x4, #256]",
|
||||
"ldr q23, [x4, #272]",
|
||||
"ldr q24, [x4, #288]",
|
||||
"ldr q25, [x4, #304]",
|
||||
"ldr q26, [x4, #320]",
|
||||
"ldr q27, [x4, #336]",
|
||||
"ldr q28, [x4, #352]",
|
||||
"ldr q29, [x4, #368]",
|
||||
"ldr q30, [x4, #384]",
|
||||
"ldr q31, [x4, #400]",
|
||||
"ldp q2, q3, [x4, #32]",
|
||||
"ldp q4, q5, [x4, #64]",
|
||||
"ldp q6, q7, [x4, #96]",
|
||||
"ldp q8, q9, [x4, #128]",
|
||||
"ldp q16, q17, [x4, #160]",
|
||||
"ldp q18, q19, [x4, #192]",
|
||||
"ldp q20, q21, [x4, #224]",
|
||||
"ldp q22, q23, [x4, #256]",
|
||||
"ldp q24, q25, [x4, #288]",
|
||||
"ldp q26, q27, [x4, #320]",
|
||||
"ldp q28, q29, [x4, #352]",
|
||||
"ldp q30, q31, [x4, #384]",
|
||||
"ldr w21, [x4, #24]",
|
||||
"and w21, w21, #0xffc0",
|
||||
"str w21, [x28, #940]",
|
||||
@ -1422,12 +1397,12 @@
|
||||
]
|
||||
},
|
||||
"xsave [rax]": {
|
||||
"ExpectedInstructionCount": 98,
|
||||
"ExpectedInstructionCount": 69,
|
||||
"Comment": "GROUP15 0x0F 0xAE /4",
|
||||
"ExpectedArm64ASM": [
|
||||
"ubfx x20, x4, #0, #1",
|
||||
"cbnz x20, #+0x8",
|
||||
"b #+0x80",
|
||||
"b #+0x70",
|
||||
"ldrh w20, [x28, #1296]",
|
||||
"strh w20, [x4]",
|
||||
"ldrb w20, [x28, #1019]",
|
||||
@ -1444,83 +1419,54 @@
|
||||
"ldrb w20, [x28, #1298]",
|
||||
"strb w20, [x4, #4]",
|
||||
"ldr q2, [x28, #1040]",
|
||||
"str q2, [x4, #32]",
|
||||
"ldr q2, [x28, #1056]",
|
||||
"str q2, [x4, #48]",
|
||||
"ldr q3, [x28, #1056]",
|
||||
"stp q2, q3, [x4, #32]",
|
||||
"ldr q2, [x28, #1072]",
|
||||
"str q2, [x4, #64]",
|
||||
"ldr q2, [x28, #1088]",
|
||||
"str q2, [x4, #80]",
|
||||
"ldr q3, [x28, #1088]",
|
||||
"stp q2, q3, [x4, #64]",
|
||||
"ldr q2, [x28, #1104]",
|
||||
"str q2, [x4, #96]",
|
||||
"ldr q2, [x28, #1120]",
|
||||
"str q2, [x4, #112]",
|
||||
"ldr q3, [x28, #1120]",
|
||||
"stp q2, q3, [x4, #96]",
|
||||
"ldr q2, [x28, #1136]",
|
||||
"str q2, [x4, #128]",
|
||||
"ldr q2, [x28, #1152]",
|
||||
"str q2, [x4, #144]",
|
||||
"ldr q3, [x28, #1152]",
|
||||
"stp q2, q3, [x4, #128]",
|
||||
"ubfx x20, x4, #1, #1",
|
||||
"cbnz x20, #+0x8",
|
||||
"b #+0x44",
|
||||
"str q16, [x4, #160]",
|
||||
"str q17, [x4, #176]",
|
||||
"str q18, [x4, #192]",
|
||||
"str q19, [x4, #208]",
|
||||
"str q20, [x4, #224]",
|
||||
"str q21, [x4, #240]",
|
||||
"str q22, [x4, #256]",
|
||||
"str q23, [x4, #272]",
|
||||
"str q24, [x4, #288]",
|
||||
"str q25, [x4, #304]",
|
||||
"str q26, [x4, #320]",
|
||||
"str q27, [x4, #336]",
|
||||
"str q28, [x4, #352]",
|
||||
"str q29, [x4, #368]",
|
||||
"str q30, [x4, #384]",
|
||||
"str q31, [x4, #400]",
|
||||
"b #+0x24",
|
||||
"stp q16, q17, [x4, #160]",
|
||||
"stp q18, q19, [x4, #192]",
|
||||
"stp q20, q21, [x4, #224]",
|
||||
"stp q22, q23, [x4, #256]",
|
||||
"stp q24, q25, [x4, #288]",
|
||||
"stp q26, q27, [x4, #320]",
|
||||
"stp q28, q29, [x4, #352]",
|
||||
"stp q30, q31, [x4, #384]",
|
||||
"ubfx x20, x4, #2, #1",
|
||||
"cbnz x20, #+0x8",
|
||||
"b #+0x84",
|
||||
"ldr q2, [x28, #16]",
|
||||
"str q2, [x4, #576]",
|
||||
"ldr q2, [x28, #32]",
|
||||
"str q2, [x4, #592]",
|
||||
"ldr q2, [x28, #48]",
|
||||
"str q2, [x4, #608]",
|
||||
"ldr q2, [x28, #64]",
|
||||
"str q2, [x4, #624]",
|
||||
"ldr q2, [x28, #80]",
|
||||
"str q2, [x4, #640]",
|
||||
"ldr q2, [x28, #96]",
|
||||
"str q2, [x4, #656]",
|
||||
"ldr q2, [x28, #112]",
|
||||
"str q2, [x4, #672]",
|
||||
"ldr q2, [x28, #128]",
|
||||
"str q2, [x4, #688]",
|
||||
"ldr q2, [x28, #144]",
|
||||
"str q2, [x4, #704]",
|
||||
"ldr q2, [x28, #160]",
|
||||
"str q2, [x4, #720]",
|
||||
"ldr q2, [x28, #176]",
|
||||
"str q2, [x4, #736]",
|
||||
"ldr q2, [x28, #192]",
|
||||
"str q2, [x4, #752]",
|
||||
"ldr q2, [x28, #208]",
|
||||
"str q2, [x4, #768]",
|
||||
"ldr q2, [x28, #224]",
|
||||
"str q2, [x4, #784]",
|
||||
"ldr q2, [x28, #240]",
|
||||
"str q2, [x4, #800]",
|
||||
"ldr q2, [x28, #256]",
|
||||
"str q2, [x4, #816]",
|
||||
"b #+0x44",
|
||||
"ldp q2, q3, [x28, #16]",
|
||||
"stp q2, q3, [x4, #576]",
|
||||
"ldp q2, q3, [x28, #48]",
|
||||
"stp q2, q3, [x4, #608]",
|
||||
"ldp q2, q3, [x28, #80]",
|
||||
"stp q2, q3, [x4, #640]",
|
||||
"ldp q2, q3, [x28, #112]",
|
||||
"stp q2, q3, [x4, #672]",
|
||||
"ldp q2, q3, [x28, #144]",
|
||||
"stp q2, q3, [x4, #704]",
|
||||
"ldp q2, q3, [x28, #176]",
|
||||
"stp q2, q3, [x4, #736]",
|
||||
"ldp q2, q3, [x28, #208]",
|
||||
"stp q2, q3, [x4, #768]",
|
||||
"ldp q2, q3, [x28, #240]",
|
||||
"stp q2, q3, [x4, #800]",
|
||||
"ubfx x20, x4, #1, #2",
|
||||
"cbnz x20, #+0x8",
|
||||
"b #+0x18",
|
||||
"b #+0x14",
|
||||
"ldr w20, [x28, #940]",
|
||||
"and w20, w20, #0xffc0",
|
||||
"str w20, [x4, #24]",
|
||||
"mov w20, #0xffff",
|
||||
"str w20, [x4, #28]",
|
||||
"mov w21, #0xffff",
|
||||
"stp w20, w21, [x4, #24]",
|
||||
"ubfx x20, x4, #0, #3",
|
||||
"str x20, [x4, #512]"
|
||||
]
|
||||
@ -1533,14 +1479,14 @@
|
||||
]
|
||||
},
|
||||
"xrstor [rax]": {
|
||||
"ExpectedInstructionCount": 166,
|
||||
"ExpectedInstructionCount": 130,
|
||||
"Comment": "GROUP15 0x0F 0xAE /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"sub sp, sp, #0x40 (64)",
|
||||
"ldr x20, [x4, #512]",
|
||||
"ubfx x20, x20, #0, #1",
|
||||
"cbnz x20, #+0x8",
|
||||
"b #+0x84",
|
||||
"b #+0x74",
|
||||
"ldrh w20, [x4]",
|
||||
"strh w20, [x28, #1296]",
|
||||
"ldrh w20, [x4, #2]",
|
||||
@ -1555,14 +1501,10 @@
|
||||
"strb w23, [x28, #1018]",
|
||||
"strb w20, [x28, #1022]",
|
||||
"ldrb w20, [x4, #4]",
|
||||
"ldr q2, [x4, #32]",
|
||||
"ldr q3, [x4, #48]",
|
||||
"ldr q4, [x4, #64]",
|
||||
"ldr q5, [x4, #80]",
|
||||
"ldr q6, [x4, #96]",
|
||||
"ldr q7, [x4, #112]",
|
||||
"ldr q8, [x4, #128]",
|
||||
"ldr q9, [x4, #144]",
|
||||
"ldp q2, q3, [x4, #32]",
|
||||
"ldp q4, q5, [x4, #64]",
|
||||
"ldp q6, q7, [x4, #96]",
|
||||
"ldp q8, q9, [x4, #128]",
|
||||
"strb w20, [x28, #1298]",
|
||||
"str q9, [x28, #1152]",
|
||||
"str q8, [x28, #1136]",
|
||||
@ -1593,23 +1535,15 @@
|
||||
"ldr x20, [x4, #512]",
|
||||
"ubfx x20, x20, #1, #1",
|
||||
"cbnz x20, #+0x8",
|
||||
"b #+0x48",
|
||||
"ldr q16, [x4, #160]",
|
||||
"ldr q17, [x4, #176]",
|
||||
"ldr q18, [x4, #192]",
|
||||
"ldr q19, [x4, #208]",
|
||||
"ldr q20, [x4, #224]",
|
||||
"ldr q21, [x4, #240]",
|
||||
"ldr q22, [x4, #256]",
|
||||
"ldr q23, [x4, #272]",
|
||||
"ldr q24, [x4, #288]",
|
||||
"ldr q25, [x4, #304]",
|
||||
"ldr q26, [x4, #320]",
|
||||
"ldr q27, [x4, #336]",
|
||||
"ldr q28, [x4, #352]",
|
||||
"ldr q29, [x4, #368]",
|
||||
"ldr q30, [x4, #384]",
|
||||
"ldr q31, [x4, #400]",
|
||||
"b #+0x28",
|
||||
"ldp q16, q17, [x4, #160]",
|
||||
"ldp q18, q19, [x4, #192]",
|
||||
"ldp q20, q21, [x4, #224]",
|
||||
"ldp q22, q23, [x4, #256]",
|
||||
"ldp q24, q25, [x4, #288]",
|
||||
"ldp q26, q27, [x4, #320]",
|
||||
"ldp q28, q29, [x4, #352]",
|
||||
"ldp q30, q31, [x4, #384]",
|
||||
"b #+0x44",
|
||||
"movi v31.2d, #0x0",
|
||||
"mov v30.16b, v31.16b",
|
||||
@ -1630,61 +1564,37 @@
|
||||
"ldr x20, [x4, #512]",
|
||||
"ubfx x20, x20, #2, #1",
|
||||
"cbnz x20, #+0x8",
|
||||
"b #+0x98",
|
||||
"ldr q2, [x4, #576]",
|
||||
"ldr q3, [x4, #592]",
|
||||
"ldr q4, [x4, #608]",
|
||||
"ldr q5, [x4, #624]",
|
||||
"ldr q6, [x4, #640]",
|
||||
"ldr q7, [x4, #656]",
|
||||
"ldr q8, [x4, #672]",
|
||||
"ldr q9, [x4, #688]",
|
||||
"ldr q10, [x4, #704]",
|
||||
"ldr q11, [x4, #720]",
|
||||
"ldr q12, [x4, #736]",
|
||||
"ldr q13, [x4, #752]",
|
||||
"ldr q14, [x4, #768]",
|
||||
"ldr q15, [x4, #784]",
|
||||
"b #+0x58",
|
||||
"ldp q2, q3, [x4, #576]",
|
||||
"ldp q4, q5, [x4, #608]",
|
||||
"ldp q6, q7, [x4, #640]",
|
||||
"ldp q8, q9, [x4, #672]",
|
||||
"ldp q10, q11, [x4, #704]",
|
||||
"ldp q12, q13, [x4, #736]",
|
||||
"ldp q14, q15, [x4, #768]",
|
||||
"str q2, [sp]",
|
||||
"ldr q2, [x4, #800]",
|
||||
"str q3, [sp, #32]",
|
||||
"ldr q3, [x4, #816]",
|
||||
"str q3, [x28, #256]",
|
||||
"str q2, [x28, #240]",
|
||||
"str q15, [x28, #224]",
|
||||
"str q14, [x28, #208]",
|
||||
"str q13, [x28, #192]",
|
||||
"str q12, [x28, #176]",
|
||||
"str q11, [x28, #160]",
|
||||
"str q10, [x28, #144]",
|
||||
"str q9, [x28, #128]",
|
||||
"str q8, [x28, #112]",
|
||||
"str q7, [x28, #96]",
|
||||
"str q6, [x28, #80]",
|
||||
"str q5, [x28, #64]",
|
||||
"str q4, [x28, #48]",
|
||||
"ldr q2, [sp, #32]",
|
||||
"str q2, [x28, #32]",
|
||||
"ldp q2, q3, [x4, #800]",
|
||||
"stp q2, q3, [x28, #240]",
|
||||
"stp q14, q15, [x28, #208]",
|
||||
"stp q12, q13, [x28, #176]",
|
||||
"stp q10, q11, [x28, #144]",
|
||||
"stp q8, q9, [x28, #112]",
|
||||
"stp q6, q7, [x28, #80]",
|
||||
"stp q4, q5, [x28, #48]",
|
||||
"ldr q2, [sp]",
|
||||
"str q2, [x28, #16]",
|
||||
"b #+0x48",
|
||||
"ldr q3, [sp, #32]",
|
||||
"stp q2, q3, [x28, #16]",
|
||||
"b #+0x28",
|
||||
"movi v2.2d, #0x0",
|
||||
"str q2, [x28, #256]",
|
||||
"str q2, [x28, #240]",
|
||||
"str q2, [x28, #224]",
|
||||
"str q2, [x28, #208]",
|
||||
"str q2, [x28, #192]",
|
||||
"str q2, [x28, #176]",
|
||||
"str q2, [x28, #160]",
|
||||
"str q2, [x28, #144]",
|
||||
"str q2, [x28, #128]",
|
||||
"str q2, [x28, #112]",
|
||||
"str q2, [x28, #96]",
|
||||
"str q2, [x28, #80]",
|
||||
"str q2, [x28, #64]",
|
||||
"str q2, [x28, #48]",
|
||||
"str q2, [x28, #32]",
|
||||
"str q2, [x28, #16]",
|
||||
"stp q2, q2, [x28, #240]",
|
||||
"stp q2, q2, [x28, #208]",
|
||||
"stp q2, q2, [x28, #176]",
|
||||
"stp q2, q2, [x28, #144]",
|
||||
"stp q2, q2, [x28, #112]",
|
||||
"stp q2, q2, [x28, #80]",
|
||||
"stp q2, q2, [x28, #48]",
|
||||
"stp q2, q2, [x28, #16]",
|
||||
"ldr x20, [x4, #512]",
|
||||
"ubfx x20, x20, #1, #2",
|
||||
"cbnz x20, #+0x8",
|
||||
|
||||
@ -1406,7 +1406,7 @@
|
||||
]
|
||||
},
|
||||
"fxsave [rax]": {
|
||||
"ExpectedInstructionCount": 52,
|
||||
"ExpectedInstructionCount": 39,
|
||||
"Comment": "GROUP15 0x0F 0xAE /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldrh w20, [x28, #1296]",
|
||||
@ -1425,42 +1425,29 @@
|
||||
"ldrb w20, [x28, #1298]",
|
||||
"strb w20, [x4, #4]",
|
||||
"ldr q2, [x28, #1040]",
|
||||
"str q2, [x4, #32]",
|
||||
"ldr q2, [x28, #1056]",
|
||||
"str q2, [x4, #48]",
|
||||
"ldr q3, [x28, #1056]",
|
||||
"stp q2, q3, [x4, #32]",
|
||||
"ldr q2, [x28, #1072]",
|
||||
"str q2, [x4, #64]",
|
||||
"ldr q2, [x28, #1088]",
|
||||
"str q2, [x4, #80]",
|
||||
"ldr q3, [x28, #1088]",
|
||||
"stp q2, q3, [x4, #64]",
|
||||
"ldr q2, [x28, #1104]",
|
||||
"str q2, [x4, #96]",
|
||||
"ldr q2, [x28, #1120]",
|
||||
"str q2, [x4, #112]",
|
||||
"ldr q3, [x28, #1120]",
|
||||
"stp q2, q3, [x4, #96]",
|
||||
"ldr q2, [x28, #1136]",
|
||||
"str q2, [x4, #128]",
|
||||
"ldr q2, [x28, #1152]",
|
||||
"str q2, [x4, #144]",
|
||||
"str q16, [x4, #160]",
|
||||
"str q17, [x4, #176]",
|
||||
"str q18, [x4, #192]",
|
||||
"str q19, [x4, #208]",
|
||||
"str q20, [x4, #224]",
|
||||
"str q21, [x4, #240]",
|
||||
"str q22, [x4, #256]",
|
||||
"str q23, [x4, #272]",
|
||||
"str q24, [x4, #288]",
|
||||
"str q25, [x4, #304]",
|
||||
"str q26, [x4, #320]",
|
||||
"str q27, [x4, #336]",
|
||||
"str q28, [x4, #352]",
|
||||
"str q29, [x4, #368]",
|
||||
"str q30, [x4, #384]",
|
||||
"str q31, [x4, #400]",
|
||||
"ldr q3, [x28, #1152]",
|
||||
"stp q2, q3, [x4, #128]",
|
||||
"stp q16, q17, [x4, #160]",
|
||||
"stp q18, q19, [x4, #192]",
|
||||
"stp q20, q21, [x4, #224]",
|
||||
"stp q22, q23, [x4, #256]",
|
||||
"stp q24, q25, [x4, #288]",
|
||||
"stp q26, q27, [x4, #320]",
|
||||
"stp q28, q29, [x4, #352]",
|
||||
"stp q30, q31, [x4, #384]",
|
||||
"ldr w20, [x28, #940]",
|
||||
"and w20, w20, #0xffc0",
|
||||
"str w20, [x4, #24]",
|
||||
"mov w20, #0xffff",
|
||||
"str w20, [x4, #28]"
|
||||
"mov w21, #0xffff",
|
||||
"stp w20, w21, [x4, #24]"
|
||||
]
|
||||
},
|
||||
"rdfsbase eax": {
|
||||
@ -1478,7 +1465,7 @@
|
||||
]
|
||||
},
|
||||
"fxrstor [rax]": {
|
||||
"ExpectedInstructionCount": 58,
|
||||
"ExpectedInstructionCount": 46,
|
||||
"Comment": "GROUP15 0x0F 0xAE /1",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldrh w20, [x4]",
|
||||
@ -1495,30 +1482,18 @@
|
||||
"strb w23, [x28, #1018]",
|
||||
"strb w20, [x28, #1022]",
|
||||
"ldrb w20, [x4, #4]",
|
||||
"ldr q2, [x4, #32]",
|
||||
"ldr q3, [x4, #48]",
|
||||
"ldr q4, [x4, #64]",
|
||||
"ldr q5, [x4, #80]",
|
||||
"ldr q6, [x4, #96]",
|
||||
"ldr q7, [x4, #112]",
|
||||
"ldr q8, [x4, #128]",
|
||||
"ldr q9, [x4, #144]",
|
||||
"ldr q16, [x4, #160]",
|
||||
"ldr q17, [x4, #176]",
|
||||
"ldr q18, [x4, #192]",
|
||||
"ldr q19, [x4, #208]",
|
||||
"ldr q20, [x4, #224]",
|
||||
"ldr q21, [x4, #240]",
|
||||
"ldr q22, [x4, #256]",
|
||||
"ldr q23, [x4, #272]",
|
||||
"ldr q24, [x4, #288]",
|
||||
"ldr q25, [x4, #304]",
|
||||
"ldr q26, [x4, #320]",
|
||||
"ldr q27, [x4, #336]",
|
||||
"ldr q28, [x4, #352]",
|
||||
"ldr q29, [x4, #368]",
|
||||
"ldr q30, [x4, #384]",
|
||||
"ldr q31, [x4, #400]",
|
||||
"ldp q2, q3, [x4, #32]",
|
||||
"ldp q4, q5, [x4, #64]",
|
||||
"ldp q6, q7, [x4, #96]",
|
||||
"ldp q8, q9, [x4, #128]",
|
||||
"ldp q16, q17, [x4, #160]",
|
||||
"ldp q18, q19, [x4, #192]",
|
||||
"ldp q20, q21, [x4, #224]",
|
||||
"ldp q22, q23, [x4, #256]",
|
||||
"ldp q24, q25, [x4, #288]",
|
||||
"ldp q26, q27, [x4, #320]",
|
||||
"ldp q28, q29, [x4, #352]",
|
||||
"ldp q30, q31, [x4, #384]",
|
||||
"ldr w21, [x4, #24]",
|
||||
"and w21, w21, #0xffc0",
|
||||
"str w21, [x28, #940]",
|
||||
@ -1612,12 +1587,12 @@
|
||||
]
|
||||
},
|
||||
"xsave [rax]": {
|
||||
"ExpectedInstructionCount": 98,
|
||||
"ExpectedInstructionCount": 69,
|
||||
"Comment": "GROUP15 0x0F 0xAE /4",
|
||||
"ExpectedArm64ASM": [
|
||||
"ubfx x20, x4, #0, #1",
|
||||
"cbnz x20, #+0x8",
|
||||
"b #+0x80",
|
||||
"b #+0x70",
|
||||
"ldrh w20, [x28, #1296]",
|
||||
"strh w20, [x4]",
|
||||
"ldrb w20, [x28, #1019]",
|
||||
@ -1634,83 +1609,54 @@
|
||||
"ldrb w20, [x28, #1298]",
|
||||
"strb w20, [x4, #4]",
|
||||
"ldr q2, [x28, #1040]",
|
||||
"str q2, [x4, #32]",
|
||||
"ldr q2, [x28, #1056]",
|
||||
"str q2, [x4, #48]",
|
||||
"ldr q3, [x28, #1056]",
|
||||
"stp q2, q3, [x4, #32]",
|
||||
"ldr q2, [x28, #1072]",
|
||||
"str q2, [x4, #64]",
|
||||
"ldr q2, [x28, #1088]",
|
||||
"str q2, [x4, #80]",
|
||||
"ldr q3, [x28, #1088]",
|
||||
"stp q2, q3, [x4, #64]",
|
||||
"ldr q2, [x28, #1104]",
|
||||
"str q2, [x4, #96]",
|
||||
"ldr q2, [x28, #1120]",
|
||||
"str q2, [x4, #112]",
|
||||
"ldr q3, [x28, #1120]",
|
||||
"stp q2, q3, [x4, #96]",
|
||||
"ldr q2, [x28, #1136]",
|
||||
"str q2, [x4, #128]",
|
||||
"ldr q2, [x28, #1152]",
|
||||
"str q2, [x4, #144]",
|
||||
"ldr q3, [x28, #1152]",
|
||||
"stp q2, q3, [x4, #128]",
|
||||
"ubfx x20, x4, #1, #1",
|
||||
"cbnz x20, #+0x8",
|
||||
"b #+0x44",
|
||||
"str q16, [x4, #160]",
|
||||
"str q17, [x4, #176]",
|
||||
"str q18, [x4, #192]",
|
||||
"str q19, [x4, #208]",
|
||||
"str q20, [x4, #224]",
|
||||
"str q21, [x4, #240]",
|
||||
"str q22, [x4, #256]",
|
||||
"str q23, [x4, #272]",
|
||||
"str q24, [x4, #288]",
|
||||
"str q25, [x4, #304]",
|
||||
"str q26, [x4, #320]",
|
||||
"str q27, [x4, #336]",
|
||||
"str q28, [x4, #352]",
|
||||
"str q29, [x4, #368]",
|
||||
"str q30, [x4, #384]",
|
||||
"str q31, [x4, #400]",
|
||||
"b #+0x24",
|
||||
"stp q16, q17, [x4, #160]",
|
||||
"stp q18, q19, [x4, #192]",
|
||||
"stp q20, q21, [x4, #224]",
|
||||
"stp q22, q23, [x4, #256]",
|
||||
"stp q24, q25, [x4, #288]",
|
||||
"stp q26, q27, [x4, #320]",
|
||||
"stp q28, q29, [x4, #352]",
|
||||
"stp q30, q31, [x4, #384]",
|
||||
"ubfx x20, x4, #2, #1",
|
||||
"cbnz x20, #+0x8",
|
||||
"b #+0x84",
|
||||
"ldr q2, [x28, #16]",
|
||||
"str q2, [x4, #576]",
|
||||
"ldr q2, [x28, #32]",
|
||||
"str q2, [x4, #592]",
|
||||
"ldr q2, [x28, #48]",
|
||||
"str q2, [x4, #608]",
|
||||
"ldr q2, [x28, #64]",
|
||||
"str q2, [x4, #624]",
|
||||
"ldr q2, [x28, #80]",
|
||||
"str q2, [x4, #640]",
|
||||
"ldr q2, [x28, #96]",
|
||||
"str q2, [x4, #656]",
|
||||
"ldr q2, [x28, #112]",
|
||||
"str q2, [x4, #672]",
|
||||
"ldr q2, [x28, #128]",
|
||||
"str q2, [x4, #688]",
|
||||
"ldr q2, [x28, #144]",
|
||||
"str q2, [x4, #704]",
|
||||
"ldr q2, [x28, #160]",
|
||||
"str q2, [x4, #720]",
|
||||
"ldr q2, [x28, #176]",
|
||||
"str q2, [x4, #736]",
|
||||
"ldr q2, [x28, #192]",
|
||||
"str q2, [x4, #752]",
|
||||
"ldr q2, [x28, #208]",
|
||||
"str q2, [x4, #768]",
|
||||
"ldr q2, [x28, #224]",
|
||||
"str q2, [x4, #784]",
|
||||
"ldr q2, [x28, #240]",
|
||||
"str q2, [x4, #800]",
|
||||
"ldr q2, [x28, #256]",
|
||||
"str q2, [x4, #816]",
|
||||
"b #+0x44",
|
||||
"ldp q2, q3, [x28, #16]",
|
||||
"stp q2, q3, [x4, #576]",
|
||||
"ldp q2, q3, [x28, #48]",
|
||||
"stp q2, q3, [x4, #608]",
|
||||
"ldp q2, q3, [x28, #80]",
|
||||
"stp q2, q3, [x4, #640]",
|
||||
"ldp q2, q3, [x28, #112]",
|
||||
"stp q2, q3, [x4, #672]",
|
||||
"ldp q2, q3, [x28, #144]",
|
||||
"stp q2, q3, [x4, #704]",
|
||||
"ldp q2, q3, [x28, #176]",
|
||||
"stp q2, q3, [x4, #736]",
|
||||
"ldp q2, q3, [x28, #208]",
|
||||
"stp q2, q3, [x4, #768]",
|
||||
"ldp q2, q3, [x28, #240]",
|
||||
"stp q2, q3, [x4, #800]",
|
||||
"ubfx x20, x4, #1, #2",
|
||||
"cbnz x20, #+0x8",
|
||||
"b #+0x18",
|
||||
"b #+0x14",
|
||||
"ldr w20, [x28, #940]",
|
||||
"and w20, w20, #0xffc0",
|
||||
"str w20, [x4, #24]",
|
||||
"mov w20, #0xffff",
|
||||
"str w20, [x4, #28]",
|
||||
"mov w21, #0xffff",
|
||||
"stp w20, w21, [x4, #24]",
|
||||
"ubfx x20, x4, #0, #3",
|
||||
"str x20, [x4, #512]"
|
||||
]
|
||||
@ -1723,14 +1669,14 @@
|
||||
]
|
||||
},
|
||||
"xrstor [rax]": {
|
||||
"ExpectedInstructionCount": 166,
|
||||
"ExpectedInstructionCount": 130,
|
||||
"Comment": "GROUP15 0x0F 0xAE /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"sub sp, sp, #0x40 (64)",
|
||||
"ldr x20, [x4, #512]",
|
||||
"ubfx x20, x20, #0, #1",
|
||||
"cbnz x20, #+0x8",
|
||||
"b #+0x84",
|
||||
"b #+0x74",
|
||||
"ldrh w20, [x4]",
|
||||
"strh w20, [x28, #1296]",
|
||||
"ldrh w20, [x4, #2]",
|
||||
@ -1745,14 +1691,10 @@
|
||||
"strb w23, [x28, #1018]",
|
||||
"strb w20, [x28, #1022]",
|
||||
"ldrb w20, [x4, #4]",
|
||||
"ldr q2, [x4, #32]",
|
||||
"ldr q3, [x4, #48]",
|
||||
"ldr q4, [x4, #64]",
|
||||
"ldr q5, [x4, #80]",
|
||||
"ldr q6, [x4, #96]",
|
||||
"ldr q7, [x4, #112]",
|
||||
"ldr q8, [x4, #128]",
|
||||
"ldr q9, [x4, #144]",
|
||||
"ldp q2, q3, [x4, #32]",
|
||||
"ldp q4, q5, [x4, #64]",
|
||||
"ldp q6, q7, [x4, #96]",
|
||||
"ldp q8, q9, [x4, #128]",
|
||||
"strb w20, [x28, #1298]",
|
||||
"str q9, [x28, #1152]",
|
||||
"str q8, [x28, #1136]",
|
||||
@ -1783,23 +1725,15 @@
|
||||
"ldr x20, [x4, #512]",
|
||||
"ubfx x20, x20, #1, #1",
|
||||
"cbnz x20, #+0x8",
|
||||
"b #+0x48",
|
||||
"ldr q16, [x4, #160]",
|
||||
"ldr q17, [x4, #176]",
|
||||
"ldr q18, [x4, #192]",
|
||||
"ldr q19, [x4, #208]",
|
||||
"ldr q20, [x4, #224]",
|
||||
"ldr q21, [x4, #240]",
|
||||
"ldr q22, [x4, #256]",
|
||||
"ldr q23, [x4, #272]",
|
||||
"ldr q24, [x4, #288]",
|
||||
"ldr q25, [x4, #304]",
|
||||
"ldr q26, [x4, #320]",
|
||||
"ldr q27, [x4, #336]",
|
||||
"ldr q28, [x4, #352]",
|
||||
"ldr q29, [x4, #368]",
|
||||
"ldr q30, [x4, #384]",
|
||||
"ldr q31, [x4, #400]",
|
||||
"b #+0x28",
|
||||
"ldp q16, q17, [x4, #160]",
|
||||
"ldp q18, q19, [x4, #192]",
|
||||
"ldp q20, q21, [x4, #224]",
|
||||
"ldp q22, q23, [x4, #256]",
|
||||
"ldp q24, q25, [x4, #288]",
|
||||
"ldp q26, q27, [x4, #320]",
|
||||
"ldp q28, q29, [x4, #352]",
|
||||
"ldp q30, q31, [x4, #384]",
|
||||
"b #+0x44",
|
||||
"movi v31.2d, #0x0",
|
||||
"mov v30.16b, v31.16b",
|
||||
@ -1820,61 +1754,37 @@
|
||||
"ldr x20, [x4, #512]",
|
||||
"ubfx x20, x20, #2, #1",
|
||||
"cbnz x20, #+0x8",
|
||||
"b #+0x98",
|
||||
"ldr q2, [x4, #576]",
|
||||
"ldr q3, [x4, #592]",
|
||||
"ldr q4, [x4, #608]",
|
||||
"ldr q5, [x4, #624]",
|
||||
"ldr q6, [x4, #640]",
|
||||
"ldr q7, [x4, #656]",
|
||||
"ldr q8, [x4, #672]",
|
||||
"ldr q9, [x4, #688]",
|
||||
"ldr q10, [x4, #704]",
|
||||
"ldr q11, [x4, #720]",
|
||||
"ldr q12, [x4, #736]",
|
||||
"ldr q13, [x4, #752]",
|
||||
"ldr q14, [x4, #768]",
|
||||
"ldr q15, [x4, #784]",
|
||||
"b #+0x58",
|
||||
"ldp q2, q3, [x4, #576]",
|
||||
"ldp q4, q5, [x4, #608]",
|
||||
"ldp q6, q7, [x4, #640]",
|
||||
"ldp q8, q9, [x4, #672]",
|
||||
"ldp q10, q11, [x4, #704]",
|
||||
"ldp q12, q13, [x4, #736]",
|
||||
"ldp q14, q15, [x4, #768]",
|
||||
"str q2, [sp]",
|
||||
"ldr q2, [x4, #800]",
|
||||
"str q3, [sp, #32]",
|
||||
"ldr q3, [x4, #816]",
|
||||
"str q3, [x28, #256]",
|
||||
"str q2, [x28, #240]",
|
||||
"str q15, [x28, #224]",
|
||||
"str q14, [x28, #208]",
|
||||
"str q13, [x28, #192]",
|
||||
"str q12, [x28, #176]",
|
||||
"str q11, [x28, #160]",
|
||||
"str q10, [x28, #144]",
|
||||
"str q9, [x28, #128]",
|
||||
"str q8, [x28, #112]",
|
||||
"str q7, [x28, #96]",
|
||||
"str q6, [x28, #80]",
|
||||
"str q5, [x28, #64]",
|
||||
"str q4, [x28, #48]",
|
||||
"ldr q2, [sp, #32]",
|
||||
"str q2, [x28, #32]",
|
||||
"ldp q2, q3, [x4, #800]",
|
||||
"stp q2, q3, [x28, #240]",
|
||||
"stp q14, q15, [x28, #208]",
|
||||
"stp q12, q13, [x28, #176]",
|
||||
"stp q10, q11, [x28, #144]",
|
||||
"stp q8, q9, [x28, #112]",
|
||||
"stp q6, q7, [x28, #80]",
|
||||
"stp q4, q5, [x28, #48]",
|
||||
"ldr q2, [sp]",
|
||||
"str q2, [x28, #16]",
|
||||
"b #+0x48",
|
||||
"ldr q3, [sp, #32]",
|
||||
"stp q2, q3, [x28, #16]",
|
||||
"b #+0x28",
|
||||
"movi v2.2d, #0x0",
|
||||
"str q2, [x28, #256]",
|
||||
"str q2, [x28, #240]",
|
||||
"str q2, [x28, #224]",
|
||||
"str q2, [x28, #208]",
|
||||
"str q2, [x28, #192]",
|
||||
"str q2, [x28, #176]",
|
||||
"str q2, [x28, #160]",
|
||||
"str q2, [x28, #144]",
|
||||
"str q2, [x28, #128]",
|
||||
"str q2, [x28, #112]",
|
||||
"str q2, [x28, #96]",
|
||||
"str q2, [x28, #80]",
|
||||
"str q2, [x28, #64]",
|
||||
"str q2, [x28, #48]",
|
||||
"str q2, [x28, #32]",
|
||||
"str q2, [x28, #16]",
|
||||
"stp q2, q2, [x28, #240]",
|
||||
"stp q2, q2, [x28, #208]",
|
||||
"stp q2, q2, [x28, #176]",
|
||||
"stp q2, q2, [x28, #144]",
|
||||
"stp q2, q2, [x28, #112]",
|
||||
"stp q2, q2, [x28, #80]",
|
||||
"stp q2, q2, [x28, #48]",
|
||||
"stp q2, q2, [x28, #16]",
|
||||
"ldr x20, [x4, #512]",
|
||||
"ubfx x20, x20, #1, #2",
|
||||
"cbnz x20, #+0x8",
|
||||
|
||||
Loading…
Reference in New Issue
Block a user