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https://github.com/FEX-Emu/FEX.git
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IR: track tied sources
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig
parent
35ec54f920
commit
7790d7a0b7
@ -55,6 +55,7 @@ class OpDefinition:
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DynamicDispatch: bool
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JITDispatch: bool
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JITDispatchOverride: str
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TiedSource: int
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Arguments: list
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EmitValidation: list
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Desc: list
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@ -77,6 +78,7 @@ class OpDefinition:
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self.DynamicDispatch = False
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self.JITDispatch = True
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self.JITDispatchOverride = None
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self.TiedSource = -1
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self.Arguments = []
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self.EmitValidation = []
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self.Desc = []
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@ -248,6 +250,9 @@ def parse_ops(ops):
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if "JITDispatchOverride" in op_val:
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OpDef.JITDispatchOverride = op_val["JITDispatchOverride"]
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if "TiedSource" in op_val:
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OpDef.TiedSource = op_val["TiedSource"]
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# Do some fixups of the data here
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if len(OpDef.EmitValidation) != 0:
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for i in range(len(OpDef.EmitValidation)):
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@ -372,13 +377,30 @@ def print_ir_sizes():
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output_file.write("[[maybe_unused, nodiscard]] static size_t GetSize(IROps Op) { return IRSizes[Op]; }\n\n")
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output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] std::string_view const& GetName(IROps Op);\n")
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output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] uint8_t GetArgs(IROps Op);\n")
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output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] uint8_t GetRAArgs(IROps Op);\n")
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output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] FEXCore::IR::RegisterClassType GetRegClass(IROps Op);\n\n")
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output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] bool HasSideEffects(IROps Op);\n")
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output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] bool ImplicitFlagClobber(IROps Op);\n")
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output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] bool GetHasDest(IROps Op);\n")
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output_file.write(
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'[[nodiscard, gnu::const, gnu::visibility("default")]] std::string_view const& GetName(IROps Op);\n'
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)
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output_file.write(
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'[[nodiscard, gnu::const, gnu::visibility("default")]] uint8_t GetArgs(IROps Op);\n'
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)
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output_file.write(
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'[[nodiscard, gnu::const, gnu::visibility("default")]] uint8_t GetRAArgs(IROps Op);\n'
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)
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output_file.write(
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'[[nodiscard, gnu::const, gnu::visibility("default")]] FEXCore::IR::RegisterClassType GetRegClass(IROps Op);\n\n'
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)
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output_file.write(
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'[[nodiscard, gnu::const, gnu::visibility("default")]] bool HasSideEffects(IROps Op);\n'
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)
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output_file.write(
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'[[nodiscard, gnu::const, gnu::visibility("default")]] bool ImplicitFlagClobber(IROps Op);\n'
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)
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output_file.write(
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'[[nodiscard, gnu::const, gnu::visibility("default")]] bool GetHasDest(IROps Op);\n'
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)
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output_file.write(
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'[[nodiscard, gnu::const, gnu::visibility("default")]] int8_t TiedSource(IROps Op);\n'
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)
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output_file.write("#undef IROP_SIZES\n")
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output_file.write("#endif\n\n")
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@ -471,15 +493,25 @@ def print_ir_getraargs():
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def print_ir_hassideeffects():
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output_file.write("#ifdef IROP_HASSIDEEFFECTS_IMPL\n")
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for array, prop in [("SideEffects", "HasSideEffects"),
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("ImplicitFlagClobbers", "ImplicitFlagClobber")]:
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output_file.write(f"constexpr std::array<uint8_t, OP_LAST + 1> {array} = {{\n")
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for array, prop, T in [
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("SideEffects", "HasSideEffects", "bool"),
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("ImplicitFlagClobbers", "ImplicitFlagClobber", "bool"),
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("TiedSources", "TiedSource", "int8_t"),
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]:
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output_file.write(
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f"constexpr std::array<{'uint8_t' if T == 'bool' else T}, OP_LAST + 1> {array} = {{\n"
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)
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for op in IROps:
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output_file.write("\t{},\n".format(("true" if getattr(op, prop) else "false")))
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if T == "bool":
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output_file.write(
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"\t{},\n".format(("true" if getattr(op, prop) else "false"))
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)
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else:
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output_file.write(f"\t{getattr(op, prop)},\n")
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output_file.write("};\n\n")
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output_file.write(f"bool {prop}(IROps Op) {{\n")
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output_file.write(f"{T} {prop}(IROps Op) {{\n")
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output_file.write(f" return {array}[Op];\n")
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output_file.write("}\n")
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@ -549,6 +549,7 @@
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"Desc": ["Does a memory load to a single element of a vector.",
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"Leaves the rest of the vector's data intact.",
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"Matches arm64 ld1 semantics"],
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"TiedSource": 0,
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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},
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@ -570,6 +571,7 @@
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"The address is decremented by the value size while.",
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"The return value size is the size of the current operating mode"
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],
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"TiedSource": 1,
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"HasSideEffects": true,
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"DestSize": "Size"
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},
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@ -1195,6 +1197,7 @@
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"Desc": ["Integer binary and"
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],
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"DestSize": "Size",
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"TiedSource": 0,
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"HasSideEffects": true
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},
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"GPR = Andn OpSize:#Size, GPR:$Src1, GPR:$Src2": {
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@ -1335,6 +1338,7 @@
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"The bitfield is copied in to Dest[(Width + lsb):lsb]"
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],
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"DestSize": "Size",
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"TiedSource": 0,
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"EmitValidation": [
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"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
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]
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@ -1346,6 +1350,7 @@
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"The bitfield is copied in to Dest[Width:0]"
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],
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"DestSize": "Size",
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"TiedSource": 0,
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"EmitValidation": [
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"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
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]
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@ -1776,29 +1781,35 @@
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"NumElements": "RegisterSize / ElementSize"
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},
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"FPR = VShlI u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, u8:$BitShift": {
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"TiedSource": 0,
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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},
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"FPR = VUShrI u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, u8:$BitShift": {
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"TiedSource": 0,
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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},
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"FPR = VUShraI u8:#RegisterSize, u8:#ElementSize, FPR:$DestVector, FPR:$Vector, u8:$BitShift": {
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"TiedSource": 0,
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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},
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"FPR = VSShrI u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, u8:$BitShift": {
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"TiedSource": 0,
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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},
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"FPR = VUShrNI u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, u8:$BitShift": {
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"TiedSource": 0,
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"Desc": "Unsigned shifts right each element and then narrows to the next lower element size",
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / (ElementSize >> 1)"
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},
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"FPR = VUShrNI2 u8:#RegisterSize, u8:#ElementSize, FPR:$VectorLower, FPR:$VectorUpper, u8:$BitShift": {
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"TiedSource": 0,
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"Desc": ["Unsigned shifts right each element and then narrows to the next lower element size",
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"Inserts results in to the high elements of the first argument"
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],
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@ -1830,10 +1841,12 @@
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"NumElements": "RegisterSize / (ElementSize << 1)"
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},
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"FPR = VSQXTN u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
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"TiedSource": 0,
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / (ElementSize >> 1)"
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},
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"FPR = VSQXTN2 u8:#RegisterSize, u8:#ElementSize, FPR:$VectorLower, FPR:$VectorUpper": {
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"TiedSource": 0,
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / (ElementSize >> 1)"
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},
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@ -1861,6 +1874,7 @@
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"Desc": ["Signed rounding shift right by immediate",
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"Exactly matching Arm64 srshr semantics"
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],
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"TiedSource": 0,
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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},
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@ -1868,6 +1882,7 @@
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"Desc": ["Signed satuating shift left by immediate",
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"Exactly matching Arm64 sqshl semantics"
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],
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"TiedSource": 0,
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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},
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@ -2076,42 +2091,52 @@
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"NumElements": "RegisterSize / (ElementSize << 1)"
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},
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"FPR = VUShl u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, FPR:$ShiftVector, i1:$RangeCheck": {
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"TiedSource": 0,
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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},
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"FPR = VUShr u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, FPR:$ShiftVector, i1:$RangeCheck": {
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"TiedSource": 0,
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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},
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"FPR = VSShr u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, FPR:$ShiftVector, i1:$RangeCheck": {
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"TiedSource": 0,
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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},
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"FPR = VUShlS u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, FPR:$ShiftScalar": {
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"TiedSource": 0,
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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},
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"FPR = VUShrS u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, FPR:$ShiftScalar": {
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"TiedSource": 0,
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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},
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"FPR = VSShrS u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, FPR:$ShiftScalar": {
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"TiedSource": 0,
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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},
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"FPR = VUShrSWide u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, FPR:$ShiftScalar": {
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"TiedSource": 0,
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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},
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"FPR = VSShrSWide u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, FPR:$ShiftScalar": {
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"TiedSource": 0,
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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},
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"FPR = VUShlSWide u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, FPR:$ShiftScalar": {
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"TiedSource": 0,
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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},
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"FPR = VInsElement u8:#RegisterSize, u8:#ElementSize, u8:$DestIdx, u8:$SrcIdx, FPR:$DestVector, FPR:$SrcVector": {
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"TiedSource": 0,
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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},
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@ -2198,6 +2223,7 @@
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"Table is always treated as a 128bit register",
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"Indices matches destination size. Either 64bit or 128bit"
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],
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"TiedSource": 0,
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"DestSize": "RegisterSize"
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},
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"FPR = VBSL u8:#RegisterSize, FPR:$VectorMask, FPR:$VectorTrue, FPR:$VectorFalse": {
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