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Merge pull request #19 from Sonicadvance1/psrl_family

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Implements PSRL{W,D,Q} instruction family
This commit is contained in:
Ryan Houdek 2020-03-13 15:51:58 -07:00 committed by GitHub
commit 78bcf3960d
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 203 additions and 6 deletions
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19
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp vendored
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@ -3857,15 +3857,23 @@ void OpDispatchBuilder::INTOp(OpcodeArgs) {
}
}
template<size_t ElementSize, uint32_t SrcIndex>
void OpDispatchBuilder::PSRLD(OpcodeArgs) {
template<size_t ElementSize, bool Scalar, uint32_t SrcIndex>
void OpDispatchBuilder::PSRLDOp(OpcodeArgs) {
OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[SrcIndex], Op->Flags, -1);
OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
auto Size = GetSrcSize(Op);
auto Shift = _VUShr(Size, ElementSize, Dest, Src);
StoreResult(FPRClass, Op, Shift, -1);
OrderedNode *Result{};
if (Scalar) {
Result = _VUShrS(Size, ElementSize, Dest, Src);
}
else {
Result = _VUShr(Size, ElementSize, Dest, Src);
}
StoreResult(FPRClass, Op, Result, -1);
}
template<size_t ElementSize>
@ -4814,6 +4822,9 @@ void InstallOpcodeHandlers() {
{0xC4, 1, &OpDispatchBuilder::PINSROp<2>},
{0xC6, 1, &OpDispatchBuilder::SHUFOp<8>},
{0xD1, 1, &OpDispatchBuilder::PSRLDOp<2, true, 0>},
{0xD2, 1, &OpDispatchBuilder::PSRLDOp<4, true, 0>},
{0xD3, 1, &OpDispatchBuilder::PSRLDOp<8, true, 0>},
{0xD4, 1, &OpDispatchBuilder::PADDQOp<8>},
// XXX: Causes LLVM to crash if commented out?
{0xD6, 1, &OpDispatchBuilder::MOVQOp},

4
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h vendored
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@ -216,8 +216,8 @@ public:
template<size_t ElementSize>
void PCMPGTOp(OpcodeArgs);
void MOVDOp(OpcodeArgs);
template<size_t ElementSize, uint32_t SrcIndex>
void PSRLD(OpcodeArgs);
template<size_t ElementSize, bool Scalar, uint32_t SrcIndex>
void PSRLDOp(OpcodeArgs);
template<size_t ElementSize>
void PSRLI(OpcodeArgs);
template<size_t ElementSize>

63
unittests/ASM/OpSize/66_D1.asm Normal file
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@ -0,0 +1,63 @@
%ifdef CONFIG
{
"RegData": {
"XMM0": ["0x20A121A222A323A4", "0x28A929AA2AAB2BAC"],
"XMM1": ["0x0041004300450047", "0x0051005300550057"],
"XMM2": ["0x0", "0x0"],
"XMM3": ["0x0", "0x0"],
"XMM4": ["0x0", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x1
mov [rdx + 8 * 2], rax
mov rax, 0x0
mov [rdx + 8 * 3], rax
mov rax, 0x8
mov [rdx + 8 * 4], rax
mov rax, 0x0
mov [rdx + 8 * 5], rax
; Will Zero
mov rax, 0x10
mov [rdx + 8 * 6], rax
mov rax, 0x0
mov [rdx + 8 * 7], rax
; Will Zero
mov rax, 0x20
mov [rdx + 8 * 8], rax
mov rax, 0x0
mov [rdx + 8 * 9], rax
; Will Zero
mov rax, 0x40
mov [rdx + 8 * 10], rax
mov rax, 0x0
mov [rdx + 8 * 11], rax
movapd xmm0, [rdx + 8 * 0]
movapd xmm1, [rdx + 8 * 0]
movapd xmm2, [rdx + 8 * 0]
movapd xmm3, [rdx + 8 * 0]
movapd xmm4, [rdx + 8 * 0]
psrlw xmm0, [rdx + 8 * 2]
psrlw xmm1, [rdx + 8 * 4]
psrlw xmm2, [rdx + 8 * 6]
psrlw xmm3, [rdx + 8 * 8]
psrlw xmm4, [rdx + 8 * 10]
hlt

62
unittests/ASM/OpSize/66_D2.asm Normal file
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@ -0,0 +1,62 @@
%ifdef CONFIG
{
"RegData": {
"XMM0": ["0x20A121A222A323A4", "0x28A929AA2AAB2BAC"],
"XMM1": ["0x0041424300454647", "0x0051525300555657"],
"XMM2": ["0x0000414200004546", "0x0000515200005556"],
"XMM3": ["0x0", "0x0"],
"XMM4": ["0x0", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x1
mov [rdx + 8 * 2], rax
mov rax, 0x0
mov [rdx + 8 * 3], rax
mov rax, 0x8
mov [rdx + 8 * 4], rax
mov rax, 0x0
mov [rdx + 8 * 5], rax
mov rax, 0x10
mov [rdx + 8 * 6], rax
mov rax, 0x0
mov [rdx + 8 * 7], rax
; Will Zero
mov rax, 0x20
mov [rdx + 8 * 8], rax
mov rax, 0x0
mov [rdx + 8 * 9], rax
; Will Zero
mov rax, 0x40
mov [rdx + 8 * 10], rax
mov rax, 0x0
mov [rdx + 8 * 11], rax
movapd xmm0, [rdx + 8 * 0]
movapd xmm1, [rdx + 8 * 0]
movapd xmm2, [rdx + 8 * 0]
movapd xmm3, [rdx + 8 * 0]
movapd xmm4, [rdx + 8 * 0]
psrld xmm0, [rdx + 8 * 2]
psrld xmm1, [rdx + 8 * 4]
psrld xmm2, [rdx + 8 * 6]
psrld xmm3, [rdx + 8 * 8]
psrld xmm4, [rdx + 8 * 10]
hlt

61
unittests/ASM/OpSize/66_D3.asm Normal file
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@ -0,0 +1,61 @@
%ifdef CONFIG
{
"RegData": {
"XMM0": ["0x20A121A222A323A4", "0x28A929AA2AAB2BAC"],
"XMM1": ["0x0041424344454647", "0x0051525354555657"],
"XMM2": ["0x0000414243444546", "0x0000515253545556"],
"XMM3": ["0x0000000041424344", "0x0000000051525354"],
"XMM4": ["0x0", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x1
mov [rdx + 8 * 2], rax
mov rax, 0x0
mov [rdx + 8 * 3], rax
mov rax, 0x8
mov [rdx + 8 * 4], rax
mov rax, 0x0
mov [rdx + 8 * 5], rax
mov rax, 0x10
mov [rdx + 8 * 6], rax
mov rax, 0x0
mov [rdx + 8 * 7], rax
mov rax, 0x20
mov [rdx + 8 * 8], rax
mov rax, 0x0
mov [rdx + 8 * 9], rax
; Will Zero
mov rax, 0x40
mov [rdx + 8 * 10], rax
mov rax, 0x0
mov [rdx + 8 * 11], rax
movapd xmm0, [rdx + 8 * 0]
movapd xmm1, [rdx + 8 * 0]
movapd xmm2, [rdx + 8 * 0]
movapd xmm3, [rdx + 8 * 0]
movapd xmm4, [rdx + 8 * 0]
psrlq xmm0, [rdx + 8 * 2]
psrlq xmm1, [rdx + 8 * 4]
psrlq xmm2, [rdx + 8 * 6]
psrlq xmm3, [rdx + 8 * 8]
psrlq xmm4, [rdx + 8 * 10]
hlt