mirror of
https://github.com/FEX-Emu/FEX.git
synced 2025-02-23 16:23:10 +00:00
Fixes 16bit ModRM rm decoding
When we are running in 32bit mode then it is possible to have an instruction's modrm working as 16bit mode. All one needs to do is prefix the instruction with an address size override
This commit is contained in:
Ryan Houdek
parent
ee8dfb8fc5
commit
7ee6b68d03
203
External/FEXCore/Source/Interface/Core/Frontend.cpp
vendored
203
External/FEXCore/Source/Interface/Core/Frontend.cpp
vendored
@ -176,8 +176,12 @@ void Decoder::DecodeModRM(uint8_t *Displacement, FEXCore::X86Tables::ModRMDecode
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}
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bool Decoder::DecodeSIB(uint8_t *Displacement, FEXCore::X86Tables::ModRMDecoded ModRM) {
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const bool Has16BitAddressing = !CTX->Config.Is64BitMode &&
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DecodeInst->Flags & DecodeFlags::FLAG_ADDRESS_SIZE;
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bool HasSIB = ((ModRM.mod != 0b11) &&
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(ModRM.rm == 0b100));
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(ModRM.rm == 0b100)) &&
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!Has16BitAddressing;
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if (HasSIB) {
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FEXCore::X86Tables::SIBDecoded SIB;
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@ -212,6 +216,146 @@ bool Decoder::DecodeSIB(uint8_t *Displacement, FEXCore::X86Tables::ModRMDecoded
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return HasSIB;
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}
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size_t Decoder::DecodeModRM_16(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM, uint8_t Displacement) {
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// 16bit modrm behaves similar to SIB but encoded directly in modrm
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// mod != 0b11 case
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// RM | Result
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// ===============
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// 0b000 | [BX + SI]
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// 0b001 | [BX + DI]
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// 0b010 | [BP + SI]
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// 0b011 | [BP + DI]
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// 0b100 | [SI]
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// 0b101 | [DI]
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// 0b110 | {[BP], disp16}
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// 0b111 | [BX]
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// if mod = 0b00
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// 0b110 = disp16
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// if mod = 0b01
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// All encodings gain 8bit displacement
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// 0b110 = [BP] + disp8
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// if mod = 0b10
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// All encodings gain 16bit displacement
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// 0b110 = [BP] + disp16
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uint32_t Literal{};
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uint8_t DisplacementSize{};
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if ((ModRM.mod == 0 && ModRM.rm == 0b110) ||
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ModRM.mod == 0b10) {
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DisplacementSize = 2;
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}
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else if (ModRM.mod == 0b01) {
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DisplacementSize = 1;
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}
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if (DisplacementSize) {
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Literal = ReadData(DisplacementSize);
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if (DisplacementSize == 1) {
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Literal = static_cast<int8_t>(Literal);
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}
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}
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Operand->TypeSIB.Type = DecodedOperand::TYPE_SIB;
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Operand->TypeSIB.Scale = 1;
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Operand->TypeSIB.Offset = Literal;
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// Only called when ModRM.mod != 0b11
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struct Encodings {
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uint8_t Base;
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uint8_t Index;
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};
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constexpr static std::array<Encodings, 24> Lookup = {{
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// Mod = 0b00
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{FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RSI},
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{FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RDI},
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{FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RSI},
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{FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RDI},
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{FEXCore::X86State::REG_RSI, 255},
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{FEXCore::X86State::REG_RDI, 255},
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{255, 255},
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{FEXCore::X86State::REG_RBX, 255},
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// Mod = 0b01
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{FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RSI},
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{FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RDI},
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{FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RSI},
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{FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RDI},
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{FEXCore::X86State::REG_RSI, 255},
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{FEXCore::X86State::REG_RDI, 255},
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{FEXCore::X86State::REG_RBP, 255},
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{FEXCore::X86State::REG_RBX, 255},
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// Mod = 0b10
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{FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RSI},
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{FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RDI},
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{FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RSI},
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{FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RDI},
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{FEXCore::X86State::REG_RSI, 255},
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{FEXCore::X86State::REG_RDI, 255},
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{FEXCore::X86State::REG_RBP, 255},
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{FEXCore::X86State::REG_RBX, 255},
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}};
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uint8_t LookupIndex = ModRM.mod << 3 | ModRM.rm;
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auto it = Lookup[LookupIndex];
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Operand->TypeSIB.Base = it.Base;
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Operand->TypeSIB.Index = it.Index;
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return DisplacementSize;
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}
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size_t Decoder::DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM, uint8_t Displacement) {
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if (DecodeInst->DecodedSIB) {
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// SIB
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FEXCore::X86Tables::SIBDecoded SIB;
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SIB.Hex = DecodeInst->SIB;
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Operand->TypeSIB.Type = DecodedOperand::TYPE_SIB;
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Operand->TypeSIB.Scale = 1 << SIB.scale;
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// The invalid encoding types are described at Table 1-12. "promoted nsigned is always non-zero"
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Operand->TypeSIB.Index = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_X ? 1 : 0, SIB.index, false, false, false, false, 0b100);
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Operand->TypeSIB.Base = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, SIB.base, false, false, false, false, ModRM.mod == 0 ? 0b101 : 16);
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uint64_t Literal {0};
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LogMan::Throw::A(Displacement <= 4, "Number of bytes should be <= 4 for literal src");
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Literal = ReadData(Displacement);
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if (Displacement == 1) {
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Literal = static_cast<int8_t>(Literal);
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}
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Operand->TypeSIB.Offset = Literal;
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}
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else if (ModRM.mod == 0) {
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// Explained in Table 1-14. "Operand Addressing Using ModRM and SIB Bytes"
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if (ModRM.rm == 0b101) {
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// 32bit Displacement
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uint32_t Literal;
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Literal = ReadData(4);
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Displacement = 4;
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Operand->TypeRIPLiteral.Type = DecodedOperand::TYPE_RIP_RELATIVE;
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Operand->TypeRIPLiteral.Literal.u = Literal;
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}
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else {
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// Register-direct addressing
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Operand->TypeGPR.Type = DecodedOperand::TYPE_GPR_DIRECT;
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Operand->TypeGPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, false, false, false, false);
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}
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}
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else {
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uint8_t DisplacementSize = ModRM.mod == 1 ? 1 : 4;
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uint32_t Literal{};
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Literal = ReadData(DisplacementSize);
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if (DisplacementSize == 1) {
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Literal = static_cast<int8_t>(Literal);
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}
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Displacement = DisplacementSize;
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Operand->TypeGPRIndirect.Type = DecodedOperand::TYPE_GPR_INDIRECT;
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Operand->TypeGPRIndirect.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, false, false, false, false);
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Operand->TypeGPRIndirect.Displacement = Literal;
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}
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return Displacement;
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}
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bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op) {
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DecodeInst->OP = Op;
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DecodeInst->TableInfo = Info;
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@ -323,6 +467,8 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op)
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bool Is8BitDest = (DecodeFlags::GetSizeDstFlags(DecodeInst->Flags) == DecodeFlags::SIZE_8BIT);
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bool HasREX = !!(DecodeInst->Flags & DecodeFlags::FLAG_REX_PREFIX);
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bool HasHighXMM = HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_HIGH_XMM_REG);
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const bool Has16BitAddressing = !CTX->Config.Is64BitMode &&
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DecodeInst->Flags & DecodeFlags::FLAG_ADDRESS_SIZE;
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uint8_t Displacement = 0;
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auto *CurrentDest = &DecodeInst->Dest;
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@ -395,59 +541,8 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op)
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NonGPR.TypeGPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, NonGPR8Bit, HasREX, HasXMMNonGPR, HasMMNonGPR);
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}
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else {
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if (HasSIB) {
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// SIB
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FEXCore::X86Tables::SIBDecoded SIB;
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SIB.Hex = DecodeInst->SIB;
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NonGPR.TypeSIB.Type = DecodedOperand::TYPE_SIB;
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NonGPR.TypeSIB.Scale = 1 << SIB.scale;
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// The invalid encoding types are described at Table 1-12. "promoted nsigned is always non-zero"
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NonGPR.TypeSIB.Index = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_X ? 1 : 0, SIB.index, false, false, false, false, 0b100);
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NonGPR.TypeSIB.Base = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, SIB.base, false, false, false, false, ModRM.mod == 0 ? 0b101 : 16);
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uint64_t Literal {0};
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LogMan::Throw::A(Displacement <= 4, "Number of bytes should be <= 4 for literal src");
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Literal = ReadData(Displacement);
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if (Displacement == 1) {
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Literal = static_cast<int8_t>(Literal);
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}
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Bytes -= Displacement;
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NonGPR.TypeSIB.Offset = Literal;
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}
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else if (ModRM.mod == 0) {
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// Explained in Table 1-14. "Operand Addressing Using ModRM and SIB Bytes"
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LogMan::Throw::A(ModRM.rm != 0b100, "Shouldn't have hit this here");
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if (ModRM.rm == 0b101) {
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// 32bit Displacement
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uint32_t Literal;
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Literal = ReadData(4);
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Bytes -= 4;
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NonGPR.TypeRIPLiteral.Type = DecodedOperand::TYPE_RIP_RELATIVE;
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NonGPR.TypeRIPLiteral.Literal.u = Literal;
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}
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else {
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// Register-direct addressing
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NonGPR.TypeGPR.Type = DecodedOperand::TYPE_GPR_DIRECT;
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NonGPR.TypeGPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, false, false, false, false);
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}
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}
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else {
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uint8_t DisplacementSize = ModRM.mod == 1 ? 1 : 4;
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uint32_t Literal{};
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Literal = ReadData(DisplacementSize);
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if (DisplacementSize == 1) {
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Literal = static_cast<int8_t>(Literal);
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}
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Bytes -= DisplacementSize;
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NonGPR.TypeGPRIndirect.Type = DecodedOperand::TYPE_GPR_INDIRECT;
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NonGPR.TypeGPRIndirect.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, false, false, false, false);
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NonGPR.TypeGPRIndirect.Displacement = Literal;
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}
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auto Disp = DecodeModRMs_Disp[Has16BitAddressing];
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Bytes -= (this->*Disp)(&NonGPR, ModRM, Displacement);
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}
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};
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@ -67,5 +67,15 @@ private:
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std::vector<DecodedBlocks> Blocks;
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std::set<uint64_t> BlocksToDecode;
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std::set<uint64_t> HasBlocks;
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// ModRM rm decoding
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using DecodeModRMPtr = size_t (FEXCore::Frontend::Decoder::*)(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM, uint8_t Displacement);
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size_t DecodeModRM_16(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM, uint8_t Displacement);
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size_t DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM, uint8_t Displacement);
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const std::array<DecodeModRMPtr, 2> DecodeModRMs_Disp {
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&FEXCore::Frontend::Decoder::DecodeModRM_64,
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&FEXCore::Frontend::Decoder::DecodeModRM_16,
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};
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};
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}
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