From 806587d6ae1c9a6613fc6548597f51ce0b3cfc96 Mon Sep 17 00:00:00 2001
From: CallumDev <callum.mcging@gmail.com>
Date: Mon, 9 Jan 2023 22:21:23 +1030
Subject: [PATCH] Fix FPREM flags calculation in F64

---
 .../Core/OpcodeDispatcher/X87F64.cpp          |  4 +--
 unittests/ASM/X87/FPREM1_Flags.asm            | 34 ++++++++++++++++++
 unittests/ASM/X87/FPREM_Flags.asm             | 34 ++++++++++++++++++
 unittests/ASM/X87_F64/FPREM1_Flags_F64.asm    | 35 +++++++++++++++++++
 unittests/ASM/X87_F64/FPREM_Flags_F64.asm     | 35 +++++++++++++++++++
 5 files changed, 140 insertions(+), 2 deletions(-)
 create mode 100644 unittests/ASM/X87/FPREM1_Flags.asm
 create mode 100644 unittests/ASM/X87/FPREM_Flags.asm
 create mode 100644 unittests/ASM/X87_F64/FPREM1_Flags_F64.asm
 create mode 100644 unittests/ASM/X87_F64/FPREM_Flags_F64.asm

diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp
index 9f10eb9cf..c9df01193 100644
--- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp
+++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp
@@ -822,8 +822,8 @@ void OpDispatchBuilder::X87BinaryOpF64(OpcodeArgs) {
   // Overwrite the op
   result.first->Header.Op = IROp;
 
-  if constexpr (IROp == IR::OP_F80FPREM ||
-    IROp == IR::OP_F80FPREM1) {
+  if constexpr (IROp == IR::OP_F64FPREM ||
+    IROp == IR::OP_F64FPREM1) {
     //TODO: Set C0 to Q2, C3 to Q1, C1 to Q0
     SetRFLAG<FEXCore::X86State::X87FLAG_C2_LOC>(_Constant(0));
   }
diff --git a/unittests/ASM/X87/FPREM1_Flags.asm b/unittests/ASM/X87/FPREM1_Flags.asm
new file mode 100644
index 000000000..03c5f863a
--- /dev/null
+++ b/unittests/ASM/X87/FPREM1_Flags.asm
@@ -0,0 +1,34 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0"
+  }
+}
+%endif
+
+mov rbx, 0xe0000000
+o32 fstenv [rbx]
+mov dword [rbx+4], 0xFFFFFFFF ; set status word to all one
+o32 fldenv [rbx]
+
+lea rdx, [rel data]
+fld tword [rdx + 8 * 0]
+
+lea rdx, [rel data2]
+fld tword [rdx + 8 * 0]
+
+fprem1
+
+xor rax, rax
+fstsw ax
+and rax, 0x400 ; C2 should be set to zero
+
+hlt
+
+align 8
+data:
+  dt 3.0
+  dq 0
+data2:
+  dt 5.1
+  dq 0
diff --git a/unittests/ASM/X87/FPREM_Flags.asm b/unittests/ASM/X87/FPREM_Flags.asm
new file mode 100644
index 000000000..dcaf43c1d
--- /dev/null
+++ b/unittests/ASM/X87/FPREM_Flags.asm
@@ -0,0 +1,34 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0"
+  }
+}
+%endif
+
+mov rbx, 0xe0000000
+o32 fstenv [rbx]
+mov dword [rbx+4], 0xFFFFFFFF ; set status word to all one
+o32 fldenv [rbx]
+
+lea rdx, [rel data]
+fld tword [rdx + 8 * 0]
+
+lea rdx, [rel data2]
+fld tword [rdx + 8 * 0]
+
+fprem
+
+xor rax, rax
+fstsw ax
+and rax, 0x400 ; C2 should be set to zero
+
+hlt
+
+align 8
+data:
+  dt 3.0
+  dq 0
+data2:
+  dt 5.1
+  dq 0
diff --git a/unittests/ASM/X87_F64/FPREM1_Flags_F64.asm b/unittests/ASM/X87_F64/FPREM1_Flags_F64.asm
new file mode 100644
index 000000000..621c22f8f
--- /dev/null
+++ b/unittests/ASM/X87_F64/FPREM1_Flags_F64.asm
@@ -0,0 +1,35 @@
+%ifdef CONFIG
+{
+  "Env": { "FEX_X87REDUCEDPRECISION" : "1" },
+  "RegData": {
+    "RAX": "0"
+  }
+}
+%endif
+
+mov rbx, 0xe0000000
+o32 fstenv [rbx]
+mov dword [rbx+4], 0xFFFFFFFF ; set status word to all one
+o32 fldenv [rbx]
+
+lea rdx, [rel data]
+fld tword [rdx + 8 * 0]
+
+lea rdx, [rel data2]
+fld tword [rdx + 8 * 0]
+
+fprem1
+
+xor rax, rax
+fstsw ax
+and rax, 0x400 ; C2 should be set to zero
+
+hlt
+
+align 8
+data:
+  dt 3.0
+  dq 0
+data2:
+  dt 5.1
+  dq 0
diff --git a/unittests/ASM/X87_F64/FPREM_Flags_F64.asm b/unittests/ASM/X87_F64/FPREM_Flags_F64.asm
new file mode 100644
index 000000000..d4f20d6c8
--- /dev/null
+++ b/unittests/ASM/X87_F64/FPREM_Flags_F64.asm
@@ -0,0 +1,35 @@
+%ifdef CONFIG
+{
+  "Env": { "FEX_X87REDUCEDPRECISION" : "1" },
+  "RegData": {
+    "RAX": "0"
+  }
+}
+%endif
+
+mov rbx, 0xe0000000
+o32 fstenv [rbx]
+mov dword [rbx+4], 0xFFFFFFFF ; set status word to all one
+o32 fldenv [rbx]
+
+lea rdx, [rel data]
+fld tword [rdx + 8 * 0]
+
+lea rdx, [rel data2]
+fld tword [rdx + 8 * 0]
+
+fprem
+
+xor rax, rax
+fstsw ax
+and rax, 0x400 ; C2 should be set to zero
+
+hlt
+
+align 8
+data:
+  dt 3.0
+  dq 0
+data2:
+  dt 5.1
+  dq 0