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OpcodeDispatcher: Handle VPSRLDQ

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This commit is contained in:
lioncash 2022-12-21 04:06:54 +00:00
parent 4aed60ee3d
commit 825e921940
5 changed files with 74 additions and 1 deletions
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1
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp vendored
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@ -6058,6 +6058,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
{OPD(X86Tables::TYPE_VEX_GROUP_13, 1, 0b100), 1, &OpDispatchBuilder::VPSRAIOp<4>},
{OPD(X86Tables::TYPE_VEX_GROUP_14, 1, 0b010), 1, &OpDispatchBuilder::VPSRLIOp<8>},
{OPD(X86Tables::TYPE_VEX_GROUP_14, 1, 0b011), 1, &OpDispatchBuilder::VPSRLDQOp},
{OPD(X86Tables::TYPE_VEX_GROUP_14, 1, 0b110), 1, &OpDispatchBuilder::VPSLLIOp<8>},
{OPD(X86Tables::TYPE_VEX_GROUP_14, 1, 0b111), 1, &OpDispatchBuilder::VPSLLDQOp},

1
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h vendored
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@ -474,6 +474,7 @@ public:
template <size_t ElementSize>
void VPSRLDOp(OpcodeArgs);
void VPSRLDQOp(OpcodeArgs);
template <size_t ElementSize>
void VPSRLIOp(OpcodeArgs);

26
External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp vendored
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@ -1521,6 +1521,32 @@ void OpDispatchBuilder::PSRLDQ(OpcodeArgs) {
StoreResult(FPRClass, Op, Result, -1);
}
void OpDispatchBuilder::VPSRLDQOp(OpcodeArgs) {
const auto DstSize = GetDstSize(Op);
const auto Is128Bit = DstSize == Core::CPUState::XMM_SSE_REG_SIZE;
LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
const uint64_t Shift = Op->Src[1].Data.Literal.Value;
OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
OrderedNode *Result = _VectorZero(DstSize);
if (Is128Bit) {
if (Shift < DstSize) {
Result = _VExtr(DstSize, 1, Result, Src, Shift);
}
} else {
if (Shift < Core::CPUState::XMM_SSE_REG_SIZE) {
OrderedNode *ResultBottom = _VExtr(16, 1, Result, Src, Shift);
OrderedNode *ResultTop = _VExtr(DstSize, 1, Result, Src, 16 + Shift);
Result = _VInsElement(DstSize, 16, 1, 0, ResultBottom, ResultTop);
}
}
StoreResult(FPRClass, Op, Result, -1);
}
void OpDispatchBuilder::PSLLDQ(OpcodeArgs) {
LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
uint64_t Shift = Op->Src[1].Data.Literal.Value;

2
External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp vendored
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@ -497,7 +497,7 @@ void InitializeVEXTables() {
{OPD(TYPE_VEX_GROUP_13, 1, 0b110), 1, X86InstInfo{"VPSLLD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(TYPE_VEX_GROUP_14, 1, 0b010), 1, X86InstInfo{"VPSRLQ", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(TYPE_VEX_GROUP_14, 1, 0b011), 1, X86InstInfo{"VPSRLDQ", TYPE_UNDEC, FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(TYPE_VEX_GROUP_14, 1, 0b011), 1, X86InstInfo{"VPSRLDQ", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(TYPE_VEX_GROUP_14, 1, 0b110), 1, X86InstInfo{"VPSLLQ", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(TYPE_VEX_GROUP_14, 1, 0b111), 1, X86InstInfo{"VPSLLDQ", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_DST | FLAGS_XMM_FLAGS, 1, nullptr}},

45
unittests/ASM/VEX/vpsrldq.asm Normal file
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@ -0,0 +1,45 @@
%ifdef CONFIG
{
"HostFeatures": ["AVX"],
"RegData": {
"XMM2": ["0x41DEADBEEFBAD0DA", "0x0041414141414141", "0x0000000000000000", "0x0000000000000000"],
"XMM3": ["0x41BEEFDEADFAD0CA", "0x0041414141414141", "0x0000000000000000", "0x0000000000000000"],
"XMM4": ["0x41DEADBEEFBAD0DA", "0x0041414141414141", "0x41DEADBEEFBAD0DA", "0x0041414141414141"],
"XMM5": ["0x41BEEFDEADFAD0CA", "0x0041414141414141", "0x41DEADBEEFBAD0DA", "0x0041414141414141"],
"XMM6": ["0x0000000000000000", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
"XMM7": ["0x0000000000000000", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
"XMM8": ["0x4141414141414141", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
"XMM9": ["0x4141414141414141", "0x0000000000000000", "0x4141414141414141", "0x0000000000000000"]
}
}
%endif
lea rdx, [rel .data]
vmovaps ymm0, [rdx]
vmovaps ymm1, [rdx + 32]
vpsrldq xmm2, xmm0, 1
vpsrldq xmm3, xmm1, 1
vpsrldq ymm4, ymm0, 1
vpsrldq ymm5, ymm1, 1
vpsrldq xmm6, xmm0, 16
vpsrldq ymm7, ymm1, 16
vpsrldq xmm8, xmm0, 8
vpsrldq ymm9, ymm1, 8
hlt
align 32
.data:
dq 0xDEADBEEFBAD0DAD1
dq 0x4141414141414141
dq 0xDEADBEEFBAD0DAD1
dq 0x4141414141414141
dq 0xBEEFDEADFAD0CAD1
dq 0x4141414141414141
dq 0xDEADBEEFBAD0DAD1
dq 0x4141414141414141