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OpcodeDispatcher: Handle VUCOMISD

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This commit is contained in:
lioncash 2022-12-07 21:23:05 +00:00
parent d1ab636df1
commit 83bccc0032
3 changed files with 63 additions and 1 deletions
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1
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp vendored
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@ -5822,6 +5822,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
{OPD(1, 0b01, 0x2B), 1, &OpDispatchBuilder::VMOVVectorNTOp},
{OPD(1, 0b00, 0x2E), 1, &OpDispatchBuilder::UCOMISxOp<4>},
{OPD(1, 0b01, 0x2E), 1, &OpDispatchBuilder::UCOMISxOp<8>},
{OPD(1, 0b00, 0x54), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VAND, 16>},
{OPD(1, 0b01, 0x54), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VAND, 16>},

2
External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp vendored
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@ -131,7 +131,7 @@ void InitializeVEXTables() {
{OPD(1, 0b11, 0x2D), 1, X86InstInfo{"VCVTSD2SI", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b00, 0x2E), 1, X86InstInfo{"VUCOMISS", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b01, 0x2E), 1, X86InstInfo{"VUCOMISD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b01, 0x2E), 1, X86InstInfo{"VUCOMISD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b00, 0x2F), 1, X86InstInfo{"VCOMISS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b01, 0x2F), 1, X86InstInfo{"VCOMISD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},

61
unittests/ASM/VEX/vucomisd.asm Normal file
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@ -0,0 +1,61 @@
%ifdef CONFIG
{
"HostFeatures": ["AVX"],
"RegData": {
"RAX": "0x4700",
"RBX": "0x0300"
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
lea rdx, [rel .data]
vmovaps xmm0, [rdx + 16 * 0]
vucomisd xmm0, [rdx + 16 * 1] ; 1.0 <comp> 4.0
; 0: CF - 00000001
; 1: - 00000010
; 2: PF - 00000000
; 3: 0 - 00000000
; 4: AF - 00000000 <- 0
; 5: 0 - 00000000
; 6: ZF - 00000000
; 7: SF - 00000000 <- 0
; ================
; 00000011
; OF: LAHF doesn't load - 0
mov rax, 0
lahf
mov rbx, rax
vucomisd xmm0, [rdx + 16 * 2] ; 1.0 <comp> NaN
; 0: CF - 00000001
; 1: - 00000010
; 2: PF - 00000100
; 3: 0 - 00000000
; 4: AF - 00000000 <- 0
; 5: 0 - 00000000
; 6: ZF - 01000000
; 7: SF - 00000000 <- 0
; ================
; 01000111
; OF: LAHF doesn't load - 0
mov rax, 0
lahf
hlt
align 16
.data:
dq 0x3FF0000000000000
dq 0x4000000000000000
dq 0x4010000000000000
dq 0x4010000000000000
dq 0x7FF8000000000000
dq 0x4010000000000000