From 8540332520a06fe92c2c34b110f259c293de582d Mon Sep 17 00:00:00 2001
From: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Date: Wed, 21 Feb 2024 22:04:18 -0400
Subject: [PATCH] IR: add AddWithFlags

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
---
 .../Source/Interface/Core/JIT/Arm64/ALUOps.cpp    | 15 +++++++++++++++
 FEXCore/Source/Interface/IR/IR.json               |  8 ++++++++
 FEXCore/Source/Interface/IR/Passes/ConstProp.cpp  |  1 +
 .../RedundantFlagCalculationElimination.cpp       |  7 +++++++
 4 files changed, 31 insertions(+)

diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
index 322c8925b..37152c9b9 100644
--- a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
+++ b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
@@ -85,6 +85,21 @@ DEF_OP(Add) {
   }
 }
 
+DEF_OP(AddWithFlags) {
+  auto Op = IROp->C<IR::IROp_AddWithFlags>();
+  const uint8_t OpSize = IROp->Size;
+
+  LOGMAN_THROW_AA_FMT(OpSize == 4 || OpSize == 8, "Unsupported {} size: {}", __func__, OpSize);
+  const auto EmitSize = OpSize == IR::i64Bit ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+
+  uint64_t Const;
+  if (IsInlineConstant(Op->Src2, &Const)) {
+    adds(EmitSize, GetReg(Node), GetReg(Op->Src1.ID()), Const);
+  } else {
+    adds(EmitSize, GetReg(Node), GetReg(Op->Src1.ID()), GetReg(Op->Src2.ID()));
+  }
+}
+
 DEF_OP(AddShift) {
   auto Op = IROp->C<IR::IROp_AddShift>();
   const uint8_t OpSize = IROp->Size;
diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json
index bcc9fc4d9..b3a6fdac6 100644
--- a/FEXCore/Source/Interface/IR/IR.json
+++ b/FEXCore/Source/Interface/IR/IR.json
@@ -961,6 +961,14 @@
           "_Shift != ShiftType::ROR"
         ]
       },
+      "GPR = AddWithFlags OpSize:#Size, GPR:$Src1, GPR:$Src2": {
+        "Desc": [ "Integer add. Truncates and sets NZCV per AddNZCV"],
+        "DestSize": "Size",
+        "HasSideEffects": true,
+        "EmitValidation": [
+          "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
+        ]
+      },
       "AddNZCV OpSize:#Size, GPR:$Src1, GPR:$Src2": {
         "Desc": ["Set NZCV for the sum of two GPRs"],
         "HasSideEffects": true,
diff --git a/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp b/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp
index cf3866a05..b59fc7da9 100644
--- a/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp
+++ b/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp
@@ -965,6 +965,7 @@ bool ConstProp::ConstantInlining(IREmitter *IREmit, const IRListView& CurrentIR)
       case OP_SUB:
       case OP_ADDNZCV:
       case OP_SUBNZCV:
+      case OP_ADDWITHFLAGS:
       case OP_SUBWITHFLAGS:
       {
         auto Op = IROp->C<IR::IROp_Add>();
diff --git a/FEXCore/Source/Interface/IR/Passes/RedundantFlagCalculationElimination.cpp b/FEXCore/Source/Interface/IR/Passes/RedundantFlagCalculationElimination.cpp
index da89dd216..3c2fcdff2 100644
--- a/FEXCore/Source/Interface/IR/Passes/RedundantFlagCalculationElimination.cpp
+++ b/FEXCore/Source/Interface/IR/Passes/RedundantFlagCalculationElimination.cpp
@@ -128,6 +128,13 @@ DeadFlagCalculationEliminination::Classify(IROp_Header *IROp)
         .Replacement = OP_AND,
       };
 
+    case OP_ADDWITHFLAGS:
+      return {
+        .Write = FLAG_NZCV,
+        .CanReplace = true,
+        .Replacement = OP_ADD,
+      };
+
     case OP_SUBWITHFLAGS:
       return {
         .Write = FLAG_NZCV,