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Merge pull request #3715 from pmatos/FXCHFlag

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FXCH should set C1 to zero
This commit is contained in:
Ryan Houdek 2024-06-19 00:20:01 -07:00 committed by GitHub
commit 87fe1d672e
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GPG Key ID: B5690EEEBB952194
5 changed files with 115 additions and 48 deletions
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3
FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp
View File

@ -745,6 +745,9 @@ void OpDispatchBuilder::FXCH(OpcodeArgs) {
auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);
auto b = _LoadContextIndexed(arg, 16, MMBaseOffset(), 16, FPRClass);
// Set C1 to Zero
SetRFLAG<FEXCore::X86State::X87FLAG_C1_LOC>(_Constant(0));
// Write to ST[TOP]
_StoreContextIndexed(b, top, 16, MMBaseOffset(), 16, FPRClass);
_StoreContextIndexed(a, arg, 16, MMBaseOffset(), 16, FPRClass);

40
unittests/InstructionCountCI/FlagM/x87.json
View File

@ -4233,26 +4233,28 @@
]
},
"fxch st0, st0": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xc8 /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x0 (0)",
"and w21, w21, #0x7",
"mov w21, #0x0",
"add w22, w20, #0x0 (0)",
"and w22, w22, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"add x0, x28, x22, lsl #4",
"ldr q3, [x0, #1040]",
"strb w21, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"add x0, x28, x22, lsl #4",
"str q2, [x0, #1040]"
]
},
"fxch st0, st1": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xc9 /1"
],
@ -4264,6 +4266,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -4271,7 +4275,7 @@
]
},
"fxch st0, st2": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xca /1"
],
@ -4283,6 +4287,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -4290,7 +4296,7 @@
]
},
"fxch st0, st3": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xcb /1"
],
@ -4302,6 +4308,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -4309,7 +4317,7 @@
]
},
"fxch st0, st4": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xcc /1"
],
@ -4321,6 +4329,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -4328,7 +4338,7 @@
]
},
"fxch st0, st5": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xcd /1"
],
@ -4340,6 +4350,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -4347,7 +4359,7 @@
]
},
"fxch st0, st6": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xce /1"
],
@ -4359,6 +4371,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -4366,7 +4380,7 @@
]
},
"fxch st0, st7": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xcf /1"
],
@ -4378,6 +4392,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",

40
unittests/InstructionCountCI/FlagM/x87_f64.json
View File

@ -1897,26 +1897,28 @@
]
},
"fxch st0, st0": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xc8 /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x0 (0)",
"and w21, w21, #0x7",
"mov w21, #0x0",
"add w22, w20, #0x0 (0)",
"and w22, w22, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"add x0, x28, x22, lsl #4",
"ldr q3, [x0, #1040]",
"strb w21, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"add x0, x28, x22, lsl #4",
"str q2, [x0, #1040]"
]
},
"fxch st0, st1": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xc9 /1"
],
@ -1928,6 +1930,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -1935,7 +1939,7 @@
]
},
"fxch st0, st2": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xca /1"
],
@ -1947,6 +1951,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -1954,7 +1960,7 @@
]
},
"fxch st0, st3": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xcb /1"
],
@ -1966,6 +1972,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -1973,7 +1981,7 @@
]
},
"fxch st0, st4": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xcc /1"
],
@ -1985,6 +1993,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -1992,7 +2002,7 @@
]
},
"fxch st0, st5": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xcd /1"
],
@ -2004,6 +2014,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -2011,7 +2023,7 @@
]
},
"fxch st0, st6": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xce /1"
],
@ -2023,6 +2035,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -2030,7 +2044,7 @@
]
},
"fxch st0, st7": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xcf /1"
],
@ -2042,6 +2056,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",

40
unittests/InstructionCountCI/x87.json
View File

@ -4232,26 +4232,28 @@
]
},
"fxch st0, st0": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xc8 /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x0 (0)",
"and w21, w21, #0x7",
"mov w21, #0x0",
"add w22, w20, #0x0 (0)",
"and w22, w22, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"add x0, x28, x22, lsl #4",
"ldr q3, [x0, #1040]",
"strb w21, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"add x0, x28, x22, lsl #4",
"str q2, [x0, #1040]"
]
},
"fxch st0, st1": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xc9 /1"
],
@ -4263,6 +4265,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -4270,7 +4274,7 @@
]
},
"fxch st0, st2": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xca /1"
],
@ -4282,6 +4286,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -4289,7 +4295,7 @@
]
},
"fxch st0, st3": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xcb /1"
],
@ -4301,6 +4307,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -4308,7 +4316,7 @@
]
},
"fxch st0, st4": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xcc /1"
],
@ -4320,6 +4328,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -4327,7 +4337,7 @@
]
},
"fxch st0, st5": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xcd /1"
],
@ -4339,6 +4349,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -4346,7 +4358,7 @@
]
},
"fxch st0, st6": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xce /1"
],
@ -4358,6 +4370,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -4365,7 +4379,7 @@
]
},
"fxch st0, st7": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xcf /1"
],
@ -4377,6 +4391,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",

40
unittests/InstructionCountCI/x87_f64.json
View File

@ -1914,26 +1914,28 @@
]
},
"fxch st0, st0": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xc8 /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1019]",
"add w21, w20, #0x0 (0)",
"and w21, w21, #0x7",
"mov w21, #0x0",
"add w22, w20, #0x0 (0)",
"and w22, w22, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"add x0, x28, x22, lsl #4",
"ldr q3, [x0, #1040]",
"strb w21, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"add x0, x28, x22, lsl #4",
"str q2, [x0, #1040]"
]
},
"fxch st0, st1": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xc9 /1"
],
@ -1945,6 +1947,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -1952,7 +1956,7 @@
]
},
"fxch st0, st2": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xca /1"
],
@ -1964,6 +1968,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -1971,7 +1977,7 @@
]
},
"fxch st0, st3": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xcb /1"
],
@ -1983,6 +1989,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -1990,7 +1998,7 @@
]
},
"fxch st0, st4": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xcc /1"
],
@ -2002,6 +2010,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -2009,7 +2019,7 @@
]
},
"fxch st0, st5": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xcd /1"
],
@ -2021,6 +2031,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -2028,7 +2040,7 @@
]
},
"fxch st0, st6": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xce /1"
],
@ -2040,6 +2052,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",
@ -2047,7 +2061,7 @@
]
},
"fxch st0, st7": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xcf /1"
],
@ -2059,6 +2073,8 @@
"ldr q2, [x0, #1040]",
"add x0, x28, x21, lsl #4",
"ldr q3, [x0, #1040]",
"mov w22, #0x0",
"strb w22, [x28, #1017]",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1040]",
"add x0, x28, x21, lsl #4",