FEX-Emu/FEX
1
0
Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2025-01-08 22:52:51 +00:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity

OpcodeDispatcher: Handle VPINSRW

Browse Source
This commit is contained in:
Lioncache 2023-03-14 13:04:13 -04:00
parent 24f03dd740
commit 8ce87d3b27
5 changed files with 69 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp vendored
View File

@ -5788,6 +5788,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
{OPD(1, 0b10, 0xC2), 1, &OpDispatchBuilder::AVXVFCMPOp<4, true>},
{OPD(1, 0b11, 0xC2), 1, &OpDispatchBuilder::AVXVFCMPOp<8, true>},
{OPD(1, 0b01, 0xC4), 1, &OpDispatchBuilder::VPINSRWOp},
{OPD(1, 0b01, 0xC5), 1, &OpDispatchBuilder::PExtrOp<2>},
{OPD(1, 0b00, 0xC6), 1, &OpDispatchBuilder::VSHUFOp<4>},

1
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h vendored
View File

@ -497,6 +497,7 @@ public:
void VPHSUBSWOp(OpcodeArgs);
void VPINSRBOp(OpcodeArgs);
void VPINSRWOp(OpcodeArgs);
void VPMADDUBSWOp(OpcodeArgs);
void VPMADDWDOp(OpcodeArgs);

7
External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp vendored
View File

@ -1331,6 +1331,13 @@ void OpDispatchBuilder::VPINSRBOp(OpcodeArgs) {
StoreResult(FPRClass, Op, Final, -1);
}
void OpDispatchBuilder::VPINSRWOp(OpcodeArgs) {
OrderedNode *Result = PINSROpImpl(Op, 2, Op->Src[0], Op->Src[1], Op->Src[2]);
OrderedNode *Final = _VMov(16, Result);
StoreResult(FPRClass, Op, Final, -1);
}
OrderedNode* OpDispatchBuilder::InsertPSOpImpl(OpcodeArgs, const X86Tables::DecodedOperand& Src1,
const X86Tables::DecodedOperand& Src2,
const X86Tables::DecodedOperand& Imm) {

2
External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp vendored
View File

@ -102,7 +102,7 @@ void InitializeVEXTables() {
{OPD(1, 0b10, 0xC2), 1, X86InstInfo{"VCMPccSS", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(1, 0b11, 0xC2), 1, X86InstInfo{"VCMPccSD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(1, 0b01, 0xC4), 1, X86InstInfo{"VPINSRW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b01, 0xC4), 1, X86InstInfo{"VPINSRW", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_SF_SRC_GPR | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(1, 0b01, 0xC5), 1, X86InstInfo{"VPEXTRW", TYPE_INST, GenFlagsSizes(SIZE_32BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_REG_ONLY | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(1, 0b00, 0xC6), 1, X86InstInfo{"VSHUFPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}},

59
unittests/ASM/VEX/vpinsrw.asm Normal file
View File

@ -0,0 +1,59 @@
%ifdef CONFIG
{
"HostFeatures": ["AVX"],
"RegData": {
"XMM0": ["0x4142434445467778", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
"XMM1": ["0x4142434477784748", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
"XMM2": ["0x4142777845464748", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
"XMM3": ["0x7778434445464748", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
"XMM4": ["0x4142434445464748", "0x5152535455567778", "0x0000000000000000", "0x0000000000000000"],
"XMM5": ["0x4142434445464748", "0x5152535477785758", "0x0000000000000000", "0x0000000000000000"],
"XMM6": ["0x4142434445464748", "0x5152777855565758", "0x0000000000000000", "0x0000000000000000"],
"XMM7": ["0x4142434445464748", "0x7778535455565758", "0x0000000000000000", "0x0000000000000000"],
"XMM8": ["0x4142434445467778", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
"XMM9": ["0x4142434477784748", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
"XMM10": ["0x4142777845464748", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
"XMM11": ["0x7778434445464748", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
"XMM12": ["0x4142434445464748", "0x5152535455567778", "0x0000000000000000", "0x0000000000000000"],
"XMM13": ["0x4142434445464748", "0x5152535477785758", "0x0000000000000000", "0x0000000000000000"],
"XMM14": ["0x4142434445464748", "0x5152777855565758", "0x0000000000000000", "0x0000000000000000"],
"XMM15": ["0x4142434445464748", "0x7778535455565758", "0x0000000000000000", "0x0000000000000000"]
}
}
%endif
lea rdx, [rel .data]
mov rax, 0x7172737475767778
vmovapd ymm0, [rdx]
vpinsrw xmm1, xmm0, eax, 1
vpinsrw xmm2, xmm0, eax, 2
vpinsrw xmm3, xmm0, eax, 3
vpinsrw xmm4, xmm0, eax, 4
vpinsrw xmm5, xmm0, eax, 5
vpinsrw xmm6, xmm0, eax, 6
vpinsrw xmm7, xmm0, eax, 7
vpinsrw xmm8, xmm0, [rdx + 32], 0
vpinsrw xmm9, xmm0, [rdx + 32], 1
vpinsrw xmm10, xmm0, [rdx + 32], 2
vpinsrw xmm11, xmm0, [rdx + 32], 3
vpinsrw xmm12, xmm0, [rdx + 32], 4
vpinsrw xmm13, xmm0, [rdx + 32], 5
vpinsrw xmm14, xmm0, [rdx + 32], 6
vpinsrw xmm15, xmm0, [rdx + 32], 7
vpinsrw xmm0, xmm0, eax, 0
hlt
align 32
.data:
dq 0x4142434445464748
dq 0x5152535455565758
dq 0x6162636465666768
dq 0x7172737475767778
dq 0x7172737475767778