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IR: add UMaxV
will be used to accelerate ptest Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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@ -1372,6 +1372,32 @@ DEF_OP(VUMinV) {
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}
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}
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}
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}
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DEF_OP(VUMaxV) {
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const auto Op = IROp->C<IR::IROp_VUMaxV>();
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const auto OpSize = IROp->Size;
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const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
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const auto ElementSize = Op->Header.ElementSize;
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const auto Dst = GetVReg(Node);
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const auto Vector = GetVReg(Op->Vector.ID());
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LOGMAN_THROW_AA_FMT(ElementSize == 1 || ElementSize == 2 || ElementSize == 4 || ElementSize == 8, "Invalid size");
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const auto SubRegSize =
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ElementSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
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ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
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ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
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ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit : ARMEmitter::SubRegSize::i8Bit;
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if (HostSupportsSVE256 && Is256Bit) {
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const auto Pred = PRED_TMP_32B;
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umaxv(SubRegSize, Dst, Pred, Vector.Z());
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} else {
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// Vector
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umaxv(SubRegSize, Dst.Q(), Vector.Q());
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}
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}
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DEF_OP(VURAvg) {
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DEF_OP(VURAvg) {
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const auto Op = IROp->C<IR::IROp_VURAvg>();
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const auto Op = IROp->C<IR::IROp_VURAvg>();
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const auto OpSize = IROp->Size;
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const auto OpSize = IROp->Size;
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@ -1612,7 +1612,13 @@
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"DestSize": "RegisterSize",
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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"NumElements": "RegisterSize / ElementSize"
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},
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},
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"FPR = VUMaxV u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
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"Desc": ["Does a horizontal vector unsigned maximum of elements across the source vector",
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"Result is a zero extended scalar"
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],
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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},
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"FPR = VFAbs u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
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"FPR = VFAbs u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
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"DestSize": "RegisterSize",
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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"NumElements": "RegisterSize / ElementSize"
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