mirror of
https://github.com/FEX-Emu/FEX.git
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Merge pull request #2878 from lioncash/fcpy
ARMEmitter: Handle SVE FCPY (predicated)
This commit is contained in:
Ryan Houdek
GitHub
commit
8fce13386a
@ -3,6 +3,7 @@
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#include "Interface/Core/ArchHelpers/CodeEmitter/Buffer.h"
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#include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h"
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#include <FEXCore/Utils/BitUtils.h>
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#include <FEXCore/Utils/CompilerDefs.h>
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#include <FEXCore/Utils/EnumUtils.h>
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#include <FEXCore/Utils/LogManager.h>
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@ -11,6 +12,7 @@
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#include <aarch64/assembler-aarch64.h>
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#include <array>
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#include <cstdint>
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#include <utility>
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#include <type_traits>
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@ -1032,9 +1032,16 @@ public:
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// SVE Bitwise Immediate
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// XXX: DUPM
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// SVE bitwise logical with immediate (unpredicated)
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// XXX:
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// SVE Integer Wide Immediate - Predicated
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// XXX: FCPY
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void fcpy(SubRegSize size, ZRegister zd, PRegisterMerge pg, float value) {
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SVEBroadcastFloatImmPredicated(size, zd, pg, value);
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}
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void fmov(SubRegSize size, ZRegister zd, PRegisterMerge pg, float value) {
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fcpy(size, zd, pg, value);
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}
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// SVE copy integer immediate (predicated)
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// XXX:
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@ -1495,26 +1502,16 @@ public:
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LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i16Bit ||
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size == FEXCore::ARMEmitter::SubRegSize::i32Bit ||
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size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Unsupported fmov size");
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uint32_t Imm;
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uint32_t Imm{};
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if (size == SubRegSize::i16Bit) {
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LOGMAN_THROW_A_FMT(vixl::aarch64::Assembler::IsImmFP16(vixl::Float16(Value)), "Invalid float");
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Imm = vixl::VFP::FP16ToImm8(vixl::Float16(Value));
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}
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else if (size == SubRegSize::i32Bit) {
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LOGMAN_THROW_A_FMT(vixl::VFP::IsImmFP32(Value), "Invalid float");
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Imm = vixl::VFP::FP32ToImm8(Value);
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}
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else if (size == SubRegSize::i64Bit) {
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LOGMAN_THROW_A_FMT(vixl::VFP::IsImmFP64(Value), "Invalid float");
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Imm = vixl::VFP::FP64ToImm8(Value);
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}
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else {
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LOGMAN_MSG_A_FMT("Invalid subregsize");
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FEX_UNREACHABLE;
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Imm = FP16ToImm8(vixl::Float16(Value));
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} else if (size == SubRegSize::i32Bit) {
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Imm = FP32ToImm8(Value);
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} else if (size == SubRegSize::i64Bit) {
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Imm = FP64ToImm8(Value);
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}
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SVEBroadcastFloatImm(0b00, 0, Imm, size, zd);
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SVEBroadcastFloatImmUnpredicated(0b00, 0, Imm, size, zd);
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}
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void fmov(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd, float Value) {
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fdup(size, zd, Value);
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@ -3335,10 +3332,29 @@ private:
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dc32(Instr);
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}
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void SVEBroadcastFloatImm(uint32_t opc, uint32_t o2, uint32_t imm, FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd) {
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constexpr uint32_t Op = 0b0010'0101'0011'1001'110 << 13;
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uint32_t Instr = Op;
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void SVEBroadcastFloatImmPredicated(SubRegSize size, ZRegister zd, PRegister pg, float value) {
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LOGMAN_THROW_AA_FMT(size == SubRegSize::i16Bit ||
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size == SubRegSize::i32Bit ||
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size == SubRegSize::i64Bit, "Unsupported fcpy/fmov size");
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uint32_t imm{};
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if (size == SubRegSize::i16Bit) {
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imm = FP16ToImm8(vixl::Float16(value));
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} else if (size == SubRegSize::i32Bit) {
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imm = FP32ToImm8(value);
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} else if (size == SubRegSize::i64Bit) {
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imm = FP64ToImm8(value);
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}
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uint32_t Instr = 0b0000'0101'0001'0000'1100'0000'0000'0000;
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Instr |= FEXCore::ToUnderlying(size) << 22;
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Instr |= pg.Idx() << 16;
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Instr |= imm << 5;
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Instr |= zd.Idx();
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dc32(Instr);
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}
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void SVEBroadcastFloatImmUnpredicated(uint32_t opc, uint32_t o2, uint32_t imm, SubRegSize size, ZRegister zd) {
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uint32_t Instr = 0b0010'0101'0011'1001'1100'0000'0000'0000;
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Instr |= FEXCore::ToUnderlying(size) << 22;
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Instr |= opc << 17;
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Instr |= o2 << 13;
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@ -4876,3 +4892,90 @@ private:
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.tszl_imm3 = encoded_shift & 0b11111,
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};
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}
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// Alias that returns the equivalently sized unsigned type for a floating-point type T.
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template <typename T>
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requires(std::is_same_v<T, float> || std::is_same_v<T, double> || std::is_same_v<T, vixl::Float16>)
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using FloatToEquivalentUInt = std::conditional_t<sizeof(T) == 2, uint16_t,
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std::conditional_t<sizeof(T) == 4, uint32_t, uint64_t>>;
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// Determines if a floating-point value is capable of being converted
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// into an 8-bit immediate. See pseudocode definition of VFPExpandImm
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// in ARM A-profile reference manual for a general overview of how this was derived.
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template <typename T>
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requires(std::is_same_v<T, float> || std::is_same_v<T, double> || std::is_same_v<T, vixl::Float16>)
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[[nodiscard, maybe_unused]] static bool IsValidFPValueForImm8(T value) {
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const uint64_t bits = FEXCore::BitCast<FloatToEquivalentUInt<T>>(value);
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const uint64_t datasize_idx = FEXCore::ilog2(sizeof(T)) - 1;
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static constexpr std::array mantissa_masks{
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0x00000000'0000003FULL, // half (bits [5:0])
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0x00000000'0007FFFFULL, // single (bits [18:0])
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0x0000FFFF'FFFFFFFFULL, // double (bits [47:0])
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};
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const auto mantissa_mask = mantissa_masks[datasize_idx];
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// Relevant mantissa bits must be set to zero
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if ((bits & mantissa_mask) != 0) {
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return false;
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}
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static constexpr std::array exponent_masks{
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0x00000000'00003000ULL, // half (bits [13:12])
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0x00000000'3E000000ULL, // single (bits [29:25])
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0x3FC00000'00000000ULL, // double (bits [61:54])
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};
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const auto exponent_mask = exponent_masks[datasize_idx];
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const auto masked_exponent = bits & exponent_mask;
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// Relevant exponent bits must either be all set or all cleared.
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if (masked_exponent != 0 && masked_exponent != exponent_mask) {
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return false;
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}
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// The two bits before the sign bit must be inverses of each other.
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const auto datasize = 8ULL * sizeof(T);
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const auto inverse = bits ^ (bits << 1);
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const auto inverse_mask = 1ULL << (datasize - 2);
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if ((inverse & inverse_mask) == 0) {
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return false;
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}
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return true;
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}
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static uint32_t FP16ToImm8(vixl::Float16 value) {
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LOGMAN_THROW_A_FMT(IsValidFPValueForImm8(value),
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"Value cannot be encoded into an 8-bit immediate");
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const uint32_t bits = vixl::Float16ToRawbits(value);
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const uint32_t sign = (bits & 0x8000) >> 8;
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const uint32_t expb2 = (bits & 0x2000) >> 7;
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const uint32_t b5_to_0 = (bits >> 6) & 0x3F;
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return sign | expb2 | b5_to_0;
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}
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static uint32_t FP32ToImm8(float value) {
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LOGMAN_THROW_A_FMT(IsValidFPValueForImm8(value),
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"Value ({}) cannot be encoded into an 8-bit immediate", value);
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const auto bits = FEXCore::BitCast<uint32_t>(value);
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const auto sign = (bits & 0x80000000) >> 24;
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const auto expb2 = (bits & 0x20000000) >> 23;
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const auto b5_to_0 = (bits >> 19) & 0x3F;
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return sign | expb2 | b5_to_0;
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}
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static uint32_t FP64ToImm8(double value) {
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LOGMAN_THROW_A_FMT(IsValidFPValueForImm8(value),
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"Value ({}) cannot be encoded into an 8-bit immediate", value);
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const auto bits = FEXCore::BitCast<uint64_t>(value);
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const auto sign = (bits & 0x80000000'00000000) >> 56;
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const auto expb2 = (bits & 0x20000000'00000000) >> 55;
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const auto b5_to_0 = (bits >> 48) & 0x3F;
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return static_cast<uint32_t>(sign | expb2 | b5_to_0);
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}
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58
External/FEXCore/unittests/Emitter/SVE_Tests.cpp
vendored
58
External/FEXCore/unittests/Emitter/SVE_Tests.cpp
vendored
@ -2275,14 +2275,72 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE broadcast integer immediat
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TEST_SINGLE(mov_imm(SubRegSize::i64Bit, ZReg::z30, 127, false), "mov z30.d, #127");
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}
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TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE broadcast floating-point immediate (predicated)") {
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TEST_SINGLE(fcpy(SubRegSize::i16Bit, ZReg::z30, PReg::p6.Merging(), -0.125), "fmov z30.h, p6/m, #0xc0 (-0.1250)");
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TEST_SINGLE(fcpy(SubRegSize::i32Bit, ZReg::z30, PReg::p6.Merging(), -0.125), "fmov z30.s, p6/m, #0xc0 (-0.1250)");
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TEST_SINGLE(fcpy(SubRegSize::i64Bit, ZReg::z30, PReg::p6.Merging(), -0.125), "fmov z30.d, p6/m, #0xc0 (-0.1250)");
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TEST_SINGLE(fcpy(SubRegSize::i16Bit, ZReg::z30, PReg::p6.Merging(), 0.5), "fmov z30.h, p6/m, #0x60 (0.5000)");
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TEST_SINGLE(fcpy(SubRegSize::i32Bit, ZReg::z30, PReg::p6.Merging(), 0.5), "fmov z30.s, p6/m, #0x60 (0.5000)");
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TEST_SINGLE(fcpy(SubRegSize::i64Bit, ZReg::z30, PReg::p6.Merging(), 0.5), "fmov z30.d, p6/m, #0x60 (0.5000)");
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TEST_SINGLE(fcpy(SubRegSize::i16Bit, ZReg::z30, PReg::p6.Merging(), 1.0), "fmov z30.h, p6/m, #0x70 (1.0000)");
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TEST_SINGLE(fcpy(SubRegSize::i32Bit, ZReg::z30, PReg::p6.Merging(), 1.0), "fmov z30.s, p6/m, #0x70 (1.0000)");
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TEST_SINGLE(fcpy(SubRegSize::i64Bit, ZReg::z30, PReg::p6.Merging(), 1.0), "fmov z30.d, p6/m, #0x70 (1.0000)");
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TEST_SINGLE(fcpy(SubRegSize::i16Bit, ZReg::z30, PReg::p6.Merging(), 31.0), "fmov z30.h, p6/m, #0x3f (31.0000)");
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TEST_SINGLE(fcpy(SubRegSize::i32Bit, ZReg::z30, PReg::p6.Merging(), 31.0), "fmov z30.s, p6/m, #0x3f (31.0000)");
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TEST_SINGLE(fcpy(SubRegSize::i64Bit, ZReg::z30, PReg::p6.Merging(), 31.0), "fmov z30.d, p6/m, #0x3f (31.0000)");
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TEST_SINGLE(fmov(SubRegSize::i16Bit, ZReg::z30, PReg::p6.Merging(), -0.125), "fmov z30.h, p6/m, #0xc0 (-0.1250)");
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TEST_SINGLE(fmov(SubRegSize::i32Bit, ZReg::z30, PReg::p6.Merging(), -0.125), "fmov z30.s, p6/m, #0xc0 (-0.1250)");
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TEST_SINGLE(fmov(SubRegSize::i64Bit, ZReg::z30, PReg::p6.Merging(), -0.125), "fmov z30.d, p6/m, #0xc0 (-0.1250)");
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TEST_SINGLE(fmov(SubRegSize::i16Bit, ZReg::z30, PReg::p6.Merging(), 0.5), "fmov z30.h, p6/m, #0x60 (0.5000)");
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TEST_SINGLE(fmov(SubRegSize::i32Bit, ZReg::z30, PReg::p6.Merging(), 0.5), "fmov z30.s, p6/m, #0x60 (0.5000)");
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TEST_SINGLE(fmov(SubRegSize::i64Bit, ZReg::z30, PReg::p6.Merging(), 0.5), "fmov z30.d, p6/m, #0x60 (0.5000)");
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TEST_SINGLE(fmov(SubRegSize::i16Bit, ZReg::z30, PReg::p6.Merging(), 1.0), "fmov z30.h, p6/m, #0x70 (1.0000)");
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TEST_SINGLE(fmov(SubRegSize::i32Bit, ZReg::z30, PReg::p6.Merging(), 1.0), "fmov z30.s, p6/m, #0x70 (1.0000)");
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TEST_SINGLE(fmov(SubRegSize::i64Bit, ZReg::z30, PReg::p6.Merging(), 1.0), "fmov z30.d, p6/m, #0x70 (1.0000)");
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TEST_SINGLE(fmov(SubRegSize::i16Bit, ZReg::z30, PReg::p6.Merging(), 31.0), "fmov z30.h, p6/m, #0x3f (31.0000)");
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TEST_SINGLE(fmov(SubRegSize::i32Bit, ZReg::z30, PReg::p6.Merging(), 31.0), "fmov z30.s, p6/m, #0x3f (31.0000)");
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TEST_SINGLE(fmov(SubRegSize::i64Bit, ZReg::z30, PReg::p6.Merging(), 31.0), "fmov z30.d, p6/m, #0x3f (31.0000)");
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}
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TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE broadcast floating-point immediate (unpredicated)") {
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TEST_SINGLE(fdup(SubRegSize::i16Bit, ZReg::z30, -0.125), "fmov z30.h, #0xc0 (-0.1250)");
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TEST_SINGLE(fdup(SubRegSize::i32Bit, ZReg::z30, -0.125), "fmov z30.s, #0xc0 (-0.1250)");
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TEST_SINGLE(fdup(SubRegSize::i64Bit, ZReg::z30, -0.125), "fmov z30.d, #0xc0 (-0.1250)");
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TEST_SINGLE(fdup(SubRegSize::i16Bit, ZReg::z30, 0.5), "fmov z30.h, #0x60 (0.5000)");
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TEST_SINGLE(fdup(SubRegSize::i32Bit, ZReg::z30, 0.5), "fmov z30.s, #0x60 (0.5000)");
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TEST_SINGLE(fdup(SubRegSize::i64Bit, ZReg::z30, 0.5), "fmov z30.d, #0x60 (0.5000)");
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TEST_SINGLE(fdup(SubRegSize::i16Bit, ZReg::z30, 1.0), "fmov z30.h, #0x70 (1.0000)");
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TEST_SINGLE(fdup(SubRegSize::i32Bit, ZReg::z30, 1.0), "fmov z30.s, #0x70 (1.0000)");
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TEST_SINGLE(fdup(SubRegSize::i64Bit, ZReg::z30, 1.0), "fmov z30.d, #0x70 (1.0000)");
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TEST_SINGLE(fdup(SubRegSize::i16Bit, ZReg::z30, 31.0), "fmov z30.h, #0x3f (31.0000)");
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TEST_SINGLE(fdup(SubRegSize::i32Bit, ZReg::z30, 31.0), "fmov z30.s, #0x3f (31.0000)");
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TEST_SINGLE(fdup(SubRegSize::i64Bit, ZReg::z30, 31.0), "fmov z30.d, #0x3f (31.0000)");
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TEST_SINGLE(fmov(SubRegSize::i16Bit, ZReg::z30, -0.125), "fmov z30.h, #0xc0 (-0.1250)");
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TEST_SINGLE(fmov(SubRegSize::i32Bit, ZReg::z30, -0.125), "fmov z30.s, #0xc0 (-0.1250)");
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TEST_SINGLE(fmov(SubRegSize::i64Bit, ZReg::z30, -0.125), "fmov z30.d, #0xc0 (-0.1250)");
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TEST_SINGLE(fmov(SubRegSize::i16Bit, ZReg::z30, 0.5), "fmov z30.h, #0x60 (0.5000)");
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TEST_SINGLE(fmov(SubRegSize::i32Bit, ZReg::z30, 0.5), "fmov z30.s, #0x60 (0.5000)");
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TEST_SINGLE(fmov(SubRegSize::i64Bit, ZReg::z30, 0.5), "fmov z30.d, #0x60 (0.5000)");
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TEST_SINGLE(fmov(SubRegSize::i16Bit, ZReg::z30, 1.0), "fmov z30.h, #0x70 (1.0000)");
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TEST_SINGLE(fmov(SubRegSize::i32Bit, ZReg::z30, 1.0), "fmov z30.s, #0x70 (1.0000)");
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TEST_SINGLE(fmov(SubRegSize::i64Bit, ZReg::z30, 1.0), "fmov z30.d, #0x70 (1.0000)");
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TEST_SINGLE(fmov(SubRegSize::i16Bit, ZReg::z30, 31.0), "fmov z30.h, #0x3f (31.0000)");
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TEST_SINGLE(fmov(SubRegSize::i32Bit, ZReg::z30, 31.0), "fmov z30.s, #0x3f (31.0000)");
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TEST_SINGLE(fmov(SubRegSize::i64Bit, ZReg::z30, 31.0), "fmov z30.d, #0x3f (31.0000)");
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}
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TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE predicate count") {
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