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CPUBackend: Removes SupportsSaturatingRoundingShifts option

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This has always been true ever since we removed the x86 JIT and
Interpreter. This was left over and adding more code for no reason.
This commit is contained in:
Ryan Houdek 2024-06-21 01:01:57 -07:00
parent 424218e327
commit 903d6a742e
No known key found for this signature in database
4 changed files with 6 additions and 24 deletions
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1
FEXCore/Source/Interface/Core/CPUBackend.h
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@ -36,7 +36,6 @@ namespace CodeSerialize {
namespace CPU { namespace CPU {
struct CPUBackendFeatures { struct CPUBackendFeatures {
bool SupportsFlags = false; bool SupportsFlags = false;
bool SupportsSaturatingRoundingShifts = false;
bool SupportsVTBL2 = false; bool SupportsVTBL2 = false;
}; };

1
FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp
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@ -887,7 +887,6 @@ fextl::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::ContextImpl*
CPUBackendFeatures GetArm64JITBackendFeatures() { CPUBackendFeatures GetArm64JITBackendFeatures() {
return CPUBackendFeatures { return CPUBackendFeatures {
.SupportsFlags = true, .SupportsFlags = true,
.SupportsSaturatingRoundingShifts = true,
.SupportsVTBL2 = true, .SupportsVTBL2 = true,
}; };
} }

8
FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp
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@ -890,17 +890,9 @@ void OpDispatchBuilder::AVX128_VPACKUS(OpcodeArgs) {
} }
Ref OpDispatchBuilder::AVX128_PSIGNImpl(size_t ElementSize, Ref Src1, Ref Src2) { Ref OpDispatchBuilder::AVX128_PSIGNImpl(size_t ElementSize, Ref Src1, Ref Src2) {
if (CTX->BackendFeatures.SupportsSaturatingRoundingShifts) {
Ref Control = _VSQSHL(OpSize::i128Bit, ElementSize, Src2, (ElementSize * 8) - 1); Ref Control = _VSQSHL(OpSize::i128Bit, ElementSize, Src2, (ElementSize * 8) - 1);
Control = _VSRSHR(OpSize::i128Bit, ElementSize, Control, (ElementSize * 8) - 1); Control = _VSRSHR(OpSize::i128Bit, ElementSize, Control, (ElementSize * 8) - 1);
return _VMul(OpSize::i128Bit, ElementSize, Src1, Control); return _VMul(OpSize::i128Bit, ElementSize, Src1, Control);
} else {
auto NegVec = _VNeg(OpSize::i128Bit, ElementSize, Src1);
Ref CmpLT = _VCMPLTZ(OpSize::i128Bit, ElementSize, Src2);
Ref CmpEQ = _VCMPEQZ(OpSize::i128Bit, ElementSize, Src2);
auto BSLResult = _VBSL(OpSize::i128Bit, CmpLT, NegVec, Src1);
return _VAndn(OpSize::i128Bit, OpSize::i128Bit, BSLResult, CmpEQ);
}
} }
template<size_t ElementSize> template<size_t ElementSize>

8
FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
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@ -1723,17 +1723,9 @@ void OpDispatchBuilder::VEXTRACT128Op(OpcodeArgs) {
Ref OpDispatchBuilder::PSIGNImpl(OpcodeArgs, size_t ElementSize, Ref Src1, Ref Src2) { Ref OpDispatchBuilder::PSIGNImpl(OpcodeArgs, size_t ElementSize, Ref Src1, Ref Src2) {
const auto Size = GetSrcSize(Op); const auto Size = GetSrcSize(Op);
if (CTX->BackendFeatures.SupportsSaturatingRoundingShifts) {
Ref Control = _VSQSHL(Size, ElementSize, Src2, (ElementSize * 8) - 1); Ref Control = _VSQSHL(Size, ElementSize, Src2, (ElementSize * 8) - 1);
Control = _VSRSHR(Size, ElementSize, Control, (ElementSize * 8) - 1); Control = _VSRSHR(Size, ElementSize, Control, (ElementSize * 8) - 1);
return _VMul(Size, ElementSize, Src1, Control); return _VMul(Size, ElementSize, Src1, Control);
} else {
auto NegVec = _VNeg(Size, ElementSize, Src1);
Ref CmpLT = _VCMPLTZ(Size, ElementSize, Src2);
Ref CmpEQ = _VCMPEQZ(Size, ElementSize, Src2);
auto BSLResult = _VBSL(Size, CmpLT, NegVec, Src1);
return _VAndn(Size, Size, BSLResult, CmpEQ);
}
} }
template<size_t ElementSize> template<size_t ElementSize>