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OpcodeDispatcher: Handle VINSERTI128

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This commit is contained in:
lioncash 2022-12-14 04:26:14 +00:00
parent fe7c6da1e2
commit 90828aeb11
3 changed files with 45 additions and 1 deletions
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1
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp vendored
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@ -5984,6 +5984,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
{OPD(3, 0b01, 0x06), 1, &OpDispatchBuilder::VPERM2Op},
{OPD(3, 0b01, 0x18), 1, &OpDispatchBuilder::VINSERTOp},
{OPD(3, 0b01, 0x38), 1, &OpDispatchBuilder::VINSERTOp},
{OPD(3, 0b01, 0x46), 1, &OpDispatchBuilder::VPERM2Op},
};

2
External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp vendored
View File

@ -435,7 +435,7 @@ void InitializeVEXTables() {
{OPD(3, 0b01, 0x21), 1, X86InstInfo{"VINSERTPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(3, 0b01, 0x22), 1, X86InstInfo{"VPINSRD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(3, 0b01, 0x38), 1, X86InstInfo{"VINSERTI128", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(3, 0b01, 0x38), 1, X86InstInfo{"VINSERTI128", TYPE_INST, GenFlagsSameSize(SIZE_256BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(3, 0b01, 0x39), 1, X86InstInfo{"VEXTRACTI128", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(3, 0b01, 0x40), 1, X86InstInfo{"VDPPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},

43
unittests/ASM/VEX/vinserti128.asm Normal file
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@ -0,0 +1,43 @@
%ifdef CONFIG
{
"HostFeatures": ["AVX"],
"RegData": {
"XMM0": ["0x3FF0000000000000", "0xEEEEEEEEEEEEEEEE", "0xFFFFFFFFFFFFFFFF", "0xAAAAAAAAAAAAAAAA"],
"XMM1": ["0xBBBBBBBBBBBBBBBB", "0xDDDDDDDDDDDDDDDD", "0xCCCCCCCCCCCCCCCC", "0x9999999999999999"],
"XMM2": ["0x3FF0000000000000", "0xEEEEEEEEEEEEEEEE", "0xBBBBBBBBBBBBBBBB", "0xDDDDDDDDDDDDDDDD"],
"XMM3": ["0x3FF0000000000000", "0xEEEEEEEEEEEEEEEE", "0xBBBBBBBBBBBBBBBB", "0xDDDDDDDDDDDDDDDD"],
"XMM4": ["0xBBBBBBBBBBBBBBBB", "0xDDDDDDDDDDDDDDDD", "0xFFFFFFFFFFFFFFFF", "0xAAAAAAAAAAAAAAAA"],
"XMM5": ["0xBBBBBBBBBBBBBBBB", "0xDDDDDDDDDDDDDDDD", "0xFFFFFFFFFFFFFFFF", "0xAAAAAAAAAAAAAAAA"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
lea rdx, [rel .data]
vmovapd ymm0, [rdx]
vmovapd ymm1, [rdx + 32]
; Insert into upper lane
vinserti128 ymm2, ymm0, xmm1, 1
vinserti128 ymm3, ymm0, [rdx + 32], 1
; Insert into lower lane
vinserti128 ymm4, ymm0, xmm1, 0
vinserti128 ymm5, ymm0, [rdx + 32], 0
hlt
align 32
.data:
dq 0x3FF0000000000000
dq 0xEEEEEEEEEEEEEEEE
dq 0xFFFFFFFFFFFFFFFF
dq 0xAAAAAAAAAAAAAAAA
dq 0xBBBBBBBBBBBBBBBB
dq 0xDDDDDDDDDDDDDDDD
dq 0xCCCCCCCCCCCCCCCC
dq 0x9999999999999999