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Merge pull request #3635 from alyssarosenzweig/opt/flag-store

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OpcodeDispatcher: reorder some moves
This commit is contained in:
Ryan Houdek 2024-05-16 10:58:40 -07:00 committed by GitHub
commit 926eefc86c
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GPG Key ID: B5690EEEBB952194
8 changed files with 351 additions and 370 deletions
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26
FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
View File

@ -1511,9 +1511,9 @@ void OpDispatchBuilder::SHLImmediateOp(OpcodeArgs) {
OrderedNode* Src = _Constant(Size, Shift); OrderedNode* Src = _Constant(Size, Shift);
OrderedNode* Result = _Lshl(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, Src); OrderedNode* Result = _Lshl(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, Src);
StoreResult(GPRClass, Op, Result, -1);
GenerateFlags_ShiftLeftImmediate(Op, Result, Dest, Shift); GenerateFlags_ShiftLeftImmediate(Op, Result, Dest, Shift);
CalculateDeferredFlags();
StoreResult(GPRClass, Op, Result, -1);
} }
void OpDispatchBuilder::SHROp(OpcodeArgs) { void OpDispatchBuilder::SHROp(OpcodeArgs) {
@ -1534,8 +1534,9 @@ void OpDispatchBuilder::SHRImmediateOp(OpcodeArgs) {
OrderedNode* Src = _Constant(Size, Shift); OrderedNode* Src = _Constant(Size, Shift);
auto ALUOp = _Lshr(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, Src); auto ALUOp = _Lshr(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, Src);
StoreResult(GPRClass, Op, ALUOp, -1);
GenerateFlags_ShiftRightImmediate(Op, ALUOp, Dest, Shift); GenerateFlags_ShiftRightImmediate(Op, ALUOp, Dest, Shift);
CalculateDeferredFlags();
StoreResult(GPRClass, Op, ALUOp, -1);
} }
void OpDispatchBuilder::SHLDOp(OpcodeArgs) { void OpDispatchBuilder::SHLDOp(OpcodeArgs) {
@ -1602,8 +1603,9 @@ void OpDispatchBuilder::SHLDImmediateOp(OpcodeArgs) {
Res = _Extr(OpSizeFromSrc(Op), Dest, Src, Size - Shift); Res = _Extr(OpSizeFromSrc(Op), Dest, Src, Size - Shift);
} }
StoreResult(GPRClass, Op, Res, -1);
GenerateFlags_ShiftLeftImmediate(Op, Res, Dest, Shift); GenerateFlags_ShiftLeftImmediate(Op, Res, Dest, Shift);
CalculateDeferredFlags();
StoreResult(GPRClass, Op, Res, -1);
} else if (Shift == 0 && Size == 32) { } else if (Shift == 0 && Size == 32) {
// Ensure Zext still occurs // Ensure Zext still occurs
StoreResult(GPRClass, Op, Dest, -1); StoreResult(GPRClass, Op, Dest, -1);
@ -1701,9 +1703,9 @@ void OpDispatchBuilder::ASHRImmediateOp(OpcodeArgs) {
OrderedNode* Src = _Constant(Size, Shift); OrderedNode* Src = _Constant(Size, Shift);
OrderedNode* Result = _Ashr(IR::SizeToOpSize(std::max<uint8_t>(4, GetOpSize(Dest))), Dest, Src); OrderedNode* Result = _Ashr(IR::SizeToOpSize(std::max<uint8_t>(4, GetOpSize(Dest))), Dest, Src);
StoreResult(GPRClass, Op, Result, -1);
GenerateFlags_SignShiftRightImmediate(Op, Result, Dest, Shift); GenerateFlags_SignShiftRightImmediate(Op, Result, Dest, Shift);
CalculateDeferredFlags();
StoreResult(GPRClass, Op, Result, -1);
} }
template<bool Left, bool IsImmediate, bool Is1Bit> template<bool Left, bool IsImmediate, bool Is1Bit>
@ -2296,14 +2298,14 @@ void OpDispatchBuilder::RCLOp1Bit(OpcodeArgs) {
// TODO: Use `adc Res, xzr, Dest, lsl 1` to save an instruction // TODO: Use `adc Res, xzr, Dest, lsl 1` to save an instruction
OrderedNode* Res = _Orlshl(OpSize, CF, Dest, 1); OrderedNode* Res = _Orlshl(OpSize, CF, Dest, 1);
StoreResult(GPRClass, Op, Res, -1);
// Our new CF will be the top bit of the source // Our new CF will be the top bit of the source
SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(Dest, Size - 1, true); SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(Dest, Size - 1, true);
// OF is the top two MSBs XOR'd together // OF is the top two MSBs XOR'd together
// Top two MSBs is CF and top bit of result // Top two MSBs is CF and top bit of result
SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(_Xor(OpSize, Res, Dest), Size - 1, true); SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(_Xor(OpSize, Res, Dest), Size - 1, true);
StoreResult(GPRClass, Op, Res, -1);
} }
void OpDispatchBuilder::RCLOp(OpcodeArgs) { void OpDispatchBuilder::RCLOp(OpcodeArgs) {
@ -2840,9 +2842,8 @@ void OpDispatchBuilder::XADDOp(OpcodeArgs) {
HandledLock = Op->Flags & FEXCore::X86Tables::DecodeFlags::FLAG_LOCK; HandledLock = Op->Flags & FEXCore::X86Tables::DecodeFlags::FLAG_LOCK;
Dest = AppendSegmentOffset(Dest, Op->Flags); Dest = AppendSegmentOffset(Dest, Op->Flags);
auto Before = _AtomicFetchAdd(OpSizeFromSrc(Op), Src, Dest); auto Before = _AtomicFetchAdd(OpSizeFromSrc(Op), Src, Dest);
StoreResult(GPRClass, Op, Op->Src[0], Before, -1);
CalculateFlags_ADD(GetSrcSize(Op), Before, Src); CalculateFlags_ADD(GetSrcSize(Op), Before, Src);
StoreResult(GPRClass, Op, Op->Src[0], Before, -1);
} }
} }
@ -3943,10 +3944,11 @@ void OpDispatchBuilder::CMPXCHGOp(OpcodeArgs) {
Size = 8; Size = 8;
} }
GenerateFlags_SUB(Op, Src3Lower, CASResult);
CalculateDeferredFlags();
// RAX gets the result of the CAS op // RAX gets the result of the CAS op
StoreGPRRegister(X86State::REG_RAX, RAXResult, Size); StoreGPRRegister(X86State::REG_RAX, RAXResult, Size);
GenerateFlags_SUB(Op, Src3Lower, CASResult);
} }
} }

3
FEXCore/Source/Interface/Core/OpcodeDispatcher.h
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@ -1569,12 +1569,11 @@ private:
// shift, with correct PF handling. // shift, with correct PF handling.
void HandleShift(X86Tables::DecodedOp Op, OrderedNode* Result, OrderedNode* Dest, ShiftType Shift, OrderedNode* Src) { void HandleShift(X86Tables::DecodedOp Op, OrderedNode* Result, OrderedNode* Dest, ShiftType Shift, OrderedNode* Src) {
StoreResult(GPRClass, Op, Result, -1);
auto OldPF = GetRFLAG(X86State::RFLAG_PF_RAW_LOC); auto OldPF = GetRFLAG(X86State::RFLAG_PF_RAW_LOC);
HandleNZCV_RMW(); HandleNZCV_RMW();
CalculatePF(_ShiftFlags(OpSizeFromSrc(Op), Result, Dest, Shift, Src, OldPF)); CalculatePF(_ShiftFlags(OpSizeFromSrc(Op), Result, Dest, Shift, Src, OldPF));
StoreResult(GPRClass, Op, Result, -1);
} }
// Helper to derive Dest by a given builder-using Expression with the opcode // Helper to derive Dest by a given builder-using Expression with the opcode

8
unittests/InstructionCountCI/Atomics.json
View File

@ -339,11 +339,11 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxtb w20, w7", "uxtb w20, w7",
"ldaddalb w20, w21, [x4]", "ldaddalb w20, w21, [x4]",
"bfxil x7, x21, #0, #8",
"eor w27, w21, w20", "eor w27, w21, w20",
"lsl w0, w21, #24", "lsl w0, w21, #24",
"cmn w0, w20, lsl #24", "cmn w0, w20, lsl #24",
"add w26, w21, w20" "add w26, w21, w20",
"bfxil x7, x21, #0, #8"
] ]
}, },
"xadd word [rax], bx": { "xadd word [rax], bx": {
@ -352,11 +352,11 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxth w20, w7", "uxth w20, w7",
"ldaddalh w20, w21, [x4]", "ldaddalh w20, w21, [x4]",
"bfxil x7, x21, #0, #16",
"eor w27, w21, w20", "eor w27, w21, w20",
"lsl w0, w21, #16", "lsl w0, w21, #16",
"cmn w0, w20, lsl #16", "cmn w0, w20, lsl #16",
"add w26, w21, w20" "add w26, w21, w20",
"bfxil x7, x21, #0, #16"
] ]
}, },
"xadd dword [rax], ebx": { "xadd dword [rax], ebx": {

8
unittests/InstructionCountCI/FlagM/Atomics.json
View File

@ -288,11 +288,11 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxtb w20, w7", "uxtb w20, w7",
"ldaddalb w20, w21, [x4]", "ldaddalb w20, w21, [x4]",
"bfxil x7, x21, #0, #8",
"eor w27, w21, w20", "eor w27, w21, w20",
"lsl w0, w21, #24", "lsl w0, w21, #24",
"cmn w0, w20, lsl #24", "cmn w0, w20, lsl #24",
"add w26, w21, w20" "add w26, w21, w20",
"bfxil x7, x21, #0, #8"
] ]
}, },
"xadd word [rax], bx": { "xadd word [rax], bx": {
@ -301,11 +301,11 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxth w20, w7", "uxth w20, w7",
"ldaddalh w20, w21, [x4]", "ldaddalh w20, w21, [x4]",
"bfxil x7, x21, #0, #16",
"eor w27, w21, w20", "eor w27, w21, w20",
"lsl w0, w21, #16", "lsl w0, w21, #16",
"cmn w0, w20, lsl #16", "cmn w0, w20, lsl #16",
"add w26, w21, w20" "add w26, w21, w20",
"bfxil x7, x21, #0, #16"
] ]
}, },
"xadd dword [rax], ebx": { "xadd dword [rax], ebx": {

194
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
View File

@ -964,9 +964,9 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxtb w20, w4", "uxtb w20, w4",
"lsl w26, w20, #2", "lsl w26, w20, #2",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24", "cmn wzr, w26, lsl #24",
"rmif x20, #5, #nzCv" "rmif x20, #5, #nzCv",
"bfxil x4, x26, #0, #8"
] ]
}, },
"shr al, 2": { "shr al, 2": {
@ -975,9 +975,9 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxtb w20, w4", "uxtb w20, w4",
"lsr w26, w20, #2", "lsr w26, w20, #2",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24", "cmn wzr, w26, lsl #24",
"rmif x20, #0, #nzCv" "rmif x20, #0, #nzCv",
"bfxil x4, x26, #0, #8"
] ]
}, },
"sar al, 2": { "sar al, 2": {
@ -987,9 +987,9 @@
"uxtb w20, w4", "uxtb w20, w4",
"sxtb x20, w20", "sxtb x20, w20",
"asr x26, x20, #2", "asr x26, x20, #2",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24", "cmn wzr, w26, lsl #24",
"rmif x20, #0, #nzCv" "rmif x20, #0, #nzCv",
"bfxil x4, x26, #0, #8"
] ]
}, },
"rol ax, 2": { "rol ax, 2": {
@ -1134,9 +1134,9 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxth w20, w4", "uxth w20, w4",
"lsl w26, w20, #2", "lsl w26, w20, #2",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"rmif x20, #13, #nzCv" "rmif x20, #13, #nzCv",
"bfxil x4, x26, #0, #16"
] ]
}, },
"shl eax, 2": { "shl eax, 2": {
@ -1144,21 +1144,20 @@
"Comment": "GROUP2 0xC1 /4", "Comment": "GROUP2 0xC1 /4",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w4", "mov w20, w4",
"lsl w4, w20, #2", "lsl w26, w20, #2",
"tst w4, w4", "tst w26, w26",
"rmif x20, #29, #nzCv", "rmif x20, #29, #nzCv",
"mov x26, x4" "mov x4, x26"
] ]
}, },
"shl rax, 2": { "shl rax, 2": {
"ExpectedInstructionCount": 5, "ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xC1 /4", "Comment": "GROUP2 0xC1 /4",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "lsl x26, x4, #2",
"lsl x4, x20, #2", "tst x26, x26",
"tst x4, x4", "rmif x4, #61, #nzCv",
"rmif x20, #61, #nzCv", "mov x4, x26"
"mov x26, x4"
] ]
}, },
"shr ax, 2": { "shr ax, 2": {
@ -1167,9 +1166,9 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxth w20, w4", "uxth w20, w4",
"lsr w26, w20, #2", "lsr w26, w20, #2",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"rmif x20, #0, #nzCv" "rmif x20, #0, #nzCv",
"bfxil x4, x26, #0, #16"
] ]
}, },
"shr eax, 2": { "shr eax, 2": {
@ -1177,21 +1176,20 @@
"Comment": "GROUP2 0xC1 /5", "Comment": "GROUP2 0xC1 /5",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w4", "mov w20, w4",
"lsr w4, w20, #2", "lsr w26, w20, #2",
"tst w4, w4", "tst w26, w26",
"rmif x20, #0, #nzCv", "rmif x20, #0, #nzCv",
"mov x26, x4" "mov x4, x26"
] ]
}, },
"shr rax, 2": { "shr rax, 2": {
"ExpectedInstructionCount": 5, "ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xC1 /5", "Comment": "GROUP2 0xC1 /5",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "lsr x26, x4, #2",
"lsr x4, x20, #2", "tst x26, x26",
"tst x4, x4", "rmif x4, #0, #nzCv",
"rmif x20, #0, #nzCv", "mov x4, x26"
"mov x26, x4"
] ]
}, },
"sar ax, 2": { "sar ax, 2": {
@ -1201,9 +1199,9 @@
"uxth w20, w4", "uxth w20, w4",
"sxth x20, w20", "sxth x20, w20",
"asr x26, x20, #2", "asr x26, x20, #2",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"rmif x20, #0, #nzCv" "rmif x20, #0, #nzCv",
"bfxil x4, x26, #0, #16"
] ]
}, },
"sar eax, 2": { "sar eax, 2": {
@ -1211,21 +1209,20 @@
"Comment": "GROUP2 0xC1 /7", "Comment": "GROUP2 0xC1 /7",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w4", "mov w20, w4",
"asr w4, w20, #2", "asr w26, w20, #2",
"tst w4, w4", "tst w26, w26",
"rmif x20, #0, #nzCv", "rmif x20, #0, #nzCv",
"mov x26, x4" "mov x4, x26"
] ]
}, },
"sar rax, 2": { "sar rax, 2": {
"ExpectedInstructionCount": 5, "ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xC1 /7", "Comment": "GROUP2 0xC1 /7",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "asr x26, x4, #2",
"asr x4, x20, #2", "tst x26, x26",
"tst x4, x4", "rmif x4, #0, #nzCv",
"rmif x20, #0, #nzCv", "mov x4, x26"
"mov x26, x4"
] ]
}, },
"rol al, 1": { "rol al, 1": {
@ -1262,10 +1259,10 @@
"uxtb w20, w4", "uxtb w20, w4",
"cset w21, hs", "cset w21, hs",
"orr w21, w21, w20, lsl #1", "orr w21, w21, w20, lsl #1",
"bfxil x4, x21, #0, #8",
"rmif x20, #6, #nzCv", "rmif x20, #6, #nzCv",
"eor w20, w21, w20", "eor w20, w21, w20",
"rmif x20, #7, #nzcV" "rmif x20, #7, #nzcV",
"bfxil x4, x21, #0, #8"
] ]
}, },
"rcr al, 1": { "rcr al, 1": {
@ -1288,11 +1285,11 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxtb w20, w4", "uxtb w20, w4",
"lsl w26, w20, #1", "lsl w26, w20, #1",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24", "cmn wzr, w26, lsl #24",
"rmif x20, #6, #nzCv", "rmif x20, #6, #nzCv",
"eor w20, w26, w20", "eor w20, w26, w20",
"rmif x20, #7, #nzcV" "rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
] ]
}, },
"shr al, 1": { "shr al, 1": {
@ -1301,10 +1298,10 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxtb w20, w4", "uxtb w20, w4",
"lsr w26, w20, #1", "lsr w26, w20, #1",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24", "cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv", "rmif x20, #63, #nzCv",
"rmif x20, #7, #nzcV" "rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
] ]
}, },
"sar al, 1": { "sar al, 1": {
@ -1314,9 +1311,9 @@
"uxtb w20, w4", "uxtb w20, w4",
"sxtb x20, w20", "sxtb x20, w20",
"asr x26, x20, #1", "asr x26, x20, #1",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24", "cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv" "rmif x20, #63, #nzCv",
"bfxil x4, x26, #0, #8"
] ]
}, },
"rol ax, 1": { "rol ax, 1": {
@ -1392,10 +1389,10 @@
"uxth w20, w4", "uxth w20, w4",
"cset w21, hs", "cset w21, hs",
"orr w21, w21, w20, lsl #1", "orr w21, w21, w20, lsl #1",
"bfxil x4, x21, #0, #16",
"rmif x20, #14, #nzCv", "rmif x20, #14, #nzCv",
"eor w20, w21, w20", "eor w20, w21, w20",
"rmif x20, #15, #nzcV" "rmif x20, #15, #nzcV",
"bfxil x4, x21, #0, #16"
] ]
}, },
"rcl eax, 1": { "rcl eax, 1": {
@ -1463,11 +1460,11 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxth w20, w4", "uxth w20, w4",
"lsl w26, w20, #1", "lsl w26, w20, #1",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"rmif x20, #14, #nzCv", "rmif x20, #14, #nzCv",
"eor w20, w26, w20", "eor w20, w26, w20",
"rmif x20, #15, #nzcV" "rmif x20, #15, #nzcV",
"bfxil x4, x26, #0, #16"
] ]
}, },
"shl eax, 1": { "shl eax, 1": {
@ -1475,25 +1472,24 @@
"Comment": "GROUP2 0xd1 /4", "Comment": "GROUP2 0xd1 /4",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w4", "mov w20, w4",
"lsl w4, w20, #1", "lsl w26, w20, #1",
"tst w4, w4", "tst w26, w26",
"rmif x20, #30, #nzCv", "rmif x20, #30, #nzCv",
"mov x26, x4", "eor w20, w26, w20",
"eor w20, w4, w20", "rmif x20, #31, #nzcV",
"rmif x20, #31, #nzcV" "mov x4, x26"
] ]
}, },
"shl rax, 1": { "shl rax, 1": {
"ExpectedInstructionCount": 7, "ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd1 /4", "Comment": "GROUP2 0xd1 /4",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "lsl x26, x4, #1",
"lsl x4, x20, #1", "tst x26, x26",
"tst x4, x4", "rmif x4, #62, #nzCv",
"rmif x20, #62, #nzCv", "eor x20, x26, x4",
"mov x26, x4", "rmif x20, #63, #nzcV",
"eor x20, x4, x20", "mov x4, x26"
"rmif x20, #63, #nzcV"
] ]
}, },
"shr ax, 1": { "shr ax, 1": {
@ -1502,10 +1498,10 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxth w20, w4", "uxth w20, w4",
"lsr w26, w20, #1", "lsr w26, w20, #1",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv", "rmif x20, #63, #nzCv",
"rmif x20, #15, #nzcV" "rmif x20, #15, #nzcV",
"bfxil x4, x26, #0, #16"
] ]
}, },
"shr eax, 1": { "shr eax, 1": {
@ -1513,23 +1509,22 @@
"Comment": "GROUP2 0xd1 /5", "Comment": "GROUP2 0xd1 /5",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w4", "mov w20, w4",
"lsr w4, w20, #1", "lsr w26, w20, #1",
"tst w4, w4", "tst w26, w26",
"rmif x20, #63, #nzCv", "rmif x20, #63, #nzCv",
"mov x26, x4", "rmif x20, #31, #nzcV",
"rmif x20, #31, #nzcV" "mov x4, x26"
] ]
}, },
"shr rax, 1": { "shr rax, 1": {
"ExpectedInstructionCount": 6, "ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xd1 /5", "Comment": "GROUP2 0xd1 /5",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "lsr x26, x4, #1",
"lsr x4, x20, #1", "tst x26, x26",
"tst x4, x4", "rmif x4, #63, #nzCv",
"rmif x20, #63, #nzCv", "rmif x4, #63, #nzcV",
"mov x26, x4", "mov x4, x26"
"rmif x20, #63, #nzcV"
] ]
}, },
"sar ax, 1": { "sar ax, 1": {
@ -1539,9 +1534,9 @@
"uxth w20, w4", "uxth w20, w4",
"sxth x20, w20", "sxth x20, w20",
"asr x26, x20, #1", "asr x26, x20, #1",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv" "rmif x20, #63, #nzCv",
"bfxil x4, x26, #0, #16"
] ]
}, },
"sar eax, 1": { "sar eax, 1": {
@ -1549,21 +1544,20 @@
"Comment": "GROUP2 0xd1 /7", "Comment": "GROUP2 0xd1 /7",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w4", "mov w20, w4",
"asr w4, w20, #1", "asr w26, w20, #1",
"tst w4, w4", "tst w26, w26",
"rmif x20, #63, #nzCv", "rmif x20, #63, #nzCv",
"mov x26, x4" "mov x4, x26"
] ]
}, },
"sar rax, 1": { "sar rax, 1": {
"ExpectedInstructionCount": 5, "ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xd1 /7", "Comment": "GROUP2 0xd1 /7",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "asr x26, x4, #1",
"asr x4, x20, #1", "tst x26, x26",
"tst x4, x4", "rmif x4, #63, #nzCv",
"rmif x20, #63, #nzCv", "mov x4, x26"
"mov x26, x4"
] ]
}, },
"rol al, cl": { "rol al, cl": {
@ -1663,7 +1657,6 @@
"uxtb w20, w4", "uxtb w20, w4",
"uxtb w21, w5", "uxtb w21, w5",
"lsl w22, w20, w21", "lsl w22, w20, w21",
"bfxil x4, x22, #0, #8",
"cbz w21, #+0x24", "cbz w21, #+0x24",
"cmn wzr, w22, lsl #24", "cmn wzr, w22, lsl #24",
"mov x26, x22", "mov x26, x22",
@ -1672,7 +1665,8 @@
"lsr w0, w20, w0", "lsr w0, w20, w0",
"eor w2, w20, w22", "eor w2, w20, w22",
"rmif x0, #63, #nzCv", "rmif x0, #63, #nzCv",
"rmif x2, #7, #nzcV" "rmif x2, #7, #nzcV",
"bfxil x4, x22, #0, #8"
] ]
}, },
"shr al, cl": { "shr al, cl": {
@ -1682,7 +1676,6 @@
"uxtb w20, w4", "uxtb w20, w4",
"uxtb w21, w5", "uxtb w21, w5",
"lsr w22, w20, w21", "lsr w22, w20, w21",
"bfxil x4, x22, #0, #8",
"cbz w21, #+0x20", "cbz w21, #+0x20",
"cmn wzr, w22, lsl #24", "cmn wzr, w22, lsl #24",
"mov x26, x22", "mov x26, x22",
@ -1690,7 +1683,8 @@
"lsr w0, w20, w0", "lsr w0, w20, w0",
"eor w2, w20, w22", "eor w2, w20, w22",
"rmif x0, #63, #nzCv", "rmif x0, #63, #nzCv",
"rmif x2, #7, #nzcV" "rmif x2, #7, #nzcV",
"bfxil x4, x22, #0, #8"
] ]
}, },
"sar al, cl": { "sar al, cl": {
@ -1701,13 +1695,13 @@
"uxtb w21, w5", "uxtb w21, w5",
"sxtb x20, w20", "sxtb x20, w20",
"asr w22, w20, w21", "asr w22, w20, w21",
"bfxil x4, x22, #0, #8",
"cbz w21, #+0x18", "cbz w21, #+0x18",
"cmn wzr, w22, lsl #24", "cmn wzr, w22, lsl #24",
"mov x26, x22", "mov x26, x22",
"sub x0, x21, #0x1 (1)", "sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0", "lsr w0, w20, w0",
"rmif x0, #63, #nzCv" "rmif x0, #63, #nzCv",
"bfxil x4, x22, #0, #8"
] ]
}, },
"rol ax, cl": { "rol ax, cl": {
@ -1930,7 +1924,6 @@
"uxth w20, w4", "uxth w20, w4",
"uxth w21, w5", "uxth w21, w5",
"lsl w22, w20, w21", "lsl w22, w20, w21",
"bfxil x4, x22, #0, #16",
"cbz w21, #+0x24", "cbz w21, #+0x24",
"cmn wzr, w22, lsl #16", "cmn wzr, w22, lsl #16",
"mov x26, x22", "mov x26, x22",
@ -1939,7 +1932,8 @@
"lsr w0, w20, w0", "lsr w0, w20, w0",
"eor w2, w20, w22", "eor w2, w20, w22",
"rmif x0, #63, #nzCv", "rmif x0, #63, #nzCv",
"rmif x2, #15, #nzcV" "rmif x2, #15, #nzcV",
"bfxil x4, x22, #0, #16"
] ]
}, },
"shl eax, cl": { "shl eax, cl": {
@ -1980,7 +1974,6 @@
"uxth w20, w4", "uxth w20, w4",
"uxth w21, w5", "uxth w21, w5",
"lsr w22, w20, w21", "lsr w22, w20, w21",
"bfxil x4, x22, #0, #16",
"cbz w21, #+0x20", "cbz w21, #+0x20",
"cmn wzr, w22, lsl #16", "cmn wzr, w22, lsl #16",
"mov x26, x22", "mov x26, x22",
@ -1988,7 +1981,8 @@
"lsr w0, w20, w0", "lsr w0, w20, w0",
"eor w2, w20, w22", "eor w2, w20, w22",
"rmif x0, #63, #nzCv", "rmif x0, #63, #nzCv",
"rmif x2, #15, #nzcV" "rmif x2, #15, #nzcV",
"bfxil x4, x22, #0, #16"
] ]
}, },
"shr eax, cl": { "shr eax, cl": {
@ -2030,13 +2024,13 @@
"uxth w21, w5", "uxth w21, w5",
"sxth x20, w20", "sxth x20, w20",
"asr w22, w20, w21", "asr w22, w20, w21",
"bfxil x4, x22, #0, #16",
"cbz w21, #+0x18", "cbz w21, #+0x18",
"cmn wzr, w22, lsl #16", "cmn wzr, w22, lsl #16",
"mov x26, x22", "mov x26, x22",
"sub x0, x21, #0x1 (1)", "sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0", "lsr w0, w20, w0",
"rmif x0, #63, #nzCv" "rmif x0, #63, #nzCv",
"bfxil x4, x22, #0, #16"
] ]
}, },
"sar eax, cl": { "sar eax, cl": {

116
unittests/InstructionCountCI/FlagM/Secondary.json
View File

@ -633,11 +633,11 @@
"lsl x22, x21, #1", "lsl x22, x21, #1",
"lsr w20, w20, #15", "lsr w20, w20, #15",
"orr x26, x22, x20", "orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"rmif x21, #14, #nzCv", "rmif x21, #14, #nzCv",
"eor w20, w26, w21", "eor w20, w26, w21",
"rmif x20, #15, #nzcV" "rmif x20, #15, #nzcV",
"bfxil x4, x26, #0, #16"
] ]
}, },
"shld ax, bx, 15": { "shld ax, bx, 15": {
@ -649,9 +649,9 @@
"lsl x22, x21, #15", "lsl x22, x21, #15",
"lsr w20, w20, #1", "lsr w20, w20, #1",
"orr x26, x22, x20", "orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"rmif x21, #0, #nzCv" "rmif x21, #0, #nzCv",
"bfxil x4, x26, #0, #16"
] ]
}, },
"shld ax, bx, 16": { "shld ax, bx, 16": {
@ -662,9 +662,9 @@
"uxth w21, w4", "uxth w21, w4",
"lsl x22, x21, #16", "lsl x22, x21, #16",
"orr x26, x22, x20", "orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"rmif x21, #63, #nzCv" "rmif x21, #63, #nzCv",
"bfxil x4, x26, #0, #16"
] ]
}, },
"shld ax, bx, 31": { "shld ax, bx, 31": {
@ -676,9 +676,9 @@
"lsl x22, x21, #31", "lsl x22, x21, #31",
"lsr w20, w20, #17", "lsr w20, w20, #17",
"orr x26, x22, x20", "orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"rmif x21, #0, #nzCv" "rmif x21, #0, #nzCv",
"bfxil x4, x26, #0, #16"
] ]
}, },
"shld eax, ebx, 1": { "shld eax, ebx, 1": {
@ -687,12 +687,12 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w7", "mov w20, w7",
"mov w21, w4", "mov w21, w4",
"extr w4, w21, w20, #31", "extr w26, w21, w20, #31",
"tst w4, w4", "tst w26, w26",
"rmif x21, #30, #nzCv", "rmif x21, #30, #nzCv",
"mov x26, x4", "eor w20, w26, w21",
"eor w20, w4, w21", "rmif x20, #31, #nzcV",
"rmif x20, #31, #nzcV" "mov x4, x26"
] ]
}, },
"shld eax, ebx, 15": { "shld eax, ebx, 15": {
@ -701,10 +701,10 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w7", "mov w20, w7",
"mov w21, w4", "mov w21, w4",
"extr w4, w21, w20, #17", "extr w26, w21, w20, #17",
"tst w4, w4", "tst w26, w26",
"rmif x21, #16, #nzCv", "rmif x21, #16, #nzCv",
"mov x26, x4" "mov x4, x26"
] ]
}, },
"shld eax, ebx, 16": { "shld eax, ebx, 16": {
@ -713,10 +713,10 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w7", "mov w20, w7",
"mov w21, w4", "mov w21, w4",
"extr w4, w21, w20, #16", "extr w26, w21, w20, #16",
"tst w4, w4", "tst w26, w26",
"rmif x21, #15, #nzCv", "rmif x21, #15, #nzCv",
"mov x26, x4" "mov x4, x26"
] ]
}, },
"shld eax, ebx, 31": { "shld eax, ebx, 31": {
@ -725,56 +725,52 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w7", "mov w20, w7",
"mov w21, w4", "mov w21, w4",
"extr w4, w21, w20, #1", "extr w26, w21, w20, #1",
"tst w4, w4", "tst w26, w26",
"rmif x21, #0, #nzCv", "rmif x21, #0, #nzCv",
"mov x26, x4" "mov x4, x26"
] ]
}, },
"shld rax, rbx, 1": { "shld rax, rbx, 1": {
"ExpectedInstructionCount": 7, "ExpectedInstructionCount": 6,
"Comment": "0x0f 0xac", "Comment": "0x0f 0xac",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "extr x26, x4, x7, #63",
"extr x4, x20, x7, #63", "tst x26, x26",
"tst x4, x4", "rmif x4, #62, #nzCv",
"rmif x20, #62, #nzCv", "eor x20, x26, x4",
"mov x26, x4", "rmif x20, #63, #nzcV",
"eor x20, x4, x20", "mov x4, x26"
"rmif x20, #63, #nzcV"
] ]
}, },
"shld rax, rbx, 15": { "shld rax, rbx, 15": {
"ExpectedInstructionCount": 5, "ExpectedInstructionCount": 4,
"Comment": "0x0f 0xac", "Comment": "0x0f 0xac",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "extr x26, x4, x7, #49",
"extr x4, x20, x7, #49", "tst x26, x26",
"tst x4, x4", "rmif x4, #48, #nzCv",
"rmif x20, #48, #nzCv", "mov x4, x26"
"mov x26, x4"
] ]
}, },
"shld rax, rbx, 32": { "shld rax, rbx, 32": {
"ExpectedInstructionCount": 5, "ExpectedInstructionCount": 4,
"Comment": "0x0f 0xac", "Comment": "0x0f 0xac",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "extr x26, x4, x7, #32",
"extr x4, x20, x7, #32", "tst x26, x26",
"tst x4, x4", "rmif x4, #31, #nzCv",
"rmif x20, #31, #nzCv", "mov x4, x26"
"mov x26, x4"
] ]
}, },
"shld rax, rbx, 63": { "shld rax, rbx, 63": {
"ExpectedInstructionCount": 5, "ExpectedInstructionCount": 4,
"Comment": "0x0f 0xac", "Comment": "0x0f 0xac",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "extr x26, x4, x7, #1",
"extr x4, x20, x7, #1", "tst x26, x26",
"tst x4, x4", "rmif x4, #0, #nzCv",
"rmif x20, #0, #nzCv", "mov x4, x26"
"mov x26, x4"
] ]
}, },
"shld ax, bx, cl": { "shld ax, bx, cl": {
@ -792,7 +788,6 @@
"mrs x23, nzcv", "mrs x23, nzcv",
"cmp x22, #0x0 (0)", "cmp x22, #0x0 (0)",
"csel x20, x21, x20, eq", "csel x20, x21, x20, eq",
"bfxil x4, x20, #0, #16",
"msr nzcv, x23", "msr nzcv, x23",
"cbz w22, #+0x24", "cbz w22, #+0x24",
"cmn wzr, w20, lsl #16", "cmn wzr, w20, lsl #16",
@ -802,7 +797,8 @@
"lsr w0, w21, w0", "lsr w0, w21, w0",
"eor w2, w21, w20", "eor w2, w21, w20",
"rmif x0, #63, #nzCv", "rmif x0, #63, #nzCv",
"rmif x2, #15, #nzcV" "rmif x2, #15, #nzcV",
"bfxil x4, x20, #0, #16"
] ]
}, },
"shld eax, ebx, cl": { "shld eax, ebx, cl": {
@ -819,7 +815,6 @@
"mrs x23, nzcv", "mrs x23, nzcv",
"cmp x22, #0x0 (0)", "cmp x22, #0x0 (0)",
"csel x20, x21, x20, eq", "csel x20, x21, x20, eq",
"mov w4, w20",
"msr nzcv, x23", "msr nzcv, x23",
"cbz w22, #+0x1c", "cbz w22, #+0x1c",
"ands w26, w20, w20", "ands w26, w20, w20",
@ -827,7 +822,8 @@
"lsr w0, w21, w0", "lsr w0, w21, w0",
"eor w2, w21, w20", "eor w2, w21, w20",
"rmif x0, #63, #nzCv", "rmif x0, #63, #nzCv",
"rmif x2, #31, #nzcV" "rmif x2, #31, #nzcV",
"mov w4, w20"
] ]
}, },
"shld rax, rbx, cl": { "shld rax, rbx, cl": {
@ -1105,12 +1101,12 @@
"mov w1, w21", "mov w1, w21",
"casalb w1, w20, [x4]", "casalb w1, w20, [x4]",
"mov w20, w1", "mov w20, w1",
"bfxil x4, x20, #0, #8",
"eor w27, w21, w20", "eor w27, w21, w20",
"lsl w0, w21, #24", "lsl w0, w21, #24",
"cmp w0, w20, lsl #24", "cmp w0, w20, lsl #24",
"sub w26, w21, w20", "sub w26, w21, w20",
"cfinv" "cfinv",
"bfxil x4, x20, #0, #8"
] ]
}, },
"cmpxchg ax, bx": { "cmpxchg ax, bx": {
@ -1137,12 +1133,12 @@
"mov w1, w21", "mov w1, w21",
"casalh w1, w20, [x4]", "casalh w1, w20, [x4]",
"mov w20, w1", "mov w20, w1",
"bfxil x4, x20, #0, #16",
"eor w27, w21, w20", "eor w27, w21, w20",
"lsl w0, w21, #16", "lsl w0, w21, #16",
"cmp w0, w20, lsl #16", "cmp w0, w20, lsl #16",
"sub w26, w21, w20", "sub w26, w21, w20",
"cfinv" "cfinv",
"bfxil x4, x20, #0, #16"
] ]
}, },
"cmpxchg eax, ebx": { "cmpxchg eax, ebx": {
@ -1530,11 +1526,11 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxtb w20, w7", "uxtb w20, w7",
"ldaddalb w20, w21, [x4]", "ldaddalb w20, w21, [x4]",
"bfxil x7, x21, #0, #8",
"eor w27, w21, w20", "eor w27, w21, w20",
"lsl w0, w21, #24", "lsl w0, w21, #24",
"cmn w0, w20, lsl #24", "cmn w0, w20, lsl #24",
"add w26, w21, w20" "add w26, w21, w20",
"bfxil x7, x21, #0, #8"
] ]
}, },
"xadd ax, bx": { "xadd ax, bx": {
@ -1557,11 +1553,11 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxth w20, w7", "uxth w20, w7",
"ldaddalh w20, w21, [x4]", "ldaddalh w20, w21, [x4]",
"bfxil x7, x21, #0, #16",
"eor w27, w21, w20", "eor w27, w21, w20",
"lsl w0, w21, #16", "lsl w0, w21, #16",
"cmn w0, w20, lsl #16", "cmn w0, w20, lsl #16",
"add w26, w21, w20" "add w26, w21, w20",
"bfxil x7, x21, #0, #16"
] ]
}, },
"xadd eax, ebx": { "xadd eax, ebx": {

222
unittests/InstructionCountCI/PrimaryGroup.json
View File

@ -1069,12 +1069,12 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxtb w20, w4", "uxtb w20, w4",
"lsl w26, w20, #2", "lsl w26, w20, #2",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24", "cmn wzr, w26, lsl #24",
"ubfx x20, x20, #6, #1", "ubfx x20, x20, #6, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"msr nzcv, x20" "msr nzcv, x20",
"bfxil x4, x26, #0, #8"
] ]
}, },
"shr al, 2": { "shr al, 2": {
@ -1083,12 +1083,12 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxtb w20, w4", "uxtb w20, w4",
"lsr w26, w20, #2", "lsr w26, w20, #2",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24", "cmn wzr, w26, lsl #24",
"ubfx x20, x20, #1, #1", "ubfx x20, x20, #1, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"msr nzcv, x20" "msr nzcv, x20",
"bfxil x4, x26, #0, #8"
] ]
}, },
"sar al, 2": { "sar al, 2": {
@ -1098,12 +1098,12 @@
"uxtb w20, w4", "uxtb w20, w4",
"sxtb x20, w20", "sxtb x20, w20",
"asr x26, x20, #2", "asr x26, x20, #2",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24", "cmn wzr, w26, lsl #24",
"ubfx x20, x20, #1, #1", "ubfx x20, x20, #1, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"msr nzcv, x20" "msr nzcv, x20",
"bfxil x4, x26, #0, #8"
] ]
}, },
"rol ax, 2": { "rol ax, 2": {
@ -1290,12 +1290,12 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxth w20, w4", "uxth w20, w4",
"lsl w26, w20, #2", "lsl w26, w20, #2",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"ubfx x20, x20, #14, #1", "ubfx x20, x20, #14, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"msr nzcv, x20" "msr nzcv, x20",
"bfxil x4, x26, #0, #16"
] ]
}, },
"shl eax, 2": { "shl eax, 2": {
@ -1303,27 +1303,26 @@
"Comment": "GROUP2 0xC1 /4", "Comment": "GROUP2 0xC1 /4",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w4", "mov w20, w4",
"lsl w4, w20, #2", "lsl w26, w20, #2",
"tst w4, w4", "tst w26, w26",
"ubfx x20, x20, #30, #1", "ubfx x20, x20, #30, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"mov x26, x4", "msr nzcv, x20",
"msr nzcv, x20" "mov x4, x26"
] ]
}, },
"shl rax, 2": { "shl rax, 2": {
"ExpectedInstructionCount": 8, "ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xC1 /4", "Comment": "GROUP2 0xC1 /4",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "lsl x26, x4, #2",
"lsl x4, x20, #2", "tst x26, x26",
"tst x4, x4", "ubfx x20, x4, #62, #1",
"ubfx x20, x20, #62, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"mov x26, x4", "msr nzcv, x20",
"msr nzcv, x20" "mov x4, x26"
] ]
}, },
"shr ax, 2": { "shr ax, 2": {
@ -1332,12 +1331,12 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxth w20, w4", "uxth w20, w4",
"lsr w26, w20, #2", "lsr w26, w20, #2",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"ubfx x20, x20, #1, #1", "ubfx x20, x20, #1, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"msr nzcv, x20" "msr nzcv, x20",
"bfxil x4, x26, #0, #16"
] ]
}, },
"shr eax, 2": { "shr eax, 2": {
@ -1345,27 +1344,26 @@
"Comment": "GROUP2 0xC1 /5", "Comment": "GROUP2 0xC1 /5",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w4", "mov w20, w4",
"lsr w4, w20, #2", "lsr w26, w20, #2",
"tst w4, w4", "tst w26, w26",
"ubfx x20, x20, #1, #1", "ubfx x20, x20, #1, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"mov x26, x4", "msr nzcv, x20",
"msr nzcv, x20" "mov x4, x26"
] ]
}, },
"shr rax, 2": { "shr rax, 2": {
"ExpectedInstructionCount": 8, "ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xC1 /5", "Comment": "GROUP2 0xC1 /5",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "lsr x26, x4, #2",
"lsr x4, x20, #2", "tst x26, x26",
"tst x4, x4", "ubfx x20, x4, #1, #1",
"ubfx x20, x20, #1, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"mov x26, x4", "msr nzcv, x20",
"msr nzcv, x20" "mov x4, x26"
] ]
}, },
"sar ax, 2": { "sar ax, 2": {
@ -1375,12 +1373,12 @@
"uxth w20, w4", "uxth w20, w4",
"sxth x20, w20", "sxth x20, w20",
"asr x26, x20, #2", "asr x26, x20, #2",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"ubfx x20, x20, #1, #1", "ubfx x20, x20, #1, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"msr nzcv, x20" "msr nzcv, x20",
"bfxil x4, x26, #0, #16"
] ]
}, },
"sar eax, 2": { "sar eax, 2": {
@ -1388,27 +1386,26 @@
"Comment": "GROUP2 0xC1 /7", "Comment": "GROUP2 0xC1 /7",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w4", "mov w20, w4",
"asr w4, w20, #2", "asr w26, w20, #2",
"tst w4, w4", "tst w26, w26",
"ubfx x20, x20, #1, #1", "ubfx x20, x20, #1, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"mov x26, x4", "msr nzcv, x20",
"msr nzcv, x20" "mov x4, x26"
] ]
}, },
"sar rax, 2": { "sar rax, 2": {
"ExpectedInstructionCount": 8, "ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xC1 /7", "Comment": "GROUP2 0xC1 /7",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "asr x26, x4, #2",
"asr x4, x20, #2", "tst x26, x26",
"tst x4, x4", "ubfx x20, x4, #1, #1",
"ubfx x20, x20, #1, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"mov x26, x4", "msr nzcv, x20",
"msr nzcv, x20" "mov x4, x26"
] ]
}, },
"rol al, 1": { "rol al, 1": {
@ -1455,7 +1452,6 @@
"uxtb w20, w4", "uxtb w20, w4",
"cset w21, hs", "cset w21, hs",
"orr w21, w21, w20, lsl #1", "orr w21, w21, w20, lsl #1",
"bfxil x4, x21, #0, #8",
"ubfx x22, x20, #7, #1", "ubfx x22, x20, #7, #1",
"mrs x23, nzcv", "mrs x23, nzcv",
"mov w0, w23", "mov w0, w23",
@ -1466,6 +1462,7 @@
"mov w0, w22", "mov w0, w22",
"bfi w0, w20, #28, #1", "bfi w0, w20, #28, #1",
"mov w20, w0", "mov w20, w0",
"bfxil x4, x21, #0, #8",
"msr nzcv, x20" "msr nzcv, x20"
] ]
}, },
@ -1497,7 +1494,6 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxtb w20, w4", "uxtb w20, w4",
"lsl w26, w20, #1", "lsl w26, w20, #1",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24", "cmn wzr, w26, lsl #24",
"ubfx x21, x20, #7, #1", "ubfx x21, x20, #7, #1",
"mrs x22, nzcv", "mrs x22, nzcv",
@ -1505,7 +1501,8 @@
"eor w20, w26, w20", "eor w20, w26, w20",
"ubfx x20, x20, #7, #1", "ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28", "orr w20, w21, w20, lsl #28",
"msr nzcv, x20" "msr nzcv, x20",
"bfxil x4, x26, #0, #8"
] ]
}, },
"shr al, 1": { "shr al, 1": {
@ -1514,14 +1511,14 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxtb w20, w4", "uxtb w20, w4",
"lsr w26, w20, #1", "lsr w26, w20, #1",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24", "cmn wzr, w26, lsl #24",
"ubfx x21, x20, #0, #1", "ubfx x21, x20, #0, #1",
"mrs x22, nzcv", "mrs x22, nzcv",
"orr w21, w22, w21, lsl #29", "orr w21, w22, w21, lsl #29",
"ubfx x20, x20, #7, #1", "ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28", "orr w20, w21, w20, lsl #28",
"msr nzcv, x20" "msr nzcv, x20",
"bfxil x4, x26, #0, #8"
] ]
}, },
"sar al, 1": { "sar al, 1": {
@ -1531,12 +1528,12 @@
"uxtb w20, w4", "uxtb w20, w4",
"sxtb x20, w20", "sxtb x20, w20",
"asr x26, x20, #1", "asr x26, x20, #1",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24", "cmn wzr, w26, lsl #24",
"ubfx x20, x20, #0, #1", "ubfx x20, x20, #0, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"msr nzcv, x20" "msr nzcv, x20",
"bfxil x4, x26, #0, #8"
] ]
}, },
"rol ax, 1": { "rol ax, 1": {
@ -1642,7 +1639,6 @@
"uxth w20, w4", "uxth w20, w4",
"cset w21, hs", "cset w21, hs",
"orr w21, w21, w20, lsl #1", "orr w21, w21, w20, lsl #1",
"bfxil x4, x21, #0, #16",
"ubfx x22, x20, #15, #1", "ubfx x22, x20, #15, #1",
"mrs x23, nzcv", "mrs x23, nzcv",
"mov w0, w23", "mov w0, w23",
@ -1653,6 +1649,7 @@
"mov w0, w22", "mov w0, w22",
"bfi w0, w20, #28, #1", "bfi w0, w20, #28, #1",
"mov w20, w0", "mov w20, w0",
"bfxil x4, x21, #0, #16",
"msr nzcv, x20" "msr nzcv, x20"
] ]
}, },
@ -1761,7 +1758,6 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxth w20, w4", "uxth w20, w4",
"lsl w26, w20, #1", "lsl w26, w20, #1",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"ubfx x21, x20, #15, #1", "ubfx x21, x20, #15, #1",
"mrs x22, nzcv", "mrs x22, nzcv",
@ -1769,7 +1765,8 @@
"eor w20, w26, w20", "eor w20, w26, w20",
"ubfx x20, x20, #15, #1", "ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28", "orr w20, w21, w20, lsl #28",
"msr nzcv, x20" "msr nzcv, x20",
"bfxil x4, x26, #0, #16"
] ]
}, },
"shl eax, 1": { "shl eax, 1": {
@ -1777,33 +1774,32 @@
"Comment": "GROUP2 0xd1 /4", "Comment": "GROUP2 0xd1 /4",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w4", "mov w20, w4",
"lsl w4, w20, #1", "lsl w26, w20, #1",
"tst w4, w4", "tst w26, w26",
"ubfx x21, x20, #31, #1", "ubfx x21, x20, #31, #1",
"mrs x22, nzcv", "mrs x22, nzcv",
"orr w21, w22, w21, lsl #29", "orr w21, w22, w21, lsl #29",
"mov x26, x4", "eor w20, w26, w20",
"eor w20, w4, w20",
"ubfx x20, x20, #31, #1", "ubfx x20, x20, #31, #1",
"orr w20, w21, w20, lsl #28", "orr w20, w21, w20, lsl #28",
"msr nzcv, x20" "msr nzcv, x20",
"mov x4, x26"
] ]
}, },
"shl rax, 1": { "shl rax, 1": {
"ExpectedInstructionCount": 11, "ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd1 /4", "Comment": "GROUP2 0xd1 /4",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "lsl x26, x4, #1",
"lsl x4, x20, #1", "tst x26, x26",
"tst x4, x4", "lsr x20, x4, #63",
"lsr x21, x20, #63", "mrs x21, nzcv",
"mrs x22, nzcv", "orr w20, w21, w20, lsl #29",
"orr w21, w22, w21, lsl #29", "eor x21, x26, x4",
"mov x26, x4", "lsr x21, x21, #63",
"eor x20, x4, x20", "orr w20, w20, w21, lsl #28",
"lsr x20, x20, #63", "msr nzcv, x20",
"orr w20, w21, w20, lsl #28", "mov x4, x26"
"msr nzcv, x20"
] ]
}, },
"shr ax, 1": { "shr ax, 1": {
@ -1812,14 +1808,14 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxth w20, w4", "uxth w20, w4",
"lsr w26, w20, #1", "lsr w26, w20, #1",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"ubfx x21, x20, #0, #1", "ubfx x21, x20, #0, #1",
"mrs x22, nzcv", "mrs x22, nzcv",
"orr w21, w22, w21, lsl #29", "orr w21, w22, w21, lsl #29",
"ubfx x20, x20, #15, #1", "ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28", "orr w20, w21, w20, lsl #28",
"msr nzcv, x20" "msr nzcv, x20",
"bfxil x4, x26, #0, #16"
] ]
}, },
"shr eax, 1": { "shr eax, 1": {
@ -1827,31 +1823,30 @@
"Comment": "GROUP2 0xd1 /5", "Comment": "GROUP2 0xd1 /5",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w4", "mov w20, w4",
"lsr w4, w20, #1", "lsr w26, w20, #1",
"tst w4, w4", "tst w26, w26",
"ubfx x21, x20, #0, #1", "ubfx x21, x20, #0, #1",
"mrs x22, nzcv", "mrs x22, nzcv",
"orr w21, w22, w21, lsl #29", "orr w21, w22, w21, lsl #29",
"mov x26, x4",
"ubfx x20, x20, #31, #1", "ubfx x20, x20, #31, #1",
"orr w20, w21, w20, lsl #28", "orr w20, w21, w20, lsl #28",
"msr nzcv, x20" "msr nzcv, x20",
"mov x4, x26"
] ]
}, },
"shr rax, 1": { "shr rax, 1": {
"ExpectedInstructionCount": 10, "ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd1 /5", "Comment": "GROUP2 0xd1 /5",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "lsr x26, x4, #1",
"lsr x4, x20, #1", "tst x26, x26",
"tst x4, x4", "ubfx x20, x4, #0, #1",
"ubfx x21, x20, #0, #1", "mrs x21, nzcv",
"mrs x22, nzcv", "orr w20, w21, w20, lsl #29",
"orr w21, w22, w21, lsl #29", "lsr x21, x4, #63",
"mov x26, x4", "orr w20, w20, w21, lsl #28",
"lsr x20, x20, #63", "msr nzcv, x20",
"orr w20, w21, w20, lsl #28", "mov x4, x26"
"msr nzcv, x20"
] ]
}, },
"sar ax, 1": { "sar ax, 1": {
@ -1861,12 +1856,12 @@
"uxth w20, w4", "uxth w20, w4",
"sxth x20, w20", "sxth x20, w20",
"asr x26, x20, #1", "asr x26, x20, #1",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"ubfx x20, x20, #0, #1", "ubfx x20, x20, #0, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"msr nzcv, x20" "msr nzcv, x20",
"bfxil x4, x26, #0, #16"
] ]
}, },
"sar eax, 1": { "sar eax, 1": {
@ -1874,27 +1869,26 @@
"Comment": "GROUP2 0xd1 /7", "Comment": "GROUP2 0xd1 /7",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w4", "mov w20, w4",
"asr w4, w20, #1", "asr w26, w20, #1",
"tst w4, w4", "tst w26, w26",
"ubfx x20, x20, #0, #1", "ubfx x20, x20, #0, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"mov x26, x4", "msr nzcv, x20",
"msr nzcv, x20" "mov x4, x26"
] ]
}, },
"sar rax, 1": { "sar rax, 1": {
"ExpectedInstructionCount": 8, "ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd1 /7", "Comment": "GROUP2 0xd1 /7",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "asr x26, x4, #1",
"asr x4, x20, #1", "tst x26, x26",
"tst x4, x4", "ubfx x20, x4, #0, #1",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"mov x26, x4", "msr nzcv, x20",
"msr nzcv, x20" "mov x4, x26"
] ]
}, },
"rol al, cl": { "rol al, cl": {
@ -2018,7 +2012,6 @@
"uxtb w20, w4", "uxtb w20, w4",
"uxtb w21, w5", "uxtb w21, w5",
"lsl w22, w20, w21", "lsl w22, w20, w21",
"bfxil x4, x22, #0, #8",
"cbz w21, #+0x30", "cbz w21, #+0x30",
"cmn wzr, w22, lsl #24", "cmn wzr, w22, lsl #24",
"mov x26, x22", "mov x26, x22",
@ -2030,7 +2023,8 @@
"bfi w1, w0, #29, #1", "bfi w1, w0, #29, #1",
"lsr w2, w2, #7", "lsr w2, w2, #7",
"bfi w1, w2, #28, #1", "bfi w1, w2, #28, #1",
"msr nzcv, x1" "msr nzcv, x1",
"bfxil x4, x22, #0, #8"
] ]
}, },
"shr al, cl": { "shr al, cl": {
@ -2040,7 +2034,6 @@
"uxtb w20, w4", "uxtb w20, w4",
"uxtb w21, w5", "uxtb w21, w5",
"lsr w22, w20, w21", "lsr w22, w20, w21",
"bfxil x4, x22, #0, #8",
"cbz w21, #+0x2c", "cbz w21, #+0x2c",
"cmn wzr, w22, lsl #24", "cmn wzr, w22, lsl #24",
"mov x26, x22", "mov x26, x22",
@ -2051,7 +2044,8 @@
"bfi w1, w0, #29, #1", "bfi w1, w0, #29, #1",
"lsr w2, w2, #7", "lsr w2, w2, #7",
"bfi w1, w2, #28, #1", "bfi w1, w2, #28, #1",
"msr nzcv, x1" "msr nzcv, x1",
"bfxil x4, x22, #0, #8"
] ]
}, },
"sar al, cl": { "sar al, cl": {
@ -2062,7 +2056,6 @@
"uxtb w21, w5", "uxtb w21, w5",
"sxtb x20, w20", "sxtb x20, w20",
"asr w22, w20, w21", "asr w22, w20, w21",
"bfxil x4, x22, #0, #8",
"cbz w21, #+0x20", "cbz w21, #+0x20",
"cmn wzr, w22, lsl #24", "cmn wzr, w22, lsl #24",
"mov x26, x22", "mov x26, x22",
@ -2070,7 +2063,8 @@
"lsr w0, w20, w0", "lsr w0, w20, w0",
"mrs x1, nzcv", "mrs x1, nzcv",
"bfi w1, w0, #29, #1", "bfi w1, w0, #29, #1",
"msr nzcv, x1" "msr nzcv, x1",
"bfxil x4, x22, #0, #8"
] ]
}, },
"rol ax, cl": { "rol ax, cl": {
@ -2369,7 +2363,6 @@
"uxth w20, w4", "uxth w20, w4",
"uxth w21, w5", "uxth w21, w5",
"lsl w22, w20, w21", "lsl w22, w20, w21",
"bfxil x4, x22, #0, #16",
"cbz w21, #+0x30", "cbz w21, #+0x30",
"cmn wzr, w22, lsl #16", "cmn wzr, w22, lsl #16",
"mov x26, x22", "mov x26, x22",
@ -2381,7 +2374,8 @@
"bfi w1, w0, #29, #1", "bfi w1, w0, #29, #1",
"lsr w2, w2, #15", "lsr w2, w2, #15",
"bfi w1, w2, #28, #1", "bfi w1, w2, #28, #1",
"msr nzcv, x1" "msr nzcv, x1",
"bfxil x4, x22, #0, #16"
] ]
}, },
"shl eax, cl": { "shl eax, cl": {
@ -2428,7 +2422,6 @@
"uxth w20, w4", "uxth w20, w4",
"uxth w21, w5", "uxth w21, w5",
"lsr w22, w20, w21", "lsr w22, w20, w21",
"bfxil x4, x22, #0, #16",
"cbz w21, #+0x2c", "cbz w21, #+0x2c",
"cmn wzr, w22, lsl #16", "cmn wzr, w22, lsl #16",
"mov x26, x22", "mov x26, x22",
@ -2439,7 +2432,8 @@
"bfi w1, w0, #29, #1", "bfi w1, w0, #29, #1",
"lsr w2, w2, #15", "lsr w2, w2, #15",
"bfi w1, w2, #28, #1", "bfi w1, w2, #28, #1",
"msr nzcv, x1" "msr nzcv, x1",
"bfxil x4, x22, #0, #16"
] ]
}, },
"shr eax, cl": { "shr eax, cl": {
@ -2487,7 +2481,6 @@
"uxth w21, w5", "uxth w21, w5",
"sxth x20, w20", "sxth x20, w20",
"asr w22, w20, w21", "asr w22, w20, w21",
"bfxil x4, x22, #0, #16",
"cbz w21, #+0x20", "cbz w21, #+0x20",
"cmn wzr, w22, lsl #16", "cmn wzr, w22, lsl #16",
"mov x26, x22", "mov x26, x22",
@ -2495,7 +2488,8 @@
"lsr w0, w20, w0", "lsr w0, w20, w0",
"mrs x1, nzcv", "mrs x1, nzcv",
"bfi w1, w0, #29, #1", "bfi w1, w0, #29, #1",
"msr nzcv, x1" "msr nzcv, x1",
"bfxil x4, x22, #0, #16"
] ]
}, },
"sar eax, cl": { "sar eax, cl": {

144
unittests/InstructionCountCI/Secondary.json
View File

@ -1392,7 +1392,6 @@
"lsl x22, x21, #1", "lsl x22, x21, #1",
"lsr w20, w20, #15", "lsr w20, w20, #15",
"orr x26, x22, x20", "orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"ubfx x20, x21, #15, #1", "ubfx x20, x21, #15, #1",
"mrs x22, nzcv", "mrs x22, nzcv",
@ -1400,7 +1399,8 @@
"eor w21, w26, w21", "eor w21, w26, w21",
"ubfx x21, x21, #15, #1", "ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28", "orr w20, w20, w21, lsl #28",
"msr nzcv, x20" "msr nzcv, x20",
"bfxil x4, x26, #0, #16"
] ]
}, },
"shld ax, bx, 15": { "shld ax, bx, 15": {
@ -1412,12 +1412,12 @@
"lsl x22, x21, #15", "lsl x22, x21, #15",
"lsr w20, w20, #1", "lsr w20, w20, #1",
"orr x26, x22, x20", "orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"ubfx x20, x21, #1, #1", "ubfx x20, x21, #1, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"msr nzcv, x20" "msr nzcv, x20",
"bfxil x4, x26, #0, #16"
] ]
}, },
"shld ax, bx, 16": { "shld ax, bx, 16": {
@ -1428,12 +1428,12 @@
"uxth w21, w4", "uxth w21, w4",
"lsl x22, x21, #16", "lsl x22, x21, #16",
"orr x26, x22, x20", "orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"ubfx x20, x21, #0, #1", "ubfx x20, x21, #0, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"msr nzcv, x20" "msr nzcv, x20",
"bfxil x4, x26, #0, #16"
] ]
}, },
"shld ax, bx, 31": { "shld ax, bx, 31": {
@ -1445,12 +1445,12 @@
"lsl x22, x21, #31", "lsl x22, x21, #31",
"lsr w20, w20, #17", "lsr w20, w20, #17",
"orr x26, x22, x20", "orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16", "cmn wzr, w26, lsl #16",
"ubfx x20, x21, #1, #1", "ubfx x20, x21, #1, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"msr nzcv, x20" "msr nzcv, x20",
"bfxil x4, x26, #0, #16"
] ]
}, },
"shld eax, ebx, 0": { "shld eax, ebx, 0": {
@ -1466,16 +1466,16 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w7", "mov w20, w7",
"mov w21, w4", "mov w21, w4",
"extr w4, w21, w20, #31", "extr w26, w21, w20, #31",
"tst w4, w4", "tst w26, w26",
"ubfx x20, x21, #31, #1", "ubfx x20, x21, #31, #1",
"mrs x22, nzcv", "mrs x22, nzcv",
"orr w20, w22, w20, lsl #29", "orr w20, w22, w20, lsl #29",
"mov x26, x4", "eor w21, w26, w21",
"eor w21, w4, w21",
"ubfx x21, x21, #31, #1", "ubfx x21, x21, #31, #1",
"orr w20, w20, w21, lsl #28", "orr w20, w20, w21, lsl #28",
"msr nzcv, x20" "msr nzcv, x20",
"mov x4, x26"
] ]
}, },
"shld eax, ebx, 15": { "shld eax, ebx, 15": {
@ -1484,13 +1484,13 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w7", "mov w20, w7",
"mov w21, w4", "mov w21, w4",
"extr w4, w21, w20, #17", "extr w26, w21, w20, #17",
"tst w4, w4", "tst w26, w26",
"ubfx x20, x21, #17, #1", "ubfx x20, x21, #17, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"mov x26, x4", "msr nzcv, x20",
"msr nzcv, x20" "mov x4, x26"
] ]
}, },
"shld eax, ebx, 16": { "shld eax, ebx, 16": {
@ -1499,13 +1499,13 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w7", "mov w20, w7",
"mov w21, w4", "mov w21, w4",
"extr w4, w21, w20, #16", "extr w26, w21, w20, #16",
"tst w4, w4", "tst w26, w26",
"ubfx x20, x21, #16, #1", "ubfx x20, x21, #16, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"mov x26, x4", "msr nzcv, x20",
"msr nzcv, x20" "mov x4, x26"
] ]
}, },
"shld eax, ebx, 31": { "shld eax, ebx, 31": {
@ -1514,13 +1514,13 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w7", "mov w20, w7",
"mov w21, w4", "mov w21, w4",
"extr w4, w21, w20, #1", "extr w26, w21, w20, #1",
"tst w4, w4", "tst w26, w26",
"ubfx x20, x21, #1, #1", "ubfx x20, x21, #1, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"mov x26, x4", "msr nzcv, x20",
"msr nzcv, x20" "mov x4, x26"
] ]
}, },
"shld rax, rbx, 0": { "shld rax, rbx, 0": {
@ -1529,62 +1529,58 @@
"ExpectedArm64ASM": [] "ExpectedArm64ASM": []
}, },
"shld rax, rbx, 1": { "shld rax, rbx, 1": {
"ExpectedInstructionCount": 11, "ExpectedInstructionCount": 10,
"Comment": "0x0f 0xac", "Comment": "0x0f 0xac",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "extr x26, x4, x7, #63",
"extr x4, x20, x7, #63", "tst x26, x26",
"tst x4, x4", "lsr x20, x4, #63",
"lsr x21, x20, #63", "mrs x21, nzcv",
"mrs x22, nzcv", "orr w20, w21, w20, lsl #29",
"orr w21, w22, w21, lsl #29", "eor x21, x26, x4",
"mov x26, x4", "lsr x21, x21, #63",
"eor x20, x4, x20", "orr w20, w20, w21, lsl #28",
"lsr x20, x20, #63", "msr nzcv, x20",
"orr w20, w21, w20, lsl #28", "mov x4, x26"
"msr nzcv, x20"
] ]
}, },
"shld rax, rbx, 15": { "shld rax, rbx, 15": {
"ExpectedInstructionCount": 8, "ExpectedInstructionCount": 7,
"Comment": "0x0f 0xac", "Comment": "0x0f 0xac",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "extr x26, x4, x7, #49",
"extr x4, x20, x7, #49", "tst x26, x26",
"tst x4, x4", "ubfx x20, x4, #49, #1",
"ubfx x20, x20, #49, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"mov x26, x4", "msr nzcv, x20",
"msr nzcv, x20" "mov x4, x26"
] ]
}, },
"shld rax, rbx, 32": { "shld rax, rbx, 32": {
"ExpectedInstructionCount": 8, "ExpectedInstructionCount": 7,
"Comment": "0x0f 0xac", "Comment": "0x0f 0xac",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "extr x26, x4, x7, #32",
"extr x4, x20, x7, #32", "tst x26, x26",
"tst x4, x4", "ubfx x20, x4, #32, #1",
"ubfx x20, x20, #32, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"mov x26, x4", "msr nzcv, x20",
"msr nzcv, x20" "mov x4, x26"
] ]
}, },
"shld rax, rbx, 63": { "shld rax, rbx, 63": {
"ExpectedInstructionCount": 8, "ExpectedInstructionCount": 7,
"Comment": "0x0f 0xac", "Comment": "0x0f 0xac",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov x20, x4", "extr x26, x4, x7, #1",
"extr x4, x20, x7, #1", "tst x26, x26",
"tst x4, x4", "ubfx x20, x4, #1, #1",
"ubfx x20, x20, #1, #1",
"mrs x21, nzcv", "mrs x21, nzcv",
"orr w20, w21, w20, lsl #29", "orr w20, w21, w20, lsl #29",
"mov x26, x4", "msr nzcv, x20",
"msr nzcv, x20" "mov x4, x26"
] ]
}, },
"shld ax, bx, cl": { "shld ax, bx, cl": {
@ -1602,7 +1598,6 @@
"mrs x23, nzcv", "mrs x23, nzcv",
"cmp x22, #0x0 (0)", "cmp x22, #0x0 (0)",
"csel x20, x21, x20, eq", "csel x20, x21, x20, eq",
"bfxil x4, x20, #0, #16",
"msr nzcv, x23", "msr nzcv, x23",
"cbz w22, #+0x30", "cbz w22, #+0x30",
"cmn wzr, w20, lsl #16", "cmn wzr, w20, lsl #16",
@ -1615,7 +1610,8 @@
"bfi w1, w0, #29, #1", "bfi w1, w0, #29, #1",
"lsr w2, w2, #15", "lsr w2, w2, #15",
"bfi w1, w2, #28, #1", "bfi w1, w2, #28, #1",
"msr nzcv, x1" "msr nzcv, x1",
"bfxil x4, x20, #0, #16"
] ]
}, },
"shld eax, ebx, cl": { "shld eax, ebx, cl": {
@ -1632,7 +1628,6 @@
"mrs x23, nzcv", "mrs x23, nzcv",
"cmp x22, #0x0 (0)", "cmp x22, #0x0 (0)",
"csel x20, x21, x20, eq", "csel x20, x21, x20, eq",
"mov w4, w20",
"msr nzcv, x23", "msr nzcv, x23",
"cbz w22, #+0x28", "cbz w22, #+0x28",
"ands w26, w20, w20", "ands w26, w20, w20",
@ -1643,7 +1638,8 @@
"bfi w1, w0, #29, #1", "bfi w1, w0, #29, #1",
"lsr w2, w2, #31", "lsr w2, w2, #31",
"bfi w1, w2, #28, #1", "bfi w1, w2, #28, #1",
"msr nzcv, x1" "msr nzcv, x1",
"mov w4, w20"
] ]
}, },
"shld rax, rbx, cl": { "shld rax, rbx, cl": {
@ -1896,14 +1892,14 @@
"mov w1, w21", "mov w1, w21",
"casalb w1, w20, [x4]", "casalb w1, w20, [x4]",
"mov w20, w1", "mov w20, w1",
"bfxil x4, x20, #0, #8",
"eor w27, w21, w20", "eor w27, w21, w20",
"lsl w0, w21, #24", "lsl w0, w21, #24",
"cmp w0, w20, lsl #24", "cmp w0, w20, lsl #24",
"sub w26, w21, w20", "sub w26, w21, w20",
"mrs x20, nzcv", "mrs x21, nzcv",
"eor w20, w20, #0x20000000", "eor w21, w21, #0x20000000",
"msr nzcv, x20" "msr nzcv, x21",
"bfxil x4, x20, #0, #8"
] ]
}, },
"cmpxchg ax, bx": { "cmpxchg ax, bx": {
@ -1932,14 +1928,14 @@
"mov w1, w21", "mov w1, w21",
"casalh w1, w20, [x4]", "casalh w1, w20, [x4]",
"mov w20, w1", "mov w20, w1",
"bfxil x4, x20, #0, #16",
"eor w27, w21, w20", "eor w27, w21, w20",
"lsl w0, w21, #16", "lsl w0, w21, #16",
"cmp w0, w20, lsl #16", "cmp w0, w20, lsl #16",
"sub w26, w21, w20", "sub w26, w21, w20",
"mrs x20, nzcv", "mrs x21, nzcv",
"eor w20, w20, #0x20000000", "eor w21, w21, #0x20000000",
"msr nzcv, x20" "msr nzcv, x21",
"bfxil x4, x20, #0, #16"
] ]
}, },
"cmpxchg eax, ebx": { "cmpxchg eax, ebx": {
@ -2542,11 +2538,11 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxtb w20, w7", "uxtb w20, w7",
"ldaddalb w20, w21, [x4]", "ldaddalb w20, w21, [x4]",
"bfxil x7, x21, #0, #8",
"eor w27, w21, w20", "eor w27, w21, w20",
"lsl w0, w21, #24", "lsl w0, w21, #24",
"cmn w0, w20, lsl #24", "cmn w0, w20, lsl #24",
"add w26, w21, w20" "add w26, w21, w20",
"bfxil x7, x21, #0, #8"
] ]
}, },
"xadd ax, bx": { "xadd ax, bx": {
@ -2569,11 +2565,11 @@
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxth w20, w7", "uxth w20, w7",
"ldaddalh w20, w21, [x4]", "ldaddalh w20, w21, [x4]",
"bfxil x7, x21, #0, #16",
"eor w27, w21, w20", "eor w27, w21, w20",
"lsl w0, w21, #16", "lsl w0, w21, #16",
"cmn w0, w20, lsl #16", "cmn w0, w20, lsl #16",
"add w26, w21, w20" "add w26, w21, w20",
"bfxil x7, x21, #0, #16"
] ]
}, },
"xadd eax, ebx": { "xadd eax, ebx": {