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Merge pull request #3710 from Sonicadvance1/avx128_1

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CoreState: Move `InlineJITBlockHeader` to the start of the struct
This commit is contained in:
Ryan Houdek 2024-06-17 17:17:56 -07:00 committed by GitHub
commit 933d622860
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GPG Key ID: B5690EEEBB952194
18 changed files with 6211 additions and 6195 deletions
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47
FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp
View File

@ -88,6 +88,15 @@ struct ContextInfo {
static void ClassifyContextStruct(ContextInfo* ContextClassificationInfo, bool SupportsAVX) {
auto ContextClassification = &ContextClassificationInfo->ClassificationInfo;
ContextClassification->emplace_back(ContextMemberInfo {
ContextMemberClassification {
offsetof(FEXCore::Core::CPUState, InlineJITBlockHeader),
sizeof(FEXCore::Core::CPUState::InlineJITBlockHeader),
},
LastAccessType::INVALID,
FEXCore::IR::InvalidClass,
});
ContextClassification->emplace_back(ContextMemberInfo {
ContextMemberClassification {
offsetof(FEXCore::Core::CPUState, rip),
@ -225,15 +234,6 @@ static void ClassifyContextStruct(ContextInfo* ContextClassificationInfo, bool S
FEXCore::IR::InvalidClass,
});
ContextClassification->emplace_back(ContextMemberInfo {
ContextMemberClassification {
offsetof(FEXCore::Core::CPUState, InlineJITBlockHeader),
sizeof(FEXCore::Core::CPUState::InlineJITBlockHeader),
},
LastAccessType::INVALID,
FEXCore::IR::InvalidClass,
});
if (SupportsAVX) {
for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) {
ContextClassification->emplace_back(ContextMemberInfo {
@ -386,7 +386,14 @@ static void ResetClassificationAccesses(ContextInfo* ContextClassificationInfo,
ContextClassification->at(Offset).StoreNode = nullptr;
};
size_t Offset = 0;
///< InlineJITBlockHeader
SetAccess(Offset++, LastAccessType::INVALID);
///< rip
SetAccess(Offset++, LastAccessType::NONE);
///< gregs
for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_GPRS; ++i) {
SetAccess(Offset++, LastAccessType::NONE);
}
@ -410,37 +417,47 @@ static void ResetClassificationAccesses(ContextInfo* ContextClassificationInfo,
SetAccess(Offset++, LastAccessType::NONE);
SetAccess(Offset++, LastAccessType::NONE);
// Pad2
SetAccess(Offset++, LastAccessType::INVALID);
///< xmm
for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) {
SetAccess(Offset++, LastAccessType::NONE);
}
if (!SupportsAVX) {
///< xmm pad if AVX isn't supported.
SetAccess(Offset++, LastAccessType::NONE);
}
///< flags
for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_FLAGS; ++i) {
SetAccess(Offset++, LastAccessType::NONE);
}
// PF/AF
SetAccess(Offset++, LastAccessType::NONE);
///< pf_raw
SetAccess(Offset++, LastAccessType::NONE);
///< af_raw
SetAccess(Offset++, LastAccessType::NONE);
///< mm
for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_MMS; ++i) {
SetAccess(Offset++, LastAccessType::NONE);
}
///< gdt
for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_GDTS; ++i) {
SetAccess(Offset++, LastAccessType::NONE);
}
SetAccess(Offset++, LastAccessType::NONE);
///< FCW
SetAccess(Offset++, LastAccessType::NONE);
///< AbridgedFTW
SetAccess(Offset++, LastAccessType::NONE);
///< _pad2
SetAccess(Offset++, LastAccessType::INVALID);
///< DeferredSignalRefCount
SetAccess(Offset++, LastAccessType::INVALID);
}

3
FEXCore/include/FEXCore/Core/CoreState.h
View File

@ -88,6 +88,7 @@ struct CPUState {
SSE sse;
};
uint64_t InlineJITBlockHeader {};
uint64_t rip {}; ///< Current core's RIP. May not be entirely accurate while JIT is active
uint64_t gregs[16] {};
// Raw segment register indexes
@ -99,7 +100,6 @@ struct CPUState {
uint32_t es_cached {}, cs_cached {}, ss_cached {}, ds_cached {};
uint64_t gs_cached {};
uint64_t fs_cached {};
uint64_t InlineJITBlockHeader {};
XMMRegs xmm {};
uint8_t flags[48] {};
uint64_t pf_raw {};
@ -342,7 +342,6 @@ struct CpuStateFrame {
JITPointers Pointers;
};
static_assert(offsetof(CpuStateFrame, State) == 0, "CPUState must be first member in CpuStateFrame");
static_assert(offsetof(CpuStateFrame, State.rip) == 0, "rip must be zero offset in CpuStateFrame");
static_assert(offsetof(CpuStateFrame, Pointers) % 8 == 0, "JITPointers need to be aligned to 8 bytes");
static_assert(offsetof(CpuStateFrame, Pointers) + sizeof(CpuStateFrame::Pointers) <= 32760, "JITPointers maximum pointer needs to be less "
"than architecture maximum 32768");

16
unittests/InstructionCountCI/FlagM/HotBlocks.json
View File

@ -231,10 +231,10 @@
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #728]",
"stp x4, x5, [x28, #8]",
"stp x6, x7, [x28, #24]",
"str x8, [x28, #40]",
"stp x16, x17, [x28, #104]",
"stp x4, x5, [x28, #16]",
"stp x6, x7, [x28, #32]",
"str x8, [x28, #48]",
"stp x16, x17, [x28, #112]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
@ -249,10 +249,10 @@
"blr x5",
"ldr w4, [x28, #728]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #8]",
"ldp x6, x7, [x28, #24]",
"ldr x8, [x28, #40]",
"ldp x16, x17, [x28, #104]",
"ldp x4, x5, [x28, #16]",
"ldp x6, x7, [x28, #32]",
"ldr x8, [x28, #48]",
"ldp x16, x17, [x28, #112]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",

768
unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json
View File

File diff suppressed because it is too large Load Diff

20
unittests/InstructionCountCI/FlagM/Primary_32Bit.json
View File

@ -15,7 +15,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x06",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #136]",
"ldrh w20, [x28, #144]",
"str w20, [x8, #-4]!"
]
},
@ -25,18 +25,18 @@
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #136]",
"strh w20, [x28, #144]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #152]"
"str w20, [x28, #160]"
]
},
"push cs": {
"ExpectedInstructionCount": 2,
"Comment": "0x0e",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #138]",
"ldrh w20, [x28, #146]",
"str w20, [x8, #-4]!"
]
},
@ -44,7 +44,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x16",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #140]",
"ldrh w20, [x28, #148]",
"str w20, [x8, #-4]!"
]
},
@ -54,18 +54,18 @@
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #140]",
"strh w20, [x28, #148]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #160]"
"str w20, [x28, #168]"
]
},
"push ds": {
"ExpectedInstructionCount": 2,
"Comment": "0x1e",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #142]",
"ldrh w20, [x28, #150]",
"str w20, [x8, #-4]!"
]
},
@ -75,11 +75,11 @@
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #142]",
"strh w20, [x28, #150]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #164]"
"str w20, [x28, #172]"
]
},
"daa": {

16
unittests/InstructionCountCI/FlagM/SecondaryGroup.json
View File

@ -1251,14 +1251,14 @@
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldr w4, [x28, #176]"
"ldr w4, [x28, #184]"
]
},
"rdfsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldr x4, [x28, #176]"
"ldr x4, [x28, #184]"
]
},
"fxrstor [rax]": {
@ -1327,14 +1327,14 @@
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldr w4, [x28, #168]"
"ldr w4, [x28, #176]"
]
},
"rdgsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldr x4, [x28, #168]"
"ldr x4, [x28, #176]"
]
},
"ldmxcsr [rax]": {
@ -1357,14 +1357,14 @@
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"mov w20, w4",
"str x20, [x28, #176]"
"str x20, [x28, #184]"
]
},
"wrfsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"str x4, [x28, #176]"
"str x4, [x28, #184]"
]
},
"stmxcsr [rax]": {
@ -1385,14 +1385,14 @@
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"mov w20, w4",
"str x20, [x28, #168]"
"str x20, [x28, #176]"
]
},
"wrgsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"str x4, [x28, #168]"
"str x4, [x28, #176]"
]
},
"xsave [rax]": {

36
unittests/InstructionCountCI/FlagM/SecondaryModRM.json
View File

@ -26,14 +26,14 @@
"str x30, [x3]",
"mrs x3, nzcv",
"str w3, [x28, #728]",
"stp x4, x5, [x28, #8]",
"stp x6, x7, [x28, #24]",
"stp x8, x9, [x28, #40]",
"stp x10, x11, [x28, #56]",
"stp x12, x13, [x28, #72]",
"stp x14, x15, [x28, #88]",
"stp x16, x17, [x28, #104]",
"stp x19, x29, [x28, #120]",
"stp x4, x5, [x28, #16]",
"stp x6, x7, [x28, #32]",
"stp x8, x9, [x28, #48]",
"stp x10, x11, [x28, #64]",
"stp x12, x13, [x28, #80]",
"stp x14, x15, [x28, #96]",
"stp x16, x17, [x28, #112]",
"stp x19, x29, [x28, #128]",
"str x26, [x28, #752]",
"str x27, [x28, #760]",
"add x3, x28, #0xc0 (192)",
@ -52,14 +52,14 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #8]",
"ldp x6, x7, [x28, #24]",
"ldp x8, x9, [x28, #40]",
"ldp x10, x11, [x28, #56]",
"ldp x12, x13, [x28, #72]",
"ldp x14, x15, [x28, #88]",
"ldp x16, x17, [x28, #104]",
"ldp x19, x29, [x28, #120]",
"ldp x4, x5, [x28, #16]",
"ldp x6, x7, [x28, #32]",
"ldp x8, x9, [x28, #48]",
"ldp x10, x11, [x28, #64]",
"ldp x12, x13, [x28, #80]",
"ldp x14, x15, [x28, #96]",
"ldp x16, x17, [x28, #112]",
"ldp x19, x29, [x28, #128]",
"ldr x26, [x28, #752]",
"ldr x27, [x28, #760]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@ -83,7 +83,7 @@
"lsr x6, x20, #25",
"mrs x0, nzcv",
"str w0, [x28, #728]",
"str x8, [x28, #40]",
"str x8, [x28, #48]",
"mov w0, #0x100",
"str x0, [x28, #1048]",
"sub sp, sp, #0x10 (16)",
@ -95,7 +95,7 @@
"sub sp, sp, #0x10 (16)",
"ldr w8, [x28, #728]",
"msr nzcv, x8",
"ldr x8, [x28, #40]",
"ldr x8, [x28, #48]",
"str xzr, [x28, #1048]",
"orr x5, x0, x1, lsl #12"
]

4912
unittests/InstructionCountCI/FlagM/x87.json
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File diff suppressed because it is too large Load Diff

736
unittests/InstructionCountCI/FlagM/x87_f64.json
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File diff suppressed because it is too large Load Diff

36
unittests/InstructionCountCI/Primary.json
View File

@ -2042,7 +2042,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #138]",
"ldrh w20, [x28, #146]",
"bfxil x4, x20, #0, #16"
]
},
@ -2050,21 +2050,21 @@
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #138]"
"ldrh w4, [x28, #146]"
]
},
"mov rax, cs": {
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #138]"
"ldrh w4, [x28, #146]"
]
},
"mov ax, es": {
"ExpectedInstructionCount": 2,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #136]",
"ldrh w20, [x28, #144]",
"bfxil x4, x20, #0, #16"
]
},
@ -2072,21 +2072,21 @@
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #136]"
"ldrh w4, [x28, #144]"
]
},
"mov rax, es": {
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #136]"
"ldrh w4, [x28, #144]"
]
},
"mov ax, ss": {
"ExpectedInstructionCount": 2,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #140]",
"ldrh w20, [x28, #148]",
"bfxil x4, x20, #0, #16"
]
},
@ -2094,21 +2094,21 @@
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #140]"
"ldrh w4, [x28, #148]"
]
},
"mov rax, ss": {
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #140]"
"ldrh w4, [x28, #148]"
]
},
"mov ax, ds": {
"ExpectedInstructionCount": 2,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #142]",
"ldrh w20, [x28, #150]",
"bfxil x4, x20, #0, #16"
]
},
@ -2116,14 +2116,14 @@
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #142]"
"ldrh w4, [x28, #150]"
]
},
"mov rax, ds": {
"ExpectedInstructionCount": 1,
"Comment": "0x8c",
"ExpectedArm64ASM": [
"ldrh w4, [x28, #142]"
"ldrh w4, [x28, #150]"
]
},
"mov ax, gs": {
@ -2370,11 +2370,11 @@
"Comment": "0x8e",
"ExpectedArm64ASM": [
"uxth w20, w4",
"strh w20, [x28, #136]",
"strh w20, [x28, #144]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #152]"
"str w20, [x28, #160]"
]
},
"mov ss, ax": {
@ -2382,11 +2382,11 @@
"Comment": "0x8e",
"ExpectedArm64ASM": [
"uxth w20, w4",
"strh w20, [x28, #140]",
"strh w20, [x28, #148]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #160]"
"str w20, [x28, #168]"
]
},
"mov ds, ax": {
@ -2394,11 +2394,11 @@
"Comment": "0x8e",
"ExpectedArm64ASM": [
"uxth w20, w4",
"strh w20, [x28, #142]",
"strh w20, [x28, #150]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #164]"
"str w20, [x28, #172]"
]
},
"mov gs, ax": {

20
unittests/InstructionCountCI/Primary_32Bit.json
View File

@ -14,7 +14,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x06",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #136]",
"ldrh w20, [x28, #144]",
"str w20, [x8, #-4]!"
]
},
@ -24,18 +24,18 @@
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #136]",
"strh w20, [x28, #144]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #152]"
"str w20, [x28, #160]"
]
},
"push cs": {
"ExpectedInstructionCount": 2,
"Comment": "0x0e",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #138]",
"ldrh w20, [x28, #146]",
"str w20, [x8, #-4]!"
]
},
@ -43,7 +43,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x16",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #140]",
"ldrh w20, [x28, #148]",
"str w20, [x8, #-4]!"
]
},
@ -53,18 +53,18 @@
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #140]",
"strh w20, [x28, #148]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #160]"
"str w20, [x28, #168]"
]
},
"push ds": {
"ExpectedInstructionCount": 2,
"Comment": "0x1e",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #142]",
"ldrh w20, [x28, #150]",
"str w20, [x8, #-4]!"
]
},
@ -74,11 +74,11 @@
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #142]",
"strh w20, [x28, #150]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #164]"
"str w20, [x28, #172]"
]
},
"daa": {

64
unittests/InstructionCountCI/SSE42_Strings.json
View File

@ -44,10 +44,10 @@
"mov x1, x6",
"mrs x2, nzcv",
"str w2, [x28, #728]",
"stp x4, x5, [x28, #8]",
"stp x6, x7, [x28, #24]",
"str x8, [x28, #40]",
"stp x16, x17, [x28, #104]",
"stp x4, x5, [x28, #16]",
"stp x6, x7, [x28, #32]",
"str x8, [x28, #48]",
"stp x16, x17, [x28, #112]",
"sub sp, sp, #0x70 (112)",
"mov x2, sp",
"st1 {v2.2d, v3.2d}, [x2], #32",
@ -62,10 +62,10 @@
"blr x7",
"ldr w4, [x28, #728]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #8]",
"ldp x6, x7, [x28, #24]",
"ldr x8, [x28, #40]",
"ldp x16, x17, [x28, #104]",
"ldp x4, x5, [x28, #16]",
"ldp x6, x7, [x28, #32]",
"ldr x8, [x28, #48]",
"ldp x16, x17, [x28, #112]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
@ -87,10 +87,10 @@
"mov x1, x6",
"mrs x2, nzcv",
"str w2, [x28, #728]",
"stp x4, x5, [x28, #8]",
"stp x6, x7, [x28, #24]",
"str x8, [x28, #40]",
"stp x16, x17, [x28, #104]",
"stp x4, x5, [x28, #16]",
"stp x6, x7, [x28, #32]",
"str x8, [x28, #48]",
"stp x16, x17, [x28, #112]",
"sub sp, sp, #0x70 (112)",
"mov x2, sp",
"st1 {v2.2d, v3.2d}, [x2], #32",
@ -105,10 +105,10 @@
"blr x7",
"ldr w4, [x28, #728]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #8]",
"ldp x6, x7, [x28, #24]",
"ldr x8, [x28, #40]",
"ldp x16, x17, [x28, #104]",
"ldp x4, x5, [x28, #16]",
"ldp x6, x7, [x28, #32]",
"ldr x8, [x28, #48]",
"ldp x16, x17, [x28, #112]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
@ -135,10 +135,10 @@
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #728]",
"stp x4, x5, [x28, #8]",
"stp x6, x7, [x28, #24]",
"str x8, [x28, #40]",
"stp x16, x17, [x28, #104]",
"stp x4, x5, [x28, #16]",
"stp x6, x7, [x28, #32]",
"str x8, [x28, #48]",
"stp x16, x17, [x28, #112]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
@ -153,10 +153,10 @@
"blr x5",
"ldr w4, [x28, #728]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #8]",
"ldp x6, x7, [x28, #24]",
"ldr x8, [x28, #40]",
"ldp x16, x17, [x28, #104]",
"ldp x4, x5, [x28, #16]",
"ldp x6, x7, [x28, #32]",
"ldr x8, [x28, #48]",
"ldp x16, x17, [x28, #112]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
@ -176,10 +176,10 @@
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #728]",
"stp x4, x5, [x28, #8]",
"stp x6, x7, [x28, #24]",
"str x8, [x28, #40]",
"stp x16, x17, [x28, #104]",
"stp x4, x5, [x28, #16]",
"stp x6, x7, [x28, #32]",
"str x8, [x28, #48]",
"stp x16, x17, [x28, #112]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
@ -194,10 +194,10 @@
"blr x5",
"ldr w4, [x28, #728]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #8]",
"ldp x6, x7, [x28, #24]",
"ldr x8, [x28, #40]",
"ldp x16, x17, [x28, #104]",
"ldp x4, x5, [x28, #16]",
"ldp x6, x7, [x28, #32]",
"ldr x8, [x28, #48]",
"ldp x16, x17, [x28, #112]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",

12
unittests/InstructionCountCI/Secondary.json
View File

@ -1291,7 +1291,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xa0",
"ExpectedArm64ASM": [
"ldr x20, [x28, #176]",
"ldr x20, [x28, #184]",
"str x20, [x8, #-8]!"
]
},
@ -1301,11 +1301,11 @@
"ExpectedArm64ASM": [
"ldr x20, [x8]",
"add x8, x8, #0x8 (8)",
"strh w20, [x28, #146]",
"strh w20, [x28, #154]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #176]"
"str w20, [x28, #184]"
]
},
"bt ax, bx": {
@ -1664,7 +1664,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xa8",
"ExpectedArm64ASM": [
"ldr x20, [x28, #168]",
"ldr x20, [x28, #176]",
"str x20, [x8, #-8]!"
]
},
@ -1674,11 +1674,11 @@
"ExpectedArm64ASM": [
"ldr x20, [x8]",
"add x8, x8, #0x8 (8)",
"strh w20, [x28, #144]",
"strh w20, [x28, #152]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #168]"
"str w20, [x28, #176]"
]
},
"bts ax, bx": {

24
unittests/InstructionCountCI/SecondaryGroup.json
View File

@ -919,7 +919,7 @@
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #728]",
"str x8, [x28, #40]",
"str x8, [x28, #48]",
"mov w0, #0x100",
"str x0, [x28, #1048]",
"sub sp, sp, #0x10 (16)",
@ -931,7 +931,7 @@
"sub sp, sp, #0x10 (16)",
"ldr w8, [x28, #728]",
"msr nzcv, x8",
"ldr x8, [x28, #40]",
"ldr x8, [x28, #48]",
"str xzr, [x28, #1048]",
"orr x20, x0, x1, lsl #12",
"mov w4, w20"
@ -943,7 +943,7 @@
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #728]",
"str x8, [x28, #40]",
"str x8, [x28, #48]",
"mov w0, #0x100",
"str x0, [x28, #1048]",
"sub sp, sp, #0x10 (16)",
@ -955,7 +955,7 @@
"sub sp, sp, #0x10 (16)",
"ldr w8, [x28, #728]",
"msr nzcv, x8",
"ldr x8, [x28, #40]",
"ldr x8, [x28, #48]",
"str xzr, [x28, #1048]",
"orr x20, x0, x1, lsl #12",
"mov w4, w20"
@ -1435,14 +1435,14 @@
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldr w4, [x28, #176]"
"ldr w4, [x28, #184]"
]
},
"rdfsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldr x4, [x28, #176]"
"ldr x4, [x28, #184]"
]
},
"fxrstor [rax]": {
@ -1511,14 +1511,14 @@
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldr w4, [x28, #168]"
"ldr w4, [x28, #176]"
]
},
"rdgsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldr x4, [x28, #168]"
"ldr x4, [x28, #176]"
]
},
"ldmxcsr [rax]": {
@ -1541,14 +1541,14 @@
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"mov w20, w4",
"str x20, [x28, #176]"
"str x20, [x28, #184]"
]
},
"wrfsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"str x4, [x28, #176]"
"str x4, [x28, #184]"
]
},
"stmxcsr [rax]": {
@ -1569,14 +1569,14 @@
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"mov w20, w4",
"str x20, [x28, #168]"
"str x20, [x28, #176]"
]
},
"wrgsbase rax": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"str x4, [x28, #168]"
"str x4, [x28, #176]"
]
},
"xsave [rax]": {

36
unittests/InstructionCountCI/SecondaryModRM.json
View File

@ -26,14 +26,14 @@
"str x30, [x3]",
"mrs x3, nzcv",
"str w3, [x28, #728]",
"stp x4, x5, [x28, #8]",
"stp x6, x7, [x28, #24]",
"stp x8, x9, [x28, #40]",
"stp x10, x11, [x28, #56]",
"stp x12, x13, [x28, #72]",
"stp x14, x15, [x28, #88]",
"stp x16, x17, [x28, #104]",
"stp x19, x29, [x28, #120]",
"stp x4, x5, [x28, #16]",
"stp x6, x7, [x28, #32]",
"stp x8, x9, [x28, #48]",
"stp x10, x11, [x28, #64]",
"stp x12, x13, [x28, #80]",
"stp x14, x15, [x28, #96]",
"stp x16, x17, [x28, #112]",
"stp x19, x29, [x28, #128]",
"str x26, [x28, #752]",
"str x27, [x28, #760]",
"add x3, x28, #0xc0 (192)",
@ -52,14 +52,14 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #8]",
"ldp x6, x7, [x28, #24]",
"ldp x8, x9, [x28, #40]",
"ldp x10, x11, [x28, #56]",
"ldp x12, x13, [x28, #72]",
"ldp x14, x15, [x28, #88]",
"ldp x16, x17, [x28, #104]",
"ldp x19, x29, [x28, #120]",
"ldp x4, x5, [x28, #16]",
"ldp x6, x7, [x28, #32]",
"ldp x8, x9, [x28, #48]",
"ldp x10, x11, [x28, #64]",
"ldp x12, x13, [x28, #80]",
"ldp x14, x15, [x28, #96]",
"ldp x16, x17, [x28, #112]",
"ldp x19, x29, [x28, #128]",
"ldr x26, [x28, #752]",
"ldr x27, [x28, #760]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@ -83,7 +83,7 @@
"lsr x6, x20, #25",
"mrs x0, nzcv",
"str w0, [x28, #728]",
"str x8, [x28, #40]",
"str x8, [x28, #48]",
"mov w0, #0x100",
"str x0, [x28, #1048]",
"sub sp, sp, #0x10 (16)",
@ -95,7 +95,7 @@
"sub sp, sp, #0x10 (16)",
"ldr w8, [x28, #728]",
"msr nzcv, x8",
"ldr x8, [x28, #40]",
"ldr x8, [x28, #48]",
"str xzr, [x28, #1048]",
"orr x5, x0, x1, lsl #12"
]

12
unittests/InstructionCountCI/Secondary_32Bit.json
View File

@ -12,7 +12,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xa0",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #146]",
"ldrh w20, [x28, #154]",
"str w20, [x8, #-4]!"
]
},
@ -22,18 +22,18 @@
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #146]",
"strh w20, [x28, #154]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #176]"
"str w20, [x28, #184]"
]
},
"push gs": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xa8",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #144]",
"ldrh w20, [x28, #152]",
"str w20, [x8, #-4]!"
]
},
@ -43,11 +43,11 @@
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #144]",
"strh w20, [x28, #152]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #168]"
"str w20, [x28, #176]"
]
}
}

4912
unittests/InstructionCountCI/x87.json
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736
unittests/InstructionCountCI/x87_f64.json
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File diff suppressed because it is too large Load Diff