FEX-Emu/FEX
1
0
Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2025-01-09 07:10:39 +00:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity

OpcodeDispatcher: Handle VBLENDVPS

Browse Source
This commit is contained in:
Lioncache 2023-02-06 22:02:41 -05:00
parent acbfee55b4
commit 94e91565b1
4 changed files with 83 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp vendored
View File

@ -6119,6 +6119,8 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
{OPD(3, 0b01, 0x46), 1, &OpDispatchBuilder::VPERM2Op},
{OPD(3, 0b01, 0x4A), 1, &OpDispatchBuilder::AVXVectorVariableBlend<4>},
{OPD(3, 0b01, 0xDF), 1, &OpDispatchBuilder::VAESKeyGenAssistOp},
};
#undef OPD

2
External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp vendored
View File

@ -3467,6 +3467,8 @@ void OpDispatchBuilder::AVXVectorVariableBlend(OpcodeArgs) {
}
StoreResult(FPRClass, Op, Result, -1);
}
template
void OpDispatchBuilder::AVXVectorVariableBlend<4>(OpcodeArgs);
void OpDispatchBuilder::PTestOp(OpcodeArgs) {
// Invalidate deferred flags early

2
External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp vendored
View File

@ -445,7 +445,7 @@ void InitializeVEXTables() {
{OPD(3, 0b01, 0x48), 1, X86InstInfo{"VPERMILzz2PS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(3, 0b01, 0x49), 1, X86InstInfo{"VPERMILzz2PD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(3, 0b01, 0x4A), 1, X86InstInfo{"VBLENDVPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(3, 0b01, 0x4A), 1, X86InstInfo{"VBLENDVPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(3, 0b01, 0x4B), 1, X86InstInfo{"VBLENDVPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(3, 0b01, 0x4C), 1, X86InstInfo{"VBLENDVB", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},

78
unittests/ASM/VEX/vblendvps.asm Normal file
View File

@ -0,0 +1,78 @@
%ifdef CONFIG
{
"HostFeatures": ["AVX"],
"RegData": {
"XMM3": ["0x1111111122222222", "0x3333333344444444", "0x5555555566666666", "0x7777777788888888"],
"XMM4": ["0x1111111122222222", "0x3333333344444444", "0x0000000000000000", "0x0000000000000000"],
"XMM5": ["0xAAAAAAAABBBBBBBB", "0xCCCCCCCCDDDDDDDD", "0xEEEEEEEEFFFFFFFF", "0x9999999988888888"],
"XMM6": ["0xAAAAAAAABBBBBBBB", "0xCCCCCCCCDDDDDDDD", "0x0000000000000000", "0x0000000000000000"],
"XMM7": ["0xAAAAAAAA22222222", "0xCCCCCCCC44444444", "0xEEEEEEEE66666666", "0x9999999988888888"],
"XMM8": ["0xAAAAAAAA22222222", "0xCCCCCCCC44444444", "0x0000000000000000", "0x0000000000000000"],
"XMM9": ["0x11111111BBBBBBBB", "0x33333333DDDDDDDD", "0x55555555FFFFFFFF", "0x7777777788888888"],
"XMM10": ["0x11111111BBBBBBBB", "0x33333333DDDDDDDD", "0x0000000000000000", "0x0000000000000000"]
}
}
%endif
lea rdx, [rel .data]
vmovaps ymm0, [rdx]
vmovaps ymm1, [rdx + 32]
vmovaps ymm2, [rel .mask_all]
; Select all ymm1
vblendvps ymm3, ymm0, ymm1, ymm2
vblendvps xmm4, xmm0, xmm1, xmm2
; Select all ymm0
vmovaps ymm2, [rel .mask_none]
vblendvps ymm5, ymm0, ymm1, ymm2
vblendvps xmm6, xmm0, xmm1, xmm2
; Interleaved selection from ymm1 and ymm0
vmovaps ymm2, [rel .mask_interleave1]
vblendvps ymm7, ymm0, ymm1, ymm2
vblendvps xmm8, xmm0, xmm1, xmm2
; Interleaved selection from ymm0 and ymm1
vmovaps ymm2, [rel .mask_interleave2]
vblendvps ymm9, ymm0, ymm1, ymm2
vblendvps xmm10, xmm0, xmm1, xmm2
hlt
align 32
.data:
dq 0xAAAAAAAABBBBBBBB
dq 0xCCCCCCCCDDDDDDDD
dq 0xEEEEEEEEFFFFFFFF
dq 0x9999999988888888
dq 0x1111111122222222
dq 0x3333333344444444
dq 0x5555555566666666
dq 0x7777777788888888
.mask_all:
dq 0xFFFFFFFFFFFFFFFF
dq 0xFFFFFFFFFFFFFFFF
dq 0xFFFFFFFFFFFFFFFF
dq 0xFFFFFFFFFFFFFFFF
.mask_none:
dq 0x0000000000000000
dq 0x0000000000000000
dq 0x0000000000000000
dq 0x0000000000000000
.mask_interleave1:
dq 0x0000000080000000
dq 0x0000000080000000
dq 0x0000000080000000
dq 0x0000000080000000
.mask_interleave2:
dq 0x8000000000000000
dq 0x8000000000000000
dq 0x8000000000000000
dq 0x8000000000000000