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X87F64: Add working BCD test
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CallumDev
parent
0f8f2bf2b4
commit
9640216124
@ -108,7 +108,7 @@ void OpDispatchBuilder::FBSTPF64(OpcodeArgs) {
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auto data = _LoadContextIndexed(orig_top, 8, MMBaseOffset(), 16, FPRClass);
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OrderedNode *converted = _F80CVTTo(data, 8);
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converted = _F80BCDStore(data);
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converted = _F80BCDStore(converted);
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StoreResult_WithOpSize(FPRClass, Op, Op->Dest, converted, 10, 1);
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194
unittests/ASM/X87_F64/DF_04_F64.asm
Normal file
194
unittests/ASM/X87_F64/DF_04_F64.asm
Normal file
@ -0,0 +1,194 @@
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%ifdef CONFIG
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{
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"RegData": {
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"XMM0": ["0x0506070801000000", "0x0000000000000012"],
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"XMM1": ["0x6576879821300000", "0x0000000000000000"],
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"XMM2": ["0xB90984060D300000", "0x000000000000C03B"],
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"XMM3": ["0xA83732340C000000", "0x000000000000C03B"],
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"XMM4": ["0xFFAA6DA436100000", "0x000000000000C03A"],
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"XMM5": ["0x0000000000000001", "0x0000000000000000"],
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"XMM6": ["0x0000000000000001", "0x0000000000008000"],
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"XMM7": ["0x0000000000000000", "0x0000000000008000"],
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"XMM8": ["0x0000000000000000", "0x0000000000008000"],
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"XMM9": ["0x0000000000000000", "0x0000000000000000"],
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"XMM10": ["0x0000000000000001", "0x0000000000008000"],
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"XMM11": ["0x0000000000000001", "0x0000000000000000"]
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},
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"Env": { "FEX_X87REDUCEDPRECISION" : "1" }
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}
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%endif
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fbld [rel .data_0]
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fbstp [rel .res_data_0]
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movups xmm0, [rel .res_data_0]
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andps xmm0, [rel .precisionMask] ; Mask imprecise bits
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fbld [rel .data_1]
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fbstp [rel .res_data_1]
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movups xmm1, [rel .res_data_1]
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andps xmm1, [rel .precisionMask] ; Mask imprecise bits
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; Check encoding of invalid BCD
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fbld [rel .data_2]
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fstp tword [rel .res_data_2]
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movups xmm2, [rel .res_data_2]
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andps xmm2, [rel .precisionMask] ; Mask imprecise bits
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fbld [rel .data_3]
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fstp tword [rel .res_data_3]
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movups xmm3, [rel .res_data_3]
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andps xmm3, [rel .precisionMask] ; Mask imprecise bits
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fbld [rel .data_4]
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fstp tword [rel .res_data_4]
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movups xmm4, [rel .res_data_4]
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andps xmm4, [rel .precisionMask] ; Mask imprecise bits
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; Some special values
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fld tword [rel .data_5]
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fbstp [rel .res_data_5]
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movups xmm5, [rel .res_data_5]
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fld tword [rel .data_6]
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fbstp [rel .res_data_6]
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movups xmm6, [rel .res_data_6]
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fld tword [rel .data_7]
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fbstp [rel .res_data_7]
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movups xmm7, [rel .res_data_7]
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; Values that choose +- 0 or +-1 depending on rounding mode
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; -1 < F < -0
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; +0 < F < +1
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fld tword [rel .data_8]
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fbstp [rel .res_data_8]
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movups xmm8, [rel .res_data_8]
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fld tword [rel .data_9]
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fbstp [rel .res_data_9]
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movups xmm9, [rel .res_data_9]
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; Swap control word
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fnstcw [rel .cw]
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mov ax, [rel .cw]
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and ax, ~(3 << 10)
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or eax, 1 << 10 ; Round down
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mov [rel .cw], ax
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fldcw [rel .cw]
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fld tword [rel .data_10]
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fbstp [rel .res_data_10]
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movups xmm10, [rel .res_data_10]
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; Swap control word
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fnstcw [rel .cw]
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mov ax, [rel .cw]
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and ax, ~(3 << 10)
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or eax, 2 << 10 ; Round up
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mov [rel .cw], ax
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fldcw [rel .cw]
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fld tword [rel .data_11]
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fbstp [rel .res_data_11]
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movups xmm11, [rel .res_data_11]
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; Values that generate Invalicating floating point operation exception
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; -inf
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; +inf
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; Negative value too large for destination format
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; Positive value too large for destination format
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; NaN
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; On IA the indefinite BCD result is still stored to memory
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; XXX: We don't support IA on this
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hlt
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align 16
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.precisionMask:
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dd 0xfff00000
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dd 0xffffffff
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dd 0xffffffff
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dd 0xffffffff
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.cw:
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dw 0
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.data_0:
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dd 0x01020304
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dd 0x05060708
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dd 0x09101112
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dd 0x13141516
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.data_1:
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dd 0x21324354
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dd 0x65768798
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dd 0x00000000
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dd 0x00000000
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.data_2:
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dd 0xFFFFFFFF
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dd 0xFFFFFFFF
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dd 0xFFFFFFFF
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dd 0xFFFFFFFF
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.data_3:
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dd 0xF0F0F0F0
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dd 0xF0F0F0F0
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dd 0xF0F0F0F0
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dd 0xF0F0F0F0
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.data_4:
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dd 0x0A0B0C0D
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dd 0x0E0FAAAB
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dd 0xACADAEAF
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dd 0xBABBBCBD
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.data_5:
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dt 1.0
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.data_6:
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dt -1.0
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.data_7:
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dt -0.0
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.data_8:
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dt -0.5
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.data_9:
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dt 0.5
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.data_10:
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dt -0.5
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.data_11:
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dt 0.5
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.res_data_0:
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dq 0
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dq 0
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.res_data_1:
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dq 0
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dq 0
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.res_data_2:
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dq 0
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dq 0
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.res_data_3:
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dq 0
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dq 0
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.res_data_4:
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dq 0
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dq 0
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.res_data_5:
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dq 0
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dq 0
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.res_data_6:
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dq 0
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dq 0
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.res_data_7:
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dq 0
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dq 0
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.res_data_8:
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dq 0
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dq 0
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.res_data_9:
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dq 0
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dq 0
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.res_data_10:
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dq 0
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dq 0
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.res_data_11:
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dq 0
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dq 0
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