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InstructionCountCI: add bytemark stringsort blocks
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig
parent
689b461d7b
commit
9c8df79dfb
@ -428,6 +428,198 @@
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"mov x11, x26"
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]
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},
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"glibc AVX memcpy block 1": {
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"ExpectedInstructionCount": 43,
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"x86Insts": [
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"vmovdqu ymm5,yword [rsi+0x20]",
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"vmovdqu ymm6,yword [rsi+0x40]",
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"lea rcx,[rdi+rdx*1-0x81]",
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"vmovdqu ymm7,yword [rsi+0x60]",
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"vmovdqu ymm8,yword [rsi+rdx*1-0x20]",
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"sub rsi,rdi",
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"and rcx,0xffffffffffffffe0",
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"add rsi,rcx",
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"nop dword [rax+0x0]",
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"vmovdqu ymm1,yword [rsi+0x60]",
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"vmovdqu ymm2,yword [rsi+0x40]",
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"vmovdqu ymm3,yword [rsi+0x20]",
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"vmovdqu ymm4,yword [rsi]",
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"add rsi,0xffffffffffffff80",
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"vmovdqa yword [rcx+0x60],ymm1",
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"vmovdqa yword [rcx+0x40],ymm2",
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"vmovdqa yword [rcx+0x20],ymm3",
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"vmovdqa yword [rcx],ymm4",
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"add rcx,0xffffffffffffff80",
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"cmp rdi,rcx"
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],
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"ExpectedArm64ASM": [
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"ldr q21, [x10, #32]",
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"ldr q2, [x10, #48]",
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"ldr q22, [x10, #64]",
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"ldr q3, [x10, #80]",
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"sub x20, x11, #0x81 (129)",
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"add x5, x20, x6",
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"ldr q23, [x10, #96]",
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"ldr q4, [x10, #112]",
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"add x20, x10, x6",
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"ldur q24, [x20, #-32]",
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"add x20, x10, x6",
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"ldur q5, [x20, #-16]",
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"sub x10, x10, x11",
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"and x5, x5, #0xffffffffffffffe0",
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"add x10, x10, x5",
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"ldr q17, [x10, #96]",
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"ldr q6, [x10, #112]",
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"ldr q18, [x10, #64]",
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"ldr q7, [x10, #80]",
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"ldr q19, [x10, #32]",
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"ldr q8, [x10, #48]",
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"ldr q20, [x10]",
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"ldr q9, [x10, #16]",
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"sub x10, x10, #0x80 (128)",
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"str q17, [x5, #96]",
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"str q6, [x5, #112]",
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"str q18, [x5, #64]",
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"str q7, [x5, #80]",
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"str q19, [x5, #32]",
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"str q8, [x5, #48]",
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"str q20, [x5]",
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"str q9, [x5, #16]",
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"sub x5, x5, #0x80 (128)",
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"eor w27, w11, w5",
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"subs x26, x11, x5",
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"str q5, [x28, #144]",
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"str q4, [x28, #128]",
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"str q3, [x28, #112]",
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"str q2, [x28, #96]",
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"str q9, [x28, #80]",
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"str q8, [x28, #64]",
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"str q7, [x28, #48]",
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"str q6, [x28, #32]"
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]
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},
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"glibc AVX memcpy block 2": {
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"ExpectedInstructionCount": 51,
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"x86Insts": [
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"vmovdqu ymm5,yword [rsi+rdx*1-0x20]",
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"vmovdqu ymm6,yword [rsi+rdx*1-0x40]",
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"mov rcx,rdi",
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"or rdi,0x1f",
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"vmovdqu ymm7,yword [rsi+rdx*1-0x60]",
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"vmovdqu ymm8,yword [rsi+rdx*1-0x80]",
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"sub rsi,rcx",
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"inc rdi",
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"add rsi,rdi",
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"lea rdx,[rcx+rdx*1-0x80]",
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"nop dword [rax+rax*1+0x0]",
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"vmovdqu ymm1,yword [rsi]",
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"vmovdqu ymm2,yword [rsi+0x20]",
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"vmovdqu ymm3,yword [rsi+0x40]",
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"vmovdqu ymm4,yword [rsi+0x60]",
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"sub rsi,0xffffffffffffff80",
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"vmovdqa yword [rdi],ymm1",
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"vmovdqa yword [rdi+0x20],ymm2",
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"vmovdqa yword [rdi+0x40],ymm3",
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"vmovdqa yword [rdi+0x60],ymm4",
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"sub rdi,0xffffffffffffff80",
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"cmp rdx,rdi"
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],
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"ExpectedArm64ASM": [
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"add x20, x10, x6",
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"ldur q21, [x20, #-32]",
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"add x20, x10, x6",
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"ldur q2, [x20, #-16]",
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"add x20, x10, x6",
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"ldur q22, [x20, #-64]",
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"add x20, x10, x6",
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"ldur q3, [x20, #-48]",
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"mov x5, x11",
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"orr x11, x11, #0x1f",
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"add x20, x10, x6",
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"ldur q23, [x20, #-96]",
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"add x20, x10, x6",
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"ldur q4, [x20, #-80]",
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"add x20, x10, x6",
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"ldur q24, [x20, #-128]",
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"add x20, x10, x6",
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"ldur q5, [x20, #-112]",
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"sub x10, x10, x5",
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"add x11, x11, #0x1 (1)",
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"add x10, x10, x11",
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"sub x20, x5, #0x80 (128)",
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"add x6, x20, x6",
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"ldr q17, [x10]",
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"ldr q6, [x10, #16]",
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"ldr q18, [x10, #32]",
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"ldr q7, [x10, #48]",
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"ldr q19, [x10, #64]",
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"ldr q8, [x10, #80]",
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"ldr q20, [x10, #96]",
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"ldr q9, [x10, #112]",
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"add x10, x10, #0x80 (128)",
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"str q17, [x11]",
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"str q6, [x11, #16]",
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"str q18, [x11, #32]",
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"str q7, [x11, #48]",
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"str q19, [x11, #64]",
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"str q8, [x11, #80]",
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"str q20, [x11, #96]",
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"str q9, [x11, #112]",
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"add x11, x11, #0x80 (128)",
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"eor w27, w6, w11",
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"subs x26, x6, x11",
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"str q5, [x28, #144]",
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"str q4, [x28, #128]",
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"str q3, [x28, #112]",
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"str q2, [x28, #96]",
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"str q9, [x28, #80]",
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"str q8, [x28, #64]",
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"str q7, [x28, #48]",
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"str q6, [x28, #32]"
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]
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},
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"bytemark strsift": {
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"ExpectedInstructionCount": 20,
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"x86Insts": [
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"mov rsi,rdx",
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"and rsi,0xfffffffffffffffc",
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"movq xmm0,rcx",
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"pshufd xmm0,xmm0,0x44",
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"mov rdi,qword [rsp+0x20]",
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"lea rdi,[rdi+r13*8]",
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"xor r8d,r8d",
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"movdqu xmm1,oword [rdi+r8*8-0x10]",
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"movdqu xmm2,oword [rdi+r8*8]",
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"paddq xmm1,xmm0",
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"paddq xmm2,xmm0",
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"movdqu oword [rdi+r8*8-0x10],xmm1",
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"movdqu oword [rdi+r8*8],xmm2",
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"add r8,0x4",
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"cmp rsi,r8"
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],
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"ExpectedArm64ASM": [
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"mov x10, x6",
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"and x10, x10, #0xfffffffffffffffc",
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"fmov d16, x5",
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"dup v16.2d, v16.d[0]",
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"ldr x11, [x8, #32]",
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"add x11, x11, x17, lsl #3",
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"mov w12, #0x0",
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"add x20, x11, x12, lsl #3",
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"ldur q17, [x20, #-16]",
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"add x20, x11, x12, lsl #3",
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"ldr q18, [x20]",
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"add v17.2d, v17.2d, v16.2d",
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"add v18.2d, v18.2d, v16.2d",
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"add x20, x11, x12, lsl #3",
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"stur q17, [x20, #-16]",
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"add x20, x11, x12, lsl #3",
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"str q18, [x20]",
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"add x12, x12, #0x4 (4)",
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"eor w27, w10, w12",
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"subs x26, x10, x12"
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]
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},
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"pcmpistri xmm0, xmm1, 0_0_00_11_01b": {
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"ExpectedInstructionCount": 41,
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"Comment": [
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