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Merge pull request #738 from Sonicadvance1/remove_warnings_9
Removes warnings from Register Allocation Pass
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commit
a156210064
@ -230,11 +230,6 @@ namespace {
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Graph->Set.Conflicts[Index] |= 1 << ConflictRegAndClass.Reg;
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}
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bool IsConflict(RegisterGraph *Graph, PhysicalRegister RegAndClass, PhysicalRegister ConflictRegAndClass) {
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uint32_t Index = (ConflictRegAndClass.Class << 8) | RegAndClass.Raw;
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return (Graph->Set.Conflicts[Index] >> ConflictRegAndClass.Reg) & 1;
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}
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uint32_t GetConflicts(RegisterGraph *Graph, PhysicalRegister RegAndClass, FEXCore::IR::RegisterClassType ConflictClass) {
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uint32_t Index = (ConflictClass.Val << 8) | RegAndClass.Raw;
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@ -275,6 +270,13 @@ namespace {
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}
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#if 0
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bool IsConflict(RegisterGraph *Graph, PhysicalRegister RegAndClass, PhysicalRegister ConflictRegAndClass) {
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uint32_t Index = (ConflictRegAndClass.Class << 8) | RegAndClass.Raw;
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return (Graph->Set.Conflicts[Index] >> ConflictRegAndClass.Reg) & 1;
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}
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// PHI nodes currently unsupported
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/**
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* @brief Individual node interference check
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*/
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@ -298,6 +300,7 @@ namespace {
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return false;
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}
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#endif
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FEXCore::IR::RegisterClassType GetRegClassFromNode(FEXCore::IR::IRListView<false> *IR, FEXCore::IR::IROp_Header *IROp) {
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using namespace FEXCore;
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@ -383,7 +386,6 @@ namespace FEXCore::IR {
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RegisterAllocationData* GetAllocationData() override;
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std::unique_ptr<RegisterAllocationData, RegisterAllocationDataDeleter> PullAllocationData() override;
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private:
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bool OptimizeSRA;
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uint32_t SpillPointId;
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#define INFO_MAKE(id, Class) ((id) | (Class << 24))
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@ -397,6 +399,7 @@ namespace FEXCore::IR {
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RegisterGraph *Graph;
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FEXCore::IR::Pass* CompactionPass;
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bool OptimizeSRA;
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void SpillOne(FEXCore::IR::IREmitter *IREmit);
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@ -589,6 +592,7 @@ namespace FEXCore::IR {
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} else {
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LogMan::Throw::A(false, "Unexpected static class %d", StaticClass);
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}
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return false; // Unknown
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};
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// Is an OP_LOADREGISTER eligible to read directly from the SRA reg?
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@ -600,6 +604,7 @@ namespace FEXCore::IR {
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} else {
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LogMan::Throw::A(false, "Unexpected static class %d", StaticClass);
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}
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return false; // Unknown
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};
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// Get SRA Reg and Class from a Context offset
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@ -903,8 +908,6 @@ namespace FEXCore::IR {
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BucketList<32, uint32_t> Active;
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for (int OpNodeId = 0; OpNodeId < IR->GetSSACount(); OpNodeId++) {
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auto OpHeader = IR->GetNode(OrderedNodeWrapper::WrapOffset(OpNodeId * sizeof(IR::OrderedNode)))->Op(IR->GetData());
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// Expire end intervals first
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SpanEnd[OpNodeId].Iterate([&](uint32_t EdgeInfo) {
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Active.Erase(INFO_IDCLASS(EdgeInfo));
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