Merge pull request #738 from Sonicadvance1/remove_warnings_9

Removes warnings from Register Allocation Pass
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Scott Mansell 2021-02-01 16:32:05 +13:00 committed by GitHub
commit a156210064
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@ -230,11 +230,6 @@ namespace {
Graph->Set.Conflicts[Index] |= 1 << ConflictRegAndClass.Reg;
}
bool IsConflict(RegisterGraph *Graph, PhysicalRegister RegAndClass, PhysicalRegister ConflictRegAndClass) {
uint32_t Index = (ConflictRegAndClass.Class << 8) | RegAndClass.Raw;
return (Graph->Set.Conflicts[Index] >> ConflictRegAndClass.Reg) & 1;
}
uint32_t GetConflicts(RegisterGraph *Graph, PhysicalRegister RegAndClass, FEXCore::IR::RegisterClassType ConflictClass) {
uint32_t Index = (ConflictClass.Val << 8) | RegAndClass.Raw;
@ -275,6 +270,13 @@ namespace {
}
#if 0
bool IsConflict(RegisterGraph *Graph, PhysicalRegister RegAndClass, PhysicalRegister ConflictRegAndClass) {
uint32_t Index = (ConflictRegAndClass.Class << 8) | RegAndClass.Raw;
return (Graph->Set.Conflicts[Index] >> ConflictRegAndClass.Reg) & 1;
}
// PHI nodes currently unsupported
/**
* @brief Individual node interference check
*/
@ -298,6 +300,7 @@ namespace {
return false;
}
#endif
FEXCore::IR::RegisterClassType GetRegClassFromNode(FEXCore::IR::IRListView<false> *IR, FEXCore::IR::IROp_Header *IROp) {
using namespace FEXCore;
@ -383,7 +386,6 @@ namespace FEXCore::IR {
RegisterAllocationData* GetAllocationData() override;
std::unique_ptr<RegisterAllocationData, RegisterAllocationDataDeleter> PullAllocationData() override;
private:
bool OptimizeSRA;
uint32_t SpillPointId;
#define INFO_MAKE(id, Class) ((id) | (Class << 24))
@ -397,6 +399,7 @@ namespace FEXCore::IR {
RegisterGraph *Graph;
FEXCore::IR::Pass* CompactionPass;
bool OptimizeSRA;
void SpillOne(FEXCore::IR::IREmitter *IREmit);
@ -589,6 +592,7 @@ namespace FEXCore::IR {
} else {
LogMan::Throw::A(false, "Unexpected static class %d", StaticClass);
}
return false; // Unknown
};
// Is an OP_LOADREGISTER eligible to read directly from the SRA reg?
@ -600,6 +604,7 @@ namespace FEXCore::IR {
} else {
LogMan::Throw::A(false, "Unexpected static class %d", StaticClass);
}
return false; // Unknown
};
// Get SRA Reg and Class from a Context offset
@ -903,8 +908,6 @@ namespace FEXCore::IR {
BucketList<32, uint32_t> Active;
for (int OpNodeId = 0; OpNodeId < IR->GetSSACount(); OpNodeId++) {
auto OpHeader = IR->GetNode(OrderedNodeWrapper::WrapOffset(OpNodeId * sizeof(IR::OrderedNode)))->Op(IR->GetData());
// Expire end intervals first
SpanEnd[OpNodeId].Iterate([&](uint32_t EdgeInfo) {
Active.Erase(INFO_IDCLASS(EdgeInfo));