From a2a44d188ae69d7e05cf0bdcd18c0c489a8095b9 Mon Sep 17 00:00:00 2001
From: lioncash <mai.iam2048@gmail.com>
Date: Tue, 13 Dec 2022 20:38:19 +0000
Subject: [PATCH] OpcodeDispatcher: Handle VPMINUW

---
 .../Interface/Core/OpcodeDispatcher.cpp       |  1 +
 .../Core/OpcodeDispatcher/Vector.cpp          |  2 +
 .../Interface/Core/X86Tables/VEXTables.cpp    |  2 +-
 unittests/ASM/VEX/vpminuw.asm                 | 41 +++++++++++++++++++
 4 files changed, 45 insertions(+), 1 deletion(-)
 create mode 100644 unittests/ASM/VEX/vpminuw.asm

diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index 5c5977a5b..14185e540 100644
--- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -5957,6 +5957,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
     {OPD(2, 0b01, 0x2A), 1, &OpDispatchBuilder::VMOVVectorNTOp},
 
     {OPD(2, 0b01, 0x37), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VCMPGT, 8>},
+    {OPD(2, 0b01, 0x3A), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VUMIN, 2>},
     {OPD(2, 0b01, 0x3B), 1, &OpDispatchBuilder::UnimplementedOp},
 
     {OPD(2, 0b01, 0x58), 1, &OpDispatchBuilder::VBROADCASTOp<4>},
diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
index 3b92fa259..5e5890865 100644
--- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
@@ -501,6 +501,8 @@ void OpDispatchBuilder::AVXVectorALUOp<IR::OP_VURAVG, 2>(OpcodeArgs);
 
 template
 void OpDispatchBuilder::AVXVectorALUOp<IR::OP_VUMIN, 1>(OpcodeArgs);
+template
+void OpDispatchBuilder::AVXVectorALUOp<IR::OP_VUMIN, 2>(OpcodeArgs);
 
 template<FEXCore::IR::IROps IROp, size_t ElementSize>
 void OpDispatchBuilder::VectorALUROp(OpcodeArgs) {
diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp
index c4b5c1688..4872dca58 100644
--- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp
+++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp
@@ -316,7 +316,7 @@ void InitializeVEXTables() {
 
     {OPD(2, 0b01, 0x38), 1, X86InstInfo{"VPMINSB", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
     {OPD(2, 0b01, 0x39), 1, X86InstInfo{"VPMINSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(2, 0b01, 0x3A), 1, X86InstInfo{"VPMINUW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(2, 0b01, 0x3A), 1, X86InstInfo{"VPMINUW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(2, 0b01, 0x3B), 1, X86InstInfo{"VPMINUD", TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(2, 0b01, 0x3C), 1, X86InstInfo{"VPMAXSB", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
     {OPD(2, 0b01, 0x3D), 1, X86InstInfo{"VPMAXSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
diff --git a/unittests/ASM/VEX/vpminuw.asm b/unittests/ASM/VEX/vpminuw.asm
new file mode 100644
index 000000000..53a9d9431
--- /dev/null
+++ b/unittests/ASM/VEX/vpminuw.asm
@@ -0,0 +1,41 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+    "XMM0": ["0x4142434445464748", "0x7172737475767778", "0x4142434445464748", "0x7172737475767778"],
+    "XMM1": ["0x6162636465666768", "0x5152535455565758", "0x6162636465666768", "0x5152535455565758"],
+    "XMM2": ["0x4142434445464748", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
+    "XMM3": ["0x4142434445464748", "0x5152535455565758", "0x4142434445464748", "0x5152535455565758"],
+    "XMM4": ["0x4142434445464748", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
+    "XMM5": ["0x4142434445464748", "0x5152535455565758", "0x4142434445464748", "0x5152535455565758"]
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+lea rdx, [rel .data]
+
+vmovapd ymm0, [rdx]
+vmovapd ymm1, [rdx + 32]
+
+vpminuw xmm2, xmm0, xmm1
+vpminuw ymm3, ymm0, ymm1
+
+vpminuw xmm4, xmm0, [rdx + 32]
+vpminuw ymm5, ymm0, [rdx + 32]
+
+hlt
+
+align 32
+.data:
+dq 0x4142434445464748
+dq 0x7172737475767778
+dq 0x4142434445464748
+dq 0x7172737475767778
+
+dq 0x6162636465666768
+dq 0x5152535455565758
+dq 0x6162636465666768
+dq 0x5152535455565758