diff --git a/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp b/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
index 2a3b25848..b54d54857 100644
--- a/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
+++ b/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
@@ -96,6 +96,9 @@ private:
   // Inverse of SSAToNewSSA. Since it's indexed by new nodes, it grows.
   fextl::vector<Ref> NewSSAToSSA;
 
+  // Whether we have a non-identity mapping.
+  bool AnyRemapped;
+
   // Map of assigned registers. Grows.
   fextl::vector<PhysicalRegister> SSAToReg;
 
@@ -127,6 +130,7 @@ private:
 
     SSAToNewSSA[OldID] = New;
     NewSSAToSSA[NewID] = Old;
+    AnyRemapped = true;
 
     LOGMAN_THROW_A_FMT(Map(Old) == New && Unmap(New) == Old, "Post-condition");
     LOGMAN_THROW_A_FMT(Unmap(Old) == Old, "Invariant1");
@@ -468,6 +472,7 @@ void ConstrainedRAPass::Run(IREmitter* IREmit_) {
   NextUses.resize(IR->GetSSACount(), 0);
   SpillSlotCount = 0;
   AnySpilled = false;
+  AnyRemapped = false;
 
   // Next-use distance relative to the block end of each source, last first.
   fextl::vector<uint32_t> SourcesNextUses;
@@ -638,11 +643,13 @@ void ConstrainedRAPass::Run(IREmitter* IREmit_) {
       }
 
       // Remap sources last, since AssignReg can shuffle.
-      for (auto s = 0; s < IR::GetRAArgs(IROp->Op); ++s) {
-        Ref Remapped = SSAToNewSSA[IROp->Args[s].ID().Value];
+      if (AnyRemapped) {
+        for (auto s = 0; s < IR::GetRAArgs(IROp->Op); ++s) {
+          Ref Remapped = SSAToNewSSA[IROp->Args[s].ID().Value];
 
-        if (Remapped != nullptr) {
-          IREmit->ReplaceNodeArgument(CodeNode, s, Remapped);
+          if (Remapped != nullptr) {
+            IREmit->ReplaceNodeArgument(CodeNode, s, Remapped);
+          }
         }
       }