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https://github.com/FEX-Emu/FEX.git
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Dispatcher: Implement ARM64EC SRA setup entrypoints
While the ARM64EC ABI mostly matches FEX's SRA, the stack still needs to be switched to the emulator stack and target RIP stored into the FEX context before jumping to the dispatcher loop.
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@ -67,6 +67,10 @@ constexpr auto REG_AF = FEXCore::ARMEmitter::Reg::r24;
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// Vector temporaries
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constexpr auto VTMP1 = FEXCore::ARMEmitter::VReg::v16;
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constexpr auto VTMP2 = FEXCore::ARMEmitter::VReg::v17;
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// Entry/Exit ABI
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constexpr auto EC_CALL_CHECKER_PC_REG = FEXCore::ARMEmitter::XReg::x9;
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constexpr auto EC_ENTRY_CPUAREA_REG = FEXCore::ARMEmitter::XReg::x17;
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#endif
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// Predicate register temporaries (used when AVX support is enabled)
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@ -65,6 +65,8 @@ void Dispatcher::EmitDispatcher() {
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// These structures are not included in the standard Windows headers, define them here
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static constexpr size_t TEBCPUAreaOffset = 0x1788;
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static constexpr size_t CPUAreaInSyscallCallbackOffset = 0x1;
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static constexpr size_t CPUAreaEmulatorStackLimitOffset = 0x8;
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static constexpr size_t CPUAreaEmulatorDataOffset = 0x30;
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ARMEmitter::SingleUseForwardLabel ExitEC;
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#endif
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ARMEmitter::SingleUseForwardLabel l_CompileBlock;
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@ -85,20 +87,45 @@ void Dispatcher::EmitDispatcher() {
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AbsoluteLoopTopAddressFillSRA = GetCursorAddress<uint64_t>();
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FillStaticRegs();
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ARMEmitter::BiDirectionalLabel LoopTop {};
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#ifdef _M_ARM_64EC
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b(&LoopTop);
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AbsoluteLoopTopAddressEnterECFillSRA = GetCursorAddress<uint64_t>();
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ldr(STATE, EC_ENTRY_CPUAREA_REG, CPUAreaEmulatorDataOffset);
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FillStaticRegs();
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// Enter JIT
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b(&LoopTop);
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AbsoluteLoopTopAddressEnterEC = GetCursorAddress<uint64_t>();
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// Load ThreadState and write the target PC there
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ldr(STATE, EC_ENTRY_CPUAREA_REG, CPUAreaEmulatorDataOffset);
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str(EC_CALL_CHECKER_PC_REG, STATE_PTR(CpuStateFrame, State.rip));
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// Swap stacks to the emulator stack
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ldr(TMP1, EC_ENTRY_CPUAREA_REG, CPUAreaEmulatorStackLimitOffset);
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add(ARMEmitter::Size::i64Bit, StaticRegisters[X86State::REG_RSP], ARMEmitter::Reg::rsp, 0);
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add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, TMP1, 0);
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if (EmitterCTX->HostFeatures.SupportsSVE) {
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ptrue(ARMEmitter::SubRegSize::i8Bit, PRED_TMP_16B, ARMEmitter::PredicatePattern::SVE_VL16);
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}
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// Enter JIT
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#endif
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// We want to ensure that we are 16 byte aligned at the top of this loop
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Align16B();
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ARMEmitter::BiDirectionalLabel FullLookup {};
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ARMEmitter::BiDirectionalLabel CallBlock {};
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ARMEmitter::BackwardLabel LoopTop {};
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Bind(&LoopTop);
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AbsoluteLoopTopAddress = GetCursorAddress<uint64_t>();
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// Load in our RIP
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// Don't modify TMP3 since it contains our RIP once the block doesn't exist
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// IMPORTANT: Pointers.Common.ExitFunctionEC callsites/implementations need to be
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// adjusted accordingly if this changes.
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auto RipReg = TMP3;
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ldr(RipReg, STATE_PTR(CpuStateFrame, State.rip));
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@ -519,6 +546,8 @@ void Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState* Thread)
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Common.DispatcherLoopTop = AbsoluteLoopTopAddress;
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Common.DispatcherLoopTopFillSRA = AbsoluteLoopTopAddressFillSRA;
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Common.DispatcherLoopTopEnterEC = AbsoluteLoopTopAddressEnterEC;
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Common.DispatcherLoopTopEnterECFillSRA = AbsoluteLoopTopAddressEnterECFillSRA;
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Common.ExitFunctionLinker = ExitFunctionLinkerAddress;
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Common.ThreadStopHandlerSpillSRA = ThreadStopHandlerAddressSpillSRA;
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Common.ThreadPauseHandlerSpillSRA = ThreadPauseHandlerAddressSpillSRA;
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@ -47,6 +47,8 @@ public:
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uint64_t ThreadStopHandlerAddressSpillSRA {};
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uint64_t AbsoluteLoopTopAddress {};
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uint64_t AbsoluteLoopTopAddressFillSRA {};
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uint64_t AbsoluteLoopTopAddressEnterEC {};
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uint64_t AbsoluteLoopTopAddressEnterECFillSRA {};
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uint64_t ThreadPauseHandlerAddress {};
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uint64_t ThreadPauseHandlerAddressSpillSRA {};
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uint64_t ExitFunctionLinkerAddress {};
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@ -257,6 +257,8 @@ struct JITPointers {
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* @{ */
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uint64_t DispatcherLoopTop {};
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uint64_t DispatcherLoopTopFillSRA {};
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uint64_t DispatcherLoopTopEnterEC {};
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uint64_t DispatcherLoopTopEnterECFillSRA {};
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uint64_t ExitFunctionLinker {};
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uint64_t ThreadStopHandlerSpillSRA {};
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uint64_t ThreadPauseHandlerSpillSRA {};
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