FEX-Emu/FEX
1
0
Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2024-12-17 02:47:48 +00:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity

IR: Remove Entry from OP_HEADER, pass as parameter to CompileCode

Browse Source
This commit is contained in:
Stefanos Kornilios Mitsis Poiitidis 2021-04-19 18:57:07 +03:00
parent 60671ee6cb
commit b45b7c3441
29 changed files with 54 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
External/FEXCore/Source/Interface/Core/Core.cpp vendored
View File

@ -125,7 +125,7 @@ namespace DefaultFallbackCore {
void Initialize() override {}
bool NeedsOpDispatch() override { return false; }
void *CompileCode(FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override {
void *CompileCode(uint64_t Entry, FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override {
LogMan::Msg::E("Fell back to default code handler at RIP: 0x%lx", ThreadState->CurrentFrame->State.rip);
return nullptr;
}
@ -818,8 +818,6 @@ namespace FEXCore::Context {
if (hash == AOTEntry->second.crc) {
IRList = AOTEntry->second.IR;
//LogMan::Msg::D("using %s + %lx -> %lx\n", file->second.fileid.c_str(), AOTEntry->first, GuestRIP);
// relocate
IRList->GetHeader()->Entry = GuestRIP;
RAData = AOTEntry->second.RAData;
DebugData = new FEXCore::Core::DebugData();
@ -855,7 +853,7 @@ namespace FEXCore::Context {
}
// Attempt to get the CPU backend to compile this code
return { Thread->CPUBackend->CompileCode(IRList, DebugData, RAData), IRList, DebugData, RAData, GeneratedIR, StartAddr, Length};
return { Thread->CPUBackend->CompileCode(GuestRIP, IRList, DebugData, RAData), IRList, DebugData, RAData, GeneratedIR, StartAddr, Length};
}
bool Context::LoadAOTIRCache(std::istream &stream) {

2
External/FEXCore/Source/Interface/Core/Interpreter/InterpreterClass.h vendored
View File

@ -23,7 +23,7 @@ class InterpreterCore final : public CPUBackend {
public:
explicit InterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread);
std::string GetName() override { return "Interpreter"; }
void *CompileCode(FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
void *CompileCode(uint64_t Entry, FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
void *MapRegion(void* HostPtr, uint64_t, uint64_t) override { return HostPtr; }

4
External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.cpp vendored
View File

@ -31,7 +31,7 @@ static void InterpreterExecution(FEXCore::Core::CpuStateFrame *Frame) {
auto LocalEntry = Thread->LocalIRCache.find(Thread->CurrentFrame->State.rip);
InterpreterOps::InterpretIR(Thread, LocalEntry->second.IR.get(), LocalEntry->second.DebugData.get());
InterpreterOps::InterpretIR(Thread, Thread->CurrentFrame->State.rip, LocalEntry->second.IR.get(), LocalEntry->second.DebugData.get());
}
bool InterpreterCore::HandleSIGBUS(int Signal, void *info, void *ucontext) {
@ -111,7 +111,7 @@ InterpreterCore::InterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::
}
}
void *InterpreterCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) {
void *InterpreterCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRListView const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) {
return reinterpret_cast<void*>(InterpreterExecution);
}

8
External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp vendored
View File

@ -922,7 +922,7 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header *IROp, FallbackInfo *Inf
return false;
}
void InterpreterOps::InterpretIR(FEXCore::Core::InternalThreadState *Thread, FEXCore::IR::IRListView *CurrentIR, FEXCore::Core::DebugData *DebugData) {
void InterpreterOps::InterpretIR(FEXCore::Core::InternalThreadState *Thread, uint64_t Entry, FEXCore::IR::IRListView *CurrentIR, FEXCore::Core::DebugData *DebugData) {
volatile void* stack = alloca(0);
// Debug data is only passed in debug builds
@ -978,7 +978,7 @@ void InterpreterOps::InterpretIR(FEXCore::Core::InternalThreadState *Thread, FEX
case IR::OP_VALIDATECODE: {
auto Op = IROp->C<IR::IROp_ValidateCode>();
auto CodePtr = CurrentIR->GetHeader()->Entry + Op->Offset;
auto CodePtr = Entry + Op->Offset;
if (memcmp((void*)CodePtr, &Op->CodeOriginalLow, Op->CodeLength) != 0) {
GD = 1;
} else {
@ -988,7 +988,7 @@ void InterpreterOps::InterpretIR(FEXCore::Core::InternalThreadState *Thread, FEX
}
case IR::OP_REMOVECODEENTRY: {
Thread->CTX->RemoveCodeEntry(Thread, CurrentIR->GetHeader()->Entry);
Thread->CTX->RemoveCodeEntry(Thread, Entry);
break;
}
@ -1207,7 +1207,7 @@ void InterpreterOps::InterpretIR(FEXCore::Core::InternalThreadState *Thread, FEX
case IR::OP_ENTRYPOINTOFFSET: {
auto Op = IROp->C<IR::IROp_EntrypointOffset>();
GD = CurrentIR->GetHeader()->Entry + Op->Offset;
GD = Entry + Op->Offset;
break;
}
case IR::OP_CONSTANT: {

2
External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h vendored
View File

@ -36,7 +36,7 @@ namespace FEXCore::CPU {
class InterpreterOps {
public:
static void InterpretIR(FEXCore::Core::InternalThreadState *Thread, FEXCore::IR::IRListView *CurrentIR, FEXCore::Core::DebugData *DebugData);
static void InterpretIR(FEXCore::Core::InternalThreadState *Thread, uint64_t Entry, FEXCore::IR::IRListView *CurrentIR, FEXCore::Core::DebugData *DebugData);
static bool GetFallbackHandler(IR::IROp_Header *IROp, FallbackInfo *Info);
};
};

2
External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp vendored
View File

@ -59,7 +59,7 @@ DEF_OP(Constant) {
DEF_OP(EntrypointOffset) {
auto Op = IROp->C<IR::IROp_EntrypointOffset>();
auto Constant = IR->GetHeader()->Entry + Op->Offset;
auto Constant = Entry + Op->Offset;
auto Dst = GetReg<RA_64>(Node);
LoadConstant(Dst, Constant);
}

4
External/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp vendored
View File

@ -262,7 +262,7 @@ DEF_OP(ValidateCode) {
int idx = 0;
LoadConstant(GetReg<RA_64>(Node), 0);
LoadConstant(x0, IR->GetHeader()->Entry + Op->Offset);
LoadConstant(x0, Entry + Op->Offset);
LoadConstant(x1, 1);
while (len >= 8)
@ -311,7 +311,7 @@ DEF_OP(RemoveCodeEntry) {
PushDynamicRegsAndLR();
mov(x0, STATE);
LoadConstant(x1, IR->GetHeader()->Entry);
LoadConstant(x1, Entry);
LoadConstant(x2, reinterpret_cast<uintptr_t>(&Context::Context::RemoveCodeEntryFromJit));
SpillStaticRegs();

17
External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp vendored
View File

@ -669,7 +669,7 @@ bool Arm64JITCore::IsInlineEntrypointOffset(const IR::OrderedNodeWrapper& WNode,
if (OpHeader->Op == IR::IROps::OP_INLINEENTRYPOINTOFFSET) {
auto Op = OpHeader->C<IR::IROp_InlineEntrypointOffset>();
if (Value) {
*Value = IR->GetHeader()->Entry + Op->Offset;
*Value = Entry + Op->Offset;
}
return true;
} else {
@ -694,17 +694,18 @@ bool Arm64JITCore::IsGPR(uint32_t Node) {
return Class == IR::GPRClass || Class == IR::GPRFixedClass;
}
void *Arm64JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) {
void *Arm64JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRListView const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) {
using namespace aarch64;
JumpTargets.clear();
uint32_t SSACount = IR->GetSSACount();
this->Entry = Entry;
this->RAData = RAData;
auto HeaderOp = IR->GetHeader();
#ifndef NDEBUG
LoadConstant(x0, HeaderOp->Entry);
LoadConstant(x0, Entry);
#endif
this->IR = IR;
@ -736,7 +737,7 @@ void *Arm64JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView const *
// X4-r18 = RA
auto Buffer = GetBuffer();
auto Entry = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
auto GuestEntry = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
if (CTX->GetGdbServerStatus()) {
aarch64::Label RunBlock;
@ -753,7 +754,7 @@ void *Arm64JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView const *
cbz(w0, &RunBlock);
{
// Make sure RIP is syncronized to the context
LoadConstant(x0, HeaderOp->Entry);
LoadConstant(x0, Entry);
str(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)));
// Stop the thread
@ -827,15 +828,15 @@ void *Arm64JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView const *
FinalizeCode();
auto CodeEnd = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
CPU.EnsureIAndDCacheCoherency(reinterpret_cast<void*>(Entry), CodeEnd - reinterpret_cast<uint64_t>(Entry));
CPU.EnsureIAndDCacheCoherency(reinterpret_cast<void*>(GuestEntry), CodeEnd - reinterpret_cast<uint64_t>(GuestEntry));
if (DebugData) {
DebugData->HostCodeSize = reinterpret_cast<uintptr_t>(CodeEnd) - reinterpret_cast<uintptr_t>(Entry);
DebugData->HostCodeSize = reinterpret_cast<uintptr_t>(CodeEnd) - reinterpret_cast<uintptr_t>(GuestEntry);
}
this->IR = nullptr;
return reinterpret_cast<void*>(Entry);
return reinterpret_cast<void*>(GuestEntry);
}
uint64_t Arm64JITCore::ExitFunctionLink(Arm64JITCore *core, FEXCore::Core::CpuStateFrame *Frame, uint64_t *record) {

3
External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h vendored
View File

@ -47,7 +47,7 @@ public:
~Arm64JITCore() override;
std::string GetName() override { return "JIT"; }
void *CompileCode(FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
void *CompileCode(uint64_t Entry, FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
void *MapRegion(void* HostPtr, uint64_t, uint64_t) override { return HostPtr; }
@ -70,6 +70,7 @@ private:
FEXCore::Context::Context *CTX;
FEXCore::Core::InternalThreadState *ThreadState;
FEXCore::IR::IRListView const *IR;
uint64_t Entry;
std::map<IR::OrderedNodeWrapper::NodeOffsetType, aarch64::Label> JumpTargets;

2
External/FEXCore/Source/Interface/Core/JIT/x86_64/ALUOps.cpp vendored
View File

@ -32,7 +32,7 @@ DEF_OP(Constant) {
DEF_OP(EntrypointOffset) {
auto Op = IROp->C<IR::IROp_EntrypointOffset>();
auto Constant = IR->GetHeader()->Entry + Op->Offset;
auto Constant = Entry + Op->Offset;
mov(GetDst<RA_64>(Node), Constant);
}

4
External/FEXCore/Source/Interface/Core/JIT/x86_64/BranchOps.cpp vendored
View File

@ -253,7 +253,7 @@ DEF_OP(ValidateCode) {
int idx = 0;
xor_(GetDst<RA_64>(Node), GetDst<RA_64>(Node));
mov(rax, IR->GetHeader()->Entry + Op->Offset);
mov(rax, Entry + Op->Offset);
mov(rbx, 1);
while (len >= 4) {
cmp(dword[rax + idx], *(uint32_t*)(OldCode + idx));
@ -286,7 +286,7 @@ DEF_OP(RemoveCodeEntry) {
sub(rsp, 8); // Align
mov(rdi, STATE);
mov(rax, IR->GetHeader()->Entry); // imm64 move
mov(rax, Entry); // imm64 move
mov(rsi, rax);

15
External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp vendored
View File

@ -530,7 +530,7 @@ bool X86JITCore::IsInlineEntrypointOffset(const IR::OrderedNodeWrapper& WNode, u
if (OpHeader->Op == IR::IROps::OP_INLINEENTRYPOINTOFFSET) {
auto Op = OpHeader->C<IR::IROp_InlineEntrypointOffset>();
if (Value) {
*Value = IR->GetHeader()->Entry + Op->Offset;
*Value = Entry + Op->Offset;
}
return true;
} else {
@ -571,10 +571,11 @@ std::tuple<X86JITCore::SetCC, X86JITCore::CMovCC, X86JITCore::JCC> X86JITCore::G
return { &CodeGenerator::sete , &CodeGenerator::cmove , &CodeGenerator::je };
}
void *X86JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) {
void *X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRListView const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) {
JumpTargets.clear();
uint32_t SSACount = IR->GetSSACount();
this->Entry = Entry;
this->RAData = RAData;
// Fairly excessive buffer range to make sure we don't overflow
@ -583,7 +584,7 @@ void *X86JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView const *IR
ThreadState->CTX->ClearCodeCache(ThreadState, false);
}
void *Entry = getCurr<void*>();
void *GuestEntry = getCurr<void*>();
this->IR = IR;
if (CTX->GetGdbServerStatus()) {
@ -614,7 +615,7 @@ void *X86JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView const *IR
}
#ifdef BLOCKSTATS
BlockSamplingData::BlockData *SamplingData = CTX->BlockData->GetBlockData(HeaderOp->Entry);
BlockSamplingData::BlockData *SamplingData = CTX->BlockData->GetBlockData(Entry);
if (GetSamplingData) {
mov(rcx, reinterpret_cast<uintptr_t>(SamplingData));
rdtsc();
@ -731,15 +732,15 @@ void *X86JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView const *IR
}
PendingTargetLabel = nullptr;
void *Exit = getCurr<void*>();
void *GuestExit = getCurr<void*>();
this->IR = nullptr;
ready();
if (DebugData) {
DebugData->HostCodeSize = reinterpret_cast<uintptr_t>(Exit) - reinterpret_cast<uintptr_t>(Entry);
DebugData->HostCodeSize = reinterpret_cast<uintptr_t>(GuestExit) - reinterpret_cast<uintptr_t>(GuestEntry);
}
return Entry;
return GuestEntry;
}
uint64_t X86JITCore::ExitFunctionLink(X86JITCore *core, FEXCore::Core::CpuStateFrame *Frame, uint64_t *record) {

3
External/FEXCore/Source/Interface/Core/JIT/x86_64/JITClass.h vendored
View File

@ -66,7 +66,7 @@ public:
explicit X86JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, CodeBuffer Buffer, bool CompileThread);
~X86JITCore() override;
std::string GetName() override { return "JIT"; }
void *CompileCode(FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
void *CompileCode(uint64_t Entry, FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
void *MapRegion(void* HostPtr, uint64_t, uint64_t) override { return HostPtr; }
@ -84,6 +84,7 @@ private:
FEXCore::Core::InternalThreadState *ThreadState;
FEXCore::IR::IRListView const *IR;
std::unique_ptr<FEXCore::CPU::Dispatcher> Dispatcher;
uint64_t Entry;
std::unordered_map<IR::OrderedNodeWrapper::NodeOffsetType, Label> JumpTargets;
Xbyak::util::Cpu Features{};

4
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp vendored
View File

@ -4537,7 +4537,7 @@ void OpDispatchBuilder::CreateJumpBlocks(std::vector<FEXCore::Frontend::Decoder:
void OpDispatchBuilder::BeginFunction(uint64_t RIP, std::vector<FEXCore::Frontend::Decoder::DecodedBlocks> const *Blocks) {
Entry = RIP;
auto IRHeader = _IRHeader(InvalidNode, RIP, 0);
auto IRHeader = _IRHeader(InvalidNode, 0);
Current_Header = IRHeader.first;
Current_HeaderNode = IRHeader;
CreateJumpBlocks(Blocks);
@ -4782,7 +4782,7 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(FEXCore::IR::RegisterClass
OrderedNode *OpDispatchBuilder::GetDynamicPC(FEXCore::X86Tables::DecodedOp const& Op, int64_t Offset) {
uint8_t GPRSize = CTX->Config.Is64BitMode ? 8 : 4;
return _EntrypointOffset(Op->PC + Op->InstSize + Offset - Current_Header->Entry, GPRSize);
return _EntrypointOffset(Op->PC + Op->InstSize + Offset - Entry, GPRSize);
}
OrderedNode *OpDispatchBuilder::LoadSource(FEXCore::IR::RegisterClassType Class, FEXCore::X86Tables::DecodedOp const& Op, FEXCore::X86Tables::DecodedOperand const& Operand, uint32_t Flags, int8_t Align, bool LoadData, bool ForceLoad) {

2
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h vendored
View File

@ -88,7 +88,7 @@ public:
uint8_t GPRSize = CTX->Config.Is64BitMode ? 8 : 4;
// If we don't have a jump target to a new block then we have to leave
// Set the RIP to the next instruction and leave
auto RelocatedNextRIP = _EntrypointOffset(NextRIP - Current_Header->Entry, GPRSize);
auto RelocatedNextRIP = _EntrypointOffset(NextRIP - Entry, GPRSize);
_ExitFunction(RelocatedNextRIP);
}
else if (it != JumpTargets.end()) {

1
External/FEXCore/Source/Interface/IR/IR.json vendored
View File

@ -79,7 +79,6 @@
"Blocks"
],
"Args": [
"uint64_t", "Entry",
"uint32_t", "BlockCount"
]
},

1
External/FEXCore/Source/Interface/IR/IRDumper.cpp vendored
View File

@ -167,7 +167,6 @@ void Dump(std::stringstream *out, IRListView const* IR, IR::RegisterAllocationDa
++CurrentIndent;
AddIndent();
*out << "(%ssa0) " << "IRHeader ";
*out << "#0x" << std::hex << HeaderOp->Entry << ", ";
*out << "%ssa" << HeaderOp->Blocks.ID() << ", ";
*out << "#" << std::dec << HeaderOp->BlockCount << std::endl;

6
External/FEXCore/Source/Interface/IR/IRParser.cpp vendored
View File

@ -497,13 +497,11 @@ class IRParser: public FEXCore::IR::IREmitter {
return false;
}
auto Entry = DecodeValue<uint64_t>(Def.Args[0]);
auto CodeBlockCount = DecodeValue<uint64_t>(Def.Args[2]);
auto CodeBlockCount = DecodeValue<uint64_t>(Def.Args[1]);
if (!CheckPrintError(Def, Entry.first)) return false;
if (!CheckPrintError(Def, CodeBlockCount.first)) return false;
IRHeader = _IRHeader(InvalidNode, Entry.second, CodeBlockCount.second);
IRHeader = _IRHeader(InvalidNode, CodeBlockCount.second);
}
SetWriteCursor(nullptr); // isolate the header from everything following

2
External/FEXCore/Source/Interface/IR/Passes/IRCompaction.cpp vendored
View File

@ -84,7 +84,7 @@ bool IRCompaction::Run(IREmitter *IREmit) {
// Zero is always zero(invalid)
OldToNewRemap[0].NodeID = 0;
auto LocalHeaderOp = LocalBuilder._IRHeader(OrderedNodeWrapper::WrapOffset(0).GetNode(ListBegin), HeaderOp->Entry, HeaderOp->BlockCount);
auto LocalHeaderOp = LocalBuilder._IRHeader(OrderedNodeWrapper::WrapOffset(0).GetNode(ListBegin), HeaderOp->BlockCount);
OldToNewRemap[CurrentIR.GetID(HeaderNode)].NodeID = LocalIR.GetID(LocalHeaderOp.Node);
{

2
External/FEXCore/include/FEXCore/Core/CPUBackend.h vendored
View File

@ -51,7 +51,7 @@ class LLVMCore;
* @return An executable function pointer that is theoretically compiled from this point.
* Is actually a function pointer of type `void (FEXCore::Core::ThreadState *Thread)
*/
virtual void *CompileCode(FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) = 0;
virtual void *CompileCode(uint64_t Entry, FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) = 0;
/**
* @brief Function for mapping memory in to the CPUBackend's visible space. Allows setting up virtual mappings if required

4
Source/CommonCore/HostFactory.cpp
View File

@ -30,7 +30,7 @@ namespace HostFactory {
explicit HostCore(FEXCore::Context::Context* CTX, FEXCore::Core::InternalThreadState *Thread, bool Fallback);
~HostCore() override;
std::string GetName() override { return "Host Core"; }
void* CompileCode(FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
void* CompileCode(uint64_t Entry, FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
void *MapRegion(void *HostPtr, uint64_t VirtualGuestPtr, uint64_t Size) override {
return HostPtr;
@ -170,7 +170,7 @@ namespace HostFactory {
ready();
}
void* HostCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) {
void* HostCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) {
return nullptr;
}

2
Source/Tests/IRLoader/Loader.cpp
View File

@ -20,7 +20,7 @@ namespace FEX::IRLoader {
if (ParsedCode) {
auto NewIR = ParsedCode->ViewIR();
EntryRIP = NewIR.GetHeader()->Entry;
EntryRIP = 0x40000;
std::stringstream out;
FEXCore::IR::Dump(&out, &NewIR, nullptr);

2
unittests/IR/Basic/MemoryData.ir
View File

@ -12,7 +12,7 @@
;}
;%endif
(%ssa1) IRHeader #0x1000, %ssa2, #0
(%ssa1) IRHeader %ssa2, #0
(%ssa2) CodeBlock %start, %end, %ssa1
(%start i0) BeginBlock %ssa2
%Addr i64 = Constant #0x100000

2
unittests/IR/Basic/Sbfe.ir
View File

@ -17,7 +17,7 @@
;}
;%endif
(%ssa1) IRHeader #0x1000, %ssa2, #0
(%ssa1) IRHeader %ssa2, #0
(%ssa2) CodeBlock %start, %end, %ssa1
(%start i0) BeginBlock %ssa2
%Addr1 i64 = Constant #0x1000000

2
unittests/IR/Basic/SetGPR.ir
View File

@ -6,7 +6,7 @@
;}
;%endif
(%ssa1) IRHeader #0x1000, %ssa2, #0
(%ssa1) IRHeader %ssa2, #0
(%ssa2) CodeBlock %ssa6, %ssa8, %ssa3
(%ssa6 i0) BeginBlock %ssa2
%Value i64 = Constant #0x4142434445464748

2
unittests/IR/Correctness/AddTruncate.ir
View File

@ -16,7 +16,7 @@
;}
;%endif
(%ssa1) IRHeader #0x1000, %ssa2, #0
(%ssa1) IRHeader %ssa2, #0
(%ssa2) CodeBlock %ssa6, %ssa12, %ssa1
(%ssa6 i0) BeginBlock %ssa2
%AddrA i64 = Constant #0x1000000

2
unittests/IR/Correctness/FPRStoreTruncate.ir
View File

@ -18,7 +18,7 @@
(%ssa1) IRHeader #0x1000, %ssa2, #0
(%ssa1) IRHeader %ssa2, #0
(%ssa2) CodeBlock %ssa6, %end, %begin
(%begin i0) BeginBlock %ssa2
; Clear registers

2
unittests/IR/Correctness/LeftShiftTruncate.ir
View File

@ -16,7 +16,7 @@
;}
;%endif
(%ssa1) IRHeader #0x1000, %ssa2, #0
(%ssa1) IRHeader %ssa2, #0
(%ssa2) CodeBlock %ssa6, %ssa12, %ssa1
(%ssa6 i0) BeginBlock %ssa2
%AddrA i64 = Constant #0x1000000

2
unittests/IR/Correctness/SubTruncate.ir
View File

@ -16,7 +16,7 @@
;}
;%endif
(%ssa1) IRHeader #0x1000, %ssa2, #0
(%ssa1) IRHeader %ssa2, #0
(%ssa2) CodeBlock %ssa6, %ssa12, %ssa1
(%ssaStart i0) BeginBlock %ssa2
%AddrA i64 = Constant #0x1000000