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InstCountCI: Update

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig 2024-04-05 16:16:58 -04:00
parent 95589f6172
commit b54d4931fb
4 changed files with 266 additions and 325 deletions
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189
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
View File

@ -1676,15 +1676,15 @@
"uxtb w21, w5",
"lsl w22, w20, w21",
"bfxil x4, x22, #0, #8",
"cbz x21, #+0x24",
"cbz w21, #+0x24",
"cmn wzr, w22, lsl #24",
"mov w23, #0x8",
"sub w21, w23, w21",
"lsr w21, w20, w21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
"eor w20, w20, w22",
"rmif x20, #7, #nzcV"
"mov w0, #0x8",
"sub w0, w0, w21",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"rmif x0, #63, #nzCv",
"rmif x2, #7, #nzcV"
]
},
"shr al, cl": {
@ -1695,14 +1695,14 @@
"uxtb w21, w5",
"lsr w22, w20, w21",
"bfxil x4, x22, #0, #8",
"cbz x21, #+0x20",
"cbz w21, #+0x20",
"cmn wzr, w22, lsl #24",
"sub x21, x21, #0x1 (1)",
"lsr w21, w20, w21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
"eor w20, w20, w22",
"rmif x20, #7, #nzcV"
"sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"rmif x0, #63, #nzCv",
"rmif x2, #7, #nzcV"
]
},
"sar al, cl": {
@ -1714,12 +1714,12 @@
"sxtb x20, w20",
"asr w22, w20, w21",
"bfxil x4, x22, #0, #8",
"cbz x21, #+0x18",
"cbz w21, #+0x18",
"cmn wzr, w22, lsl #24",
"sub x21, x21, #0x1 (1)",
"lsr x20, x20, x21",
"rmif x20, #63, #nzCv",
"mov x26, x22"
"mov x26, x22",
"sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0",
"rmif x0, #63, #nzCv"
]
},
"rol ax, cl": {
@ -1943,53 +1943,46 @@
"uxth w21, w5",
"lsl w22, w20, w21",
"bfxil x4, x22, #0, #16",
"cbz x21, #+0x24",
"cbz w21, #+0x24",
"cmn wzr, w22, lsl #16",
"mov w23, #0x10",
"sub w21, w23, w21",
"lsr w21, w20, w21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
"eor w20, w20, w22",
"rmif x20, #15, #nzcV"
"mov w0, #0x10",
"sub w0, w0, w21",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"rmif x0, #63, #nzCv",
"rmif x2, #15, #nzcV"
]
},
"shl eax, cl": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"lsl w22, w20, w21",
"mov x4, x22",
"cbz x21, #+0x24",
"tst w22, w22",
"mov w23, #0x20",
"sub w21, w23, w21",
"lsr w21, w20, w21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
"eor w20, w20, w22",
"rmif x20, #31, #nzcV"
"lsl w4, w20, w21",
"cbz w21, #+0x1c",
"ands w26, w4, w4",
"neg w0, w21",
"lsr w0, w20, w0",
"eor w2, w20, w4",
"rmif x0, #63, #nzCv",
"rmif x2, #31, #nzcV"
]
},
"shl rax, cl": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x21, x5",
"lsl x22, x20, x21",
"mov x4, x22",
"cbz x21, #+0x24",
"tst x22, x22",
"mov w23, #0x40",
"sub x21, x23, x21",
"lsr x21, x20, x21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
"eor x20, x20, x22",
"rmif x20, #63, #nzcV"
"lsl x4, x20, x5",
"cbz x5, #+0x1c",
"ands x26, x4, x4",
"neg x0, x5",
"lsr x0, x20, x0",
"eor x2, x20, x4",
"rmif x0, #63, #nzCv",
"rmif x2, #63, #nzcV"
]
},
"shr ax, cl": {
@ -2000,50 +1993,45 @@
"uxth w21, w5",
"lsr w22, w20, w21",
"bfxil x4, x22, #0, #16",
"cbz x21, #+0x20",
"cbz w21, #+0x20",
"cmn wzr, w22, lsl #16",
"sub x21, x21, #0x1 (1)",
"lsr w21, w20, w21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
"eor w20, w20, w22",
"rmif x20, #15, #nzcV"
"sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"rmif x0, #63, #nzCv",
"rmif x2, #15, #nzcV"
]
},
"shr eax, cl": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"lsr w22, w20, w21",
"mov x4, x22",
"cbz x21, #+0x20",
"tst w22, w22",
"sub x21, x21, #0x1 (1)",
"lsr w21, w20, w21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
"eor w20, w20, w22",
"rmif x20, #31, #nzcV"
"lsr w4, w20, w21",
"cbz w21, #+0x1c",
"ands w26, w4, w4",
"sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0",
"eor w2, w20, w4",
"rmif x0, #63, #nzCv",
"rmif x2, #31, #nzcV"
]
},
"shr rax, cl": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x21, x5",
"lsr x22, x20, x21",
"mov x4, x22",
"cbz x21, #+0x20",
"tst x22, x22",
"sub x21, x21, #0x1 (1)",
"lsr x21, x20, x21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
"eor x20, x20, x22",
"rmif x20, #63, #nzcV"
"lsr x4, x20, x5",
"cbz x5, #+0x1c",
"ands x26, x4, x4",
"sub x0, x5, #0x1 (1)",
"lsr x0, x20, x0",
"eor x2, x20, x4",
"rmif x0, #63, #nzCv",
"rmif x2, #63, #nzcV"
]
},
"sar ax, cl": {
@ -2055,44 +2043,39 @@
"sxth x20, w20",
"asr w22, w20, w21",
"bfxil x4, x22, #0, #16",
"cbz x21, #+0x18",
"cbz w21, #+0x18",
"cmn wzr, w22, lsl #16",
"sub x21, x21, #0x1 (1)",
"lsr x20, x20, x21",
"rmif x20, #63, #nzCv",
"mov x26, x22"
"mov x26, x22",
"sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0",
"rmif x0, #63, #nzCv"
]
},
"sar eax, cl": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"asr w22, w20, w21",
"mov x4, x22",
"cbz x21, #+0x18",
"tst w22, w22",
"sub x21, x21, #0x1 (1)",
"lsr w20, w20, w21",
"rmif x20, #63, #nzCv",
"mov x26, x22"
"asr w4, w20, w21",
"cbz w21, #+0x14",
"ands w26, w4, w4",
"sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0",
"rmif x0, #63, #nzCv"
]
},
"sar rax, cl": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x21, x5",
"asr x22, x20, x21",
"mov x4, x22",
"cbz x21, #+0x18",
"tst x22, x22",
"sub x21, x21, #0x1 (1)",
"lsr x20, x20, x21",
"rmif x20, #63, #nzCv",
"mov x26, x22"
"asr x4, x20, x5",
"cbz x5, #+0x14",
"ands x26, x4, x4",
"sub x0, x5, #0x1 (1)",
"lsr x0, x20, x0",
"rmif x0, #63, #nzCv"
]
},
"test bl, 1": {

53
unittests/InstructionCountCI/FlagM/Secondary.json
View File

@ -794,19 +794,19 @@
"csel x20, x21, x20, eq",
"bfxil x4, x20, #0, #16",
"msr nzcv, x23",
"cbz x22, #+0x24",
"cbz w22, #+0x24",
"cmn wzr, w20, lsl #16",
"mov w23, #0x10",
"sub w22, w23, w22",
"lsr w22, w21, w22",
"rmif x22, #63, #nzCv",
"mov x26, x20",
"eor w20, w21, w20",
"rmif x20, #15, #nzcV"
"mov w0, #0x10",
"sub w0, w0, w22",
"lsr w0, w21, w0",
"eor w2, w21, w20",
"rmif x0, #63, #nzCv",
"rmif x2, #15, #nzcV"
]
},
"shld eax, ebx, cl": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 19,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov w20, w7",
@ -821,19 +821,17 @@
"csel x20, x21, x20, eq",
"mov w4, w20",
"msr nzcv, x23",
"cbz x22, #+0x24",
"tst w20, w20",
"mov w23, #0x20",
"sub w22, w23, w22",
"lsr w22, w21, w22",
"rmif x22, #63, #nzCv",
"mov x26, x20",
"eor w20, w21, w20",
"rmif x20, #31, #nzcV"
"cbz w22, #+0x1c",
"ands w26, w20, w20",
"neg w0, w22",
"lsr w0, w21, w0",
"eor w2, w21, w20",
"rmif x0, #63, #nzCv",
"rmif x2, #31, #nzcV"
]
},
"shld rax, rbx, cl": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 17,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov x20, x4",
@ -844,18 +842,15 @@
"orr x22, x23, x22",
"mrs x23, nzcv",
"cmp x21, #0x0 (0)",
"csel x22, x20, x22, eq",
"mov x4, x22",
"csel x4, x20, x22, eq",
"msr nzcv, x23",
"cbz x21, #+0x24",
"tst x22, x22",
"mov w23, #0x40",
"sub x21, x23, x21",
"lsr x21, x20, x21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
"eor x20, x20, x22",
"rmif x20, #63, #nzcV"
"cbz x21, #+0x1c",
"ands x26, x4, x4",
"neg x0, x21",
"lsr x0, x20, x0",
"eor x2, x20, x4",
"rmif x0, #63, #nzCv",
"rmif x2, #63, #nzcV"
]
},
"bts ax, bx": {

273
unittests/InstructionCountCI/PrimaryGroup.json
View File

@ -2024,52 +2024,50 @@
]
},
"shl al, cl": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 16,
"Comment": "GROUP2 0xd2 /4",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"uxtb w21, w5",
"lsl w22, w20, w21",
"bfxil x4, x22, #0, #8",
"cbz x21, #+0x34",
"cbz w21, #+0x30",
"cmn wzr, w22, lsl #24",
"mov w23, #0x8",
"sub w21, w23, w21",
"lsr w21, w20, w21",
"ubfx x21, x21, #0, #1",
"mrs x23, nzcv",
"orr w21, w23, w21, lsl #29",
"mov x26, x22",
"eor w20, w20, w22",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
"mov w0, #0x8",
"sub w0, w0, w21",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"lsr w2, w2, #7",
"bfi w1, w2, #28, #1",
"msr nzcv, x1"
]
},
"shr al, cl": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 15,
"Comment": "GROUP2 0xd2 /5",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"uxtb w21, w5",
"lsr w22, w20, w21",
"bfxil x4, x22, #0, #8",
"cbz x21, #+0x30",
"cbz w21, #+0x2c",
"cmn wzr, w22, lsl #24",
"sub x21, x21, #0x1 (1)",
"lsr w21, w20, w21",
"ubfx x21, x21, #0, #1",
"mrs x23, nzcv",
"orr w21, w23, w21, lsl #29",
"mov x26, x22",
"eor w20, w20, w22",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
"sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"lsr w2, w2, #7",
"bfi w1, w2, #28, #1",
"msr nzcv, x1"
]
},
"sar al, cl": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 13,
"Comment": "GROUP2 0xd2 /7",
"ExpectedArm64ASM": [
"uxtb w20, w4",
@ -2077,15 +2075,14 @@
"sxtb x20, w20",
"asr w22, w20, w21",
"bfxil x4, x22, #0, #8",
"cbz x21, #+0x24",
"cbz w21, #+0x20",
"cmn wzr, w22, lsl #24",
"sub x21, x21, #0x1 (1)",
"lsr x20, x20, x21",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"mov x26, x22",
"msr nzcv, x20"
"sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"msr nzcv, x1"
]
},
"rol ax, cl": {
@ -2378,142 +2375,124 @@
]
},
"shl ax, cl": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 16,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w5",
"lsl w22, w20, w21",
"bfxil x4, x22, #0, #16",
"cbz x21, #+0x34",
"cbz w21, #+0x30",
"cmn wzr, w22, lsl #16",
"mov w23, #0x10",
"sub w21, w23, w21",
"lsr w21, w20, w21",
"ubfx x21, x21, #0, #1",
"mrs x23, nzcv",
"orr w21, w23, w21, lsl #29",
"mov x26, x22",
"eor w20, w20, w22",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
"mov w0, #0x10",
"sub w0, w0, w21",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"lsr w2, w2, #15",
"bfi w1, w2, #28, #1",
"msr nzcv, x1"
]
},
"shl eax, cl": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 13,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"lsl w22, w20, w21",
"mov x4, x22",
"cbz x21, #+0x34",
"tst w22, w22",
"mov w23, #0x20",
"sub w21, w23, w21",
"lsr w21, w20, w21",
"ubfx x21, x21, #0, #1",
"mrs x23, nzcv",
"orr w21, w23, w21, lsl #29",
"mov x26, x22",
"eor w20, w20, w22",
"ubfx x20, x20, #31, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
"lsl w4, w20, w21",
"cbz w21, #+0x28",
"ands w26, w4, w4",
"neg w0, w21",
"lsr w0, w20, w0",
"eor w2, w20, w4",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"lsr w2, w2, #31",
"bfi w1, w2, #28, #1",
"msr nzcv, x1"
]
},
"shl rax, cl": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 12,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x21, x5",
"lsl x22, x20, x21",
"mov x4, x22",
"cbz x21, #+0x34",
"tst x22, x22",
"mov w23, #0x40",
"sub x21, x23, x21",
"lsr x21, x20, x21",
"ubfx x21, x21, #0, #1",
"mrs x23, nzcv",
"orr w21, w23, w21, lsl #29",
"mov x26, x22",
"eor x20, x20, x22",
"lsr x20, x20, #63",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
"lsl x4, x20, x5",
"cbz x5, #+0x28",
"ands x26, x4, x4",
"neg x0, x5",
"lsr x0, x20, x0",
"eor x2, x20, x4",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"lsr x2, x2, #63",
"bfi w1, w2, #28, #1",
"msr nzcv, x1"
]
},
"shr ax, cl": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 15,
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w5",
"lsr w22, w20, w21",
"bfxil x4, x22, #0, #16",
"cbz x21, #+0x30",
"cbz w21, #+0x2c",
"cmn wzr, w22, lsl #16",
"sub x21, x21, #0x1 (1)",
"lsr w21, w20, w21",
"ubfx x21, x21, #0, #1",
"mrs x23, nzcv",
"orr w21, w23, w21, lsl #29",
"mov x26, x22",
"eor w20, w20, w22",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
"sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"lsr w2, w2, #15",
"bfi w1, w2, #28, #1",
"msr nzcv, x1"
]
},
"shr eax, cl": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 13,
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"lsr w22, w20, w21",
"mov x4, x22",
"cbz x21, #+0x30",
"tst w22, w22",
"sub x21, x21, #0x1 (1)",
"lsr w21, w20, w21",
"ubfx x21, x21, #0, #1",
"mrs x23, nzcv",
"orr w21, w23, w21, lsl #29",
"mov x26, x22",
"eor w20, w20, w22",
"ubfx x20, x20, #31, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
"lsr w4, w20, w21",
"cbz w21, #+0x28",
"ands w26, w4, w4",
"sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0",
"eor w2, w20, w4",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"lsr w2, w2, #31",
"bfi w1, w2, #28, #1",
"msr nzcv, x1"
]
},
"shr rax, cl": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 12,
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x21, x5",
"lsr x22, x20, x21",
"mov x4, x22",
"cbz x21, #+0x30",
"tst x22, x22",
"sub x21, x21, #0x1 (1)",
"lsr x21, x20, x21",
"ubfx x21, x21, #0, #1",
"mrs x23, nzcv",
"orr w21, w23, w21, lsl #29",
"mov x26, x22",
"eor x20, x20, x22",
"lsr x20, x20, #63",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
"lsr x4, x20, x5",
"cbz x5, #+0x28",
"ands x26, x4, x4",
"sub x0, x5, #0x1 (1)",
"lsr x0, x20, x0",
"eor x2, x20, x4",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"lsr x2, x2, #63",
"bfi w1, w2, #28, #1",
"msr nzcv, x1"
]
},
"sar ax, cl": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 13,
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"uxth w20, w4",
@ -2521,53 +2500,45 @@
"sxth x20, w20",
"asr w22, w20, w21",
"bfxil x4, x22, #0, #16",
"cbz x21, #+0x24",
"cbz w21, #+0x20",
"cmn wzr, w22, lsl #16",
"sub x21, x21, #0x1 (1)",
"lsr x20, x20, x21",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"mov x26, x22",
"msr nzcv, x20"
"sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"msr nzcv, x1"
]
},
"sar eax, cl": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"asr w22, w20, w21",
"mov x4, x22",
"cbz x21, #+0x24",
"tst w22, w22",
"sub x21, x21, #0x1 (1)",
"lsr w20, w20, w21",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"mov x26, x22",
"msr nzcv, x20"
"asr w4, w20, w21",
"cbz w21, #+0x1c",
"ands w26, w4, w4",
"sub x0, x21, #0x1 (1)",
"lsr w0, w20, w0",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"msr nzcv, x1"
]
},
"sar rax, cl": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x21, x5",
"asr x22, x20, x21",
"mov x4, x22",
"cbz x21, #+0x24",
"tst x22, x22",
"sub x21, x21, #0x1 (1)",
"lsr x20, x20, x21",
"ubfx x20, x20, #0, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"mov x26, x22",
"msr nzcv, x20"
"asr x4, x20, x5",
"cbz x5, #+0x1c",
"ands x26, x4, x4",
"sub x0, x5, #0x1 (1)",
"lsr x0, x20, x0",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"msr nzcv, x1"
]
},
"test bl, 1": {

76
unittests/InstructionCountCI/Secondary.json
View File

@ -1588,7 +1588,7 @@
]
},
"shld ax, bx, cl": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 25,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"uxth w20, w7",
@ -1604,23 +1604,22 @@
"csel x20, x21, x20, eq",
"bfxil x4, x20, #0, #16",
"msr nzcv, x23",
"cbz x22, #+0x34",
"cbz w22, #+0x30",
"cmn wzr, w20, lsl #16",
"mov w23, #0x10",
"sub w22, w23, w22",
"lsr w22, w21, w22",
"ubfx x22, x22, #0, #1",
"mrs x23, nzcv",
"orr w22, w23, w22, lsl #29",
"mov x26, x20",
"eor w20, w21, w20",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
"mov w0, #0x10",
"sub w0, w0, w22",
"lsr w0, w21, w0",
"eor w2, w21, w20",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"lsr w2, w2, #15",
"bfi w1, w2, #28, #1",
"msr nzcv, x1"
]
},
"shld eax, ebx, cl": {
"ExpectedInstructionCount": 25,
"ExpectedInstructionCount": 22,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov w20, w7",
@ -1635,23 +1634,20 @@
"csel x20, x21, x20, eq",
"mov w4, w20",
"msr nzcv, x23",
"cbz x22, #+0x34",
"tst w20, w20",
"mov w23, #0x20",
"sub w22, w23, w22",
"lsr w22, w21, w22",
"ubfx x22, x22, #0, #1",
"mrs x23, nzcv",
"orr w22, w23, w22, lsl #29",
"mov x26, x20",
"eor w20, w21, w20",
"ubfx x20, x20, #31, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
"cbz w22, #+0x28",
"ands w26, w20, w20",
"neg w0, w22",
"lsr w0, w21, w0",
"eor w2, w21, w20",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"lsr w2, w2, #31",
"bfi w1, w2, #28, #1",
"msr nzcv, x1"
]
},
"shld rax, rbx, cl": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 20,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov x20, x4",
@ -1662,22 +1658,18 @@
"orr x22, x23, x22",
"mrs x23, nzcv",
"cmp x21, #0x0 (0)",
"csel x22, x20, x22, eq",
"mov x4, x22",
"csel x4, x20, x22, eq",
"msr nzcv, x23",
"cbz x21, #+0x34",
"tst x22, x22",
"mov w23, #0x40",
"sub x21, x23, x21",
"lsr x21, x20, x21",
"ubfx x21, x21, #0, #1",
"mrs x23, nzcv",
"orr w21, w23, w21, lsl #29",
"mov x26, x22",
"eor x20, x20, x22",
"lsr x20, x20, #63",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
"cbz x21, #+0x28",
"ands x26, x4, x4",
"neg x0, x21",
"lsr x0, x20, x0",
"eor x2, x20, x4",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"lsr x2, x2, #63",
"bfi w1, w2, #28, #1",
"msr nzcv, x1"
]
},
"push gs": {