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InstCountCI: Update

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig 2024-02-26 16:48:15 -04:00
parent 12cc980603
commit b6bd826014
8 changed files with 1194 additions and 1466 deletions
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415
unittests/InstructionCountCI/Atomics.json
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@ -69,24 +69,23 @@
]
},
"lock adc byte [rax], cl": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 21,
"Comment": "0x10",
"ExpectedArm64ASM": [
"adc w20, wzr, w5",
"ldaddalb w20, w20, [x4]",
"eor w27, w20, w5",
"cset w21, hs",
"add w22, w20, w5",
"add w22, w22, w21",
"adc w22, w20, w5",
"uxtb w26, w22",
"cmp x26, x5",
"cset x22, lo",
"cmp x26, x5",
"cset x23, ls",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"cmp x26, x5",
"cset x23, lo",
"cmp x26, x5",
"cset x24, ls",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, w5",
"eor w20, w26, w20",
@ -97,24 +96,23 @@
]
},
"lock adc word [rax], cx": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 21,
"Comment": "0x11",
"ExpectedArm64ASM": [
"adc w20, wzr, w5",
"ldaddalh w20, w20, [x4]",
"eor w27, w20, w5",
"cset w21, hs",
"add w22, w20, w5",
"add w22, w22, w21",
"adc w22, w20, w5",
"uxth w26, w22",
"cmp x26, x5",
"cset x22, lo",
"cmp x26, x5",
"cset x23, ls",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"cmp x26, x5",
"cset x23, lo",
"cmp x26, x5",
"cset x24, ls",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, w5",
"eor w20, w26, w20",
@ -138,26 +136,26 @@
"ExpectedInstructionCount": 23,
"Comment": "0x18",
"ExpectedArm64ASM": [
"uxtb w20, w5",
"adc w20, wzr, w5",
"neg w1, w20",
"ldaddalb w1, w20, [x4]",
"eor w27, w20, w5",
"cset w21, hs",
"add w22, w20, w21",
"neg w1, w22",
"ldaddalb w1, w23, [x4]",
"sub w22, w23, w22",
"add w22, w5, w21",
"sub w22, w20, w22",
"uxtb w26, w22",
"eor w27, w23, w20",
"cmp w26, w20",
"cset x22, hi",
"cmp w26, w20",
"cset x23, hs",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"cmp w26, w23",
"cset x24, hi",
"cmp w26, w23",
"cset x25, hs",
"cmp x21, #0x1 (1)",
"csel x21, x25, x24, eq",
"orr w21, w22, w21, lsl #29",
"eor w20, w23, w20",
"eor w22, w26, w23",
"and w20, w22, w20",
"eor w22, w20, w5",
"eor w20, w26, w20",
"and w20, w20, w22",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
@ -167,46 +165,43 @@
"ExpectedInstructionCount": 23,
"Comment": "0x19",
"ExpectedArm64ASM": [
"uxth w20, w5",
"adc w20, wzr, w5",
"neg w1, w20",
"ldaddalh w1, w20, [x4]",
"eor w27, w20, w5",
"cset w21, hs",
"add w22, w20, w21",
"neg w1, w22",
"ldaddalh w1, w23, [x4]",
"sub w22, w23, w22",
"add w22, w5, w21",
"sub w22, w20, w22",
"uxth w26, w22",
"eor w27, w23, w20",
"cmp w26, w20",
"cset x22, hi",
"cmp w26, w20",
"cset x23, hs",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"cmp w26, w23",
"cset x24, hi",
"cmp w26, w23",
"cset x25, hs",
"cmp x21, #0x1 (1)",
"csel x21, x25, x24, eq",
"orr w21, w22, w21, lsl #29",
"eor w20, w23, w20",
"eor w22, w26, w23",
"and w20, w22, w20",
"eor w22, w20, w5",
"eor w20, w26, w20",
"and w20, w20, w22",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb dword [rax], ecx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 11,
"Comment": "0x19",
"ExpectedArm64ASM": [
"mov w20, w5",
"cset w21, hs",
"add w21, w20, w21",
"neg w1, w21",
"ldaddal w1, w22, [x4]",
"sub w26, w22, w21",
"eor w27, w22, w20",
"adc w20, wzr, w5",
"neg w1, w20",
"ldaddal w1, w20, [x4]",
"eor w27, w20, w5",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs wzr, w22, w20",
"sbcs w26, w20, w5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
@ -623,24 +618,23 @@
]
},
"lock adc byte [rax], 1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 19,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adc w20, wzr, w20",
"ldaddalb w20, w27, [x4]",
"cset w20, hs",
"add w21, w27, #0x1 (1)",
"add w21, w21, w20",
"uxtb w26, w21",
"adc w21, wzr, w20",
"ldaddalb w21, w27, [x4]",
"cset w21, hs",
"adc w20, w27, w20",
"uxtb w26, w20",
"cmp w26, #0x1 (1)",
"cset x20, lo",
"cmp w26, #0x1 (1)",
"cset x22, ls",
"cmp x21, #0x1 (1)",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"cmp w26, #0x1 (1)",
"cset x22, lo",
"cmp w26, #0x1 (1)",
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
"orr w20, w21, w20, lsl #29",
"bic w21, w26, w27",
"ubfx x21, x21, #7, #1",
@ -649,51 +643,49 @@
]
},
"lock adc byte [rax], 0xFF": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 20,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"adc w20, wzr, w20",
"ldaddalb w20, w20, [x4]",
"eor w27, w20, #0xff",
"cset w21, hs",
"add w22, w20, #0xff (255)",
"add w22, w22, w21",
"uxtb w26, w22",
"adc w21, wzr, w20",
"ldaddalb w21, w21, [x4]",
"eor w27, w21, #0xff",
"cset w22, hs",
"adc w20, w21, w20",
"uxtb w26, w20",
"cmp w26, #0xff (255)",
"cset x20, lo",
"cmp w26, #0xff (255)",
"cset x23, ls",
"cmp x22, #0x1 (1)",
"csel x20, x23, x20, eq",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"cmp w26, #0xff (255)",
"cset x23, lo",
"cmp w26, #0xff (255)",
"cset x24, ls",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w21, w22, w21, lsl #29",
"bic w20, w20, w26",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"orr w20, w22, w20, lsl #29",
"bic w21, w21, w26",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock adc word [rax], 0x100": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 19,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"adc w20, wzr, w20",
"ldaddalh w20, w27, [x4]",
"cset w20, hs",
"add w21, w27, #0x100 (256)",
"add w21, w21, w20",
"uxth w26, w21",
"adc w21, wzr, w20",
"ldaddalh w21, w27, [x4]",
"cset w21, hs",
"adc w20, w27, w20",
"uxth w26, w20",
"cmp w26, #0x100 (256)",
"cset x20, lo",
"cmp w26, #0x100 (256)",
"cset x22, ls",
"cmp x21, #0x1 (1)",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"cmp w26, #0x100 (256)",
"cset x22, lo",
"cmp w26, #0x100 (256)",
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
"orr w20, w21, w20, lsl #29",
"bic w21, w26, w27",
"ubfx x21, x21, #15, #1",
@ -702,7 +694,7 @@
]
},
"lock adc word [rax], 0xFFFF": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 20,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
@ -710,18 +702,17 @@
"ldaddalh w21, w21, [x4]",
"eor w27, w21, #0xffff",
"cset w22, hs",
"add w23, w21, w20",
"add w23, w23, w22",
"adc w23, w21, w20",
"uxth w26, w23",
"cmn wzr, w26, lsl #16",
"mrs x23, nzcv",
"cmp w26, w20",
"cset x24, lo",
"cset x23, lo",
"cmp w26, w20",
"cset x20, ls",
"cmp x22, #0x1 (1)",
"csel x20, x20, x24, eq",
"orr w20, w23, w20, lsl #29",
"csel x20, x20, x23, eq",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"orr w20, w22, w20, lsl #29",
"bic w21, w21, w26",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
@ -770,24 +761,23 @@
]
},
"lock adc word [rax], 1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 19,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adc w20, wzr, w20",
"ldaddalh w20, w27, [x4]",
"cset w20, hs",
"add w21, w27, #0x1 (1)",
"add w21, w21, w20",
"uxth w26, w21",
"adc w21, wzr, w20",
"ldaddalh w21, w27, [x4]",
"cset w21, hs",
"adc w20, w27, w20",
"uxth w26, w20",
"cmp w26, #0x1 (1)",
"cset x20, lo",
"cmp w26, #0x1 (1)",
"cset x22, ls",
"cmp x21, #0x1 (1)",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"cmp w26, #0x1 (1)",
"cset x22, lo",
"cmp w26, #0x1 (1)",
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
"orr w20, w21, w20, lsl #29",
"bic w21, w26, w27",
"ubfx x21, x21, #15, #1",
@ -816,25 +806,26 @@
]
},
"lock sbb byte [rax], 1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 21,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddalb w1, w27, [x4]",
"cset w21, hs",
"add w20, w20, w21",
"neg w1, w20",
"ldaddalb w1, w27, [x4]",
"sub w20, w27, w20",
"uxtb w26, w20",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"cmp w26, w27",
"cset x22, hi",
"cset x20, hi",
"cmp w26, w27",
"cset x23, hs",
"cset x22, hs",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"orr w20, w20, w21, lsl #29",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"bic w21, w27, w26",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
@ -842,52 +833,54 @@
]
},
"lock sbb byte [rax], 0xFF": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 22,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"cset w21, hs",
"add w20, w20, w21",
"neg w1, w20",
"ldaddalb w1, w22, [x4]",
"sub w20, w22, w20",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddalb w1, w21, [x4]",
"eor w27, w21, #0xff",
"cset w22, hs",
"add w20, w20, w22",
"sub w20, w21, w20",
"uxtb w26, w20",
"eor w27, w22, #0xff",
"cmp w26, w21",
"cset x20, hi",
"cmp w26, w21",
"cset x23, hs",
"cmp x22, #0x1 (1)",
"csel x20, x23, x20, eq",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"cmp w26, w22",
"cset x23, hi",
"cmp w26, w22",
"cset x24, hs",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w26, w22",
"mrs x22, nzcv",
"orr w20, w22, w20, lsl #29",
"bic w21, w26, w21",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb word [rax], 0x100": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 21,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddalh w1, w27, [x4]",
"cset w21, hs",
"add w20, w20, w21",
"neg w1, w20",
"ldaddalh w1, w27, [x4]",
"sub w20, w27, w20",
"uxth w26, w20",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"cmp w26, w27",
"cset x22, hi",
"cset x20, hi",
"cmp w26, w27",
"cset x23, hs",
"cset x22, hs",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"orr w20, w20, w21, lsl #29",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"bic w21, w27, w26",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
@ -895,129 +888,123 @@
]
},
"lock sbb word [rax], 0xFFFF": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 22,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"cset w21, hs",
"add w20, w20, w21",
"neg w1, w20",
"ldaddalh w1, w22, [x4]",
"sub w20, w22, w20",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddalh w1, w21, [x4]",
"eor w27, w21, #0xffff",
"cset w22, hs",
"add w20, w20, w22",
"sub w20, w21, w20",
"uxth w26, w20",
"eor w27, w22, #0xffff",
"cmp w26, w21",
"cset x20, hi",
"cmp w26, w21",
"cset x23, hs",
"cmp x22, #0x1 (1)",
"csel x20, x23, x20, eq",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"cmp w26, w22",
"cset x23, hi",
"cmp w26, w22",
"cset x24, hs",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w26, w22",
"mrs x22, nzcv",
"orr w20, w22, w20, lsl #29",
"bic w21, w26, w21",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb dword [rax], 0x100": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cset w21, hs",
"add w21, w20, w21",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddal w1, w27, [x4]",
"sub w26, w27, w21",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs wzr, w27, w20",
"sbcs w26, w27, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sbb dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"cset w21, hs",
"add w21, w20, w21",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddal w1, w22, [x4]",
"sub w26, w22, w21",
"eor w27, w22, w20",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs wzr, w22, w20",
"ldaddal w1, w21, [x4]",
"eor w27, w21, w20",
"mrs x22, nzcv",
"eor w22, w22, #0x20000000",
"msr nzcv, x22",
"sbcs w26, w21, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sbb qword [rax], 0x100": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cset w21, hs",
"add x21, x20, x21",
"adc x21, xzr, x20",
"neg x1, x21",
"ldaddal x1, x27, [x4]",
"sub x26, x27, x21",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs xzr, x27, x20",
"sbcs x26, x27, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sbb qword [rax], -2147483647": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"cset w21, hs",
"add x21, x20, x21",
"adc x21, xzr, x20",
"neg x1, x21",
"ldaddal x1, x27, [x4]",
"sub x26, x27, x21",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs xzr, x27, x20",
"sbcs x26, x27, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sbb word [rax], 1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 21,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddalh w1, w27, [x4]",
"cset w21, hs",
"add w20, w20, w21",
"neg w1, w20",
"ldaddalh w1, w27, [x4]",
"sub w20, w27, w20",
"uxth w26, w20",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"cmp w26, w27",
"cset x22, hi",
"cset x20, hi",
"cmp w26, w27",
"cset x23, hs",
"cset x22, hs",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"orr w20, w20, w21, lsl #29",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"bic w21, w27, w26",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
@ -1025,38 +1012,34 @@
]
},
"lock sbb dword [rax], 1": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add w21, w20, w21",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddal w1, w27, [x4]",
"sub w26, w27, w21",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs wzr, w27, w20",
"sbcs w26, w27, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sbb qword [rax], 1": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add x21, x20, x21",
"adc x21, xzr, x20",
"neg x1, x21",
"ldaddal x1, x27, [x4]",
"sub x26, x27, x21",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs xzr, x27, x20",
"sbcs x26, x27, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"

471
unittests/InstructionCountCI/FlagM/Atomics.json
View File

@ -70,56 +70,50 @@
]
},
"lock adc byte [rax], cl": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 18,
"Comment": "0x10",
"ExpectedArm64ASM": [
"adc w20, wzr, w5",
"ldaddalb w20, w20, [x4]",
"eor w27, w20, w5",
"cset w21, hs",
"add w22, w20, w5",
"add w22, w22, w21",
"adc w22, w20, w5",
"uxtb w26, w22",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"cmp x26, x5",
"cset x23, lo",
"cset x22, lo",
"cmp x26, x5",
"cset x24, ls",
"cset x23, ls",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, w5",
"csel x21, x23, x22, eq",
"cmn wzr, w26, lsl #24",
"rmif x21, #63, #nzCv",
"eor w21, w20, w5",
"eor w20, w26, w20",
"bic w20, w20, w22",
"msr nzcv, x21",
"bic w20, w20, w21",
"rmif x20, #7, #nzcV"
]
},
"lock adc word [rax], cx": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 18,
"Comment": "0x11",
"ExpectedArm64ASM": [
"adc w20, wzr, w5",
"ldaddalh w20, w20, [x4]",
"eor w27, w20, w5",
"cset w21, hs",
"add w22, w20, w5",
"add w22, w22, w21",
"adc w22, w20, w5",
"uxth w26, w22",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"cmp x26, x5",
"cset x23, lo",
"cset x22, lo",
"cmp x26, x5",
"cset x24, ls",
"cset x23, ls",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, w5",
"csel x21, x23, x22, eq",
"cmn wzr, w26, lsl #16",
"rmif x21, #63, #nzCv",
"eor w21, w20, w5",
"eor w20, w26, w20",
"bic w20, w20, w22",
"msr nzcv, x21",
"bic w20, w20, w21",
"rmif x20, #15, #nzcV"
]
},
@ -134,74 +128,67 @@
]
},
"lock sbb byte [rax], cl": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 20,
"Comment": "0x18",
"ExpectedArm64ASM": [
"uxtb w20, w5",
"adc w20, wzr, w5",
"neg w1, w20",
"ldaddalb w1, w20, [x4]",
"eor w27, w20, w5",
"cset w21, hs",
"add w22, w20, w21",
"neg w1, w22",
"ldaddalb w1, w23, [x4]",
"sub w22, w23, w22",
"add w22, w5, w21",
"sub w22, w20, w22",
"uxtb w26, w22",
"eor w27, w23, w20",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"cmp w26, w23",
"cset x24, hi",
"cmp w26, w23",
"cset x25, hs",
"cmp w26, w20",
"cset x22, hi",
"cmp w26, w20",
"cset x23, hs",
"cmp x21, #0x1 (1)",
"csel x21, x25, x24, eq",
"orr w21, w22, w21, lsl #29",
"eor w20, w23, w20",
"eor w22, w26, w23",
"and w20, w22, w20",
"msr nzcv, x21",
"csel x21, x23, x22, eq",
"cmn wzr, w26, lsl #24",
"rmif x21, #63, #nzCv",
"eor w21, w20, w5",
"eor w20, w26, w20",
"and w20, w20, w21",
"rmif x20, #7, #nzcV"
]
},
"lock sbb word [rax], cx": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 20,
"Comment": "0x19",
"ExpectedArm64ASM": [
"uxth w20, w5",
"adc w20, wzr, w5",
"neg w1, w20",
"ldaddalh w1, w20, [x4]",
"eor w27, w20, w5",
"cset w21, hs",
"add w22, w20, w21",
"neg w1, w22",
"ldaddalh w1, w23, [x4]",
"sub w22, w23, w22",
"add w22, w5, w21",
"sub w22, w20, w22",
"uxth w26, w22",
"eor w27, w23, w20",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"cmp w26, w23",
"cset x24, hi",
"cmp w26, w23",
"cset x25, hs",
"cmp w26, w20",
"cset x22, hi",
"cmp w26, w20",
"cset x23, hs",
"cmp x21, #0x1 (1)",
"csel x21, x25, x24, eq",
"orr w21, w22, w21, lsl #29",
"eor w20, w23, w20",
"eor w22, w26, w23",
"and w20, w22, w20",
"msr nzcv, x21",
"csel x21, x23, x22, eq",
"cmn wzr, w26, lsl #16",
"rmif x21, #63, #nzCv",
"eor w21, w20, w5",
"eor w20, w26, w20",
"and w20, w20, w21",
"rmif x20, #15, #nzcV"
]
},
"lock sbb dword [rax], ecx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 7,
"Comment": "0x19",
"ExpectedArm64ASM": [
"mov w20, w5",
"cset w21, hs",
"add w21, w20, w21",
"neg w1, w21",
"ldaddal w1, w22, [x4]",
"sub w26, w22, w21",
"eor w27, w22, w20",
"adc w20, wzr, w5",
"neg w1, w20",
"ldaddal w1, w20, [x4]",
"eor w27, w20, w5",
"cfinv",
"sbcs wzr, w22, w20",
"sbcs w26, w20, w5",
"cfinv"
]
},
@ -576,83 +563,74 @@
]
},
"lock adc byte [rax], 1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 16,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adc w20, wzr, w20",
"ldaddalb w20, w27, [x4]",
"cset w20, hs",
"add w21, w27, #0x1 (1)",
"add w21, w21, w20",
"uxtb w26, w21",
"adc w21, wzr, w20",
"ldaddalb w21, w27, [x4]",
"cset w21, hs",
"adc w20, w27, w20",
"uxtb w26, w20",
"cmp w26, #0x1 (1)",
"cset x20, lo",
"cmp w26, #0x1 (1)",
"cset x22, ls",
"cmp x21, #0x1 (1)",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"cmp w26, #0x1 (1)",
"cset x22, lo",
"cmp w26, #0x1 (1)",
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
"orr w20, w21, w20, lsl #29",
"bic w21, w26, w27",
"msr nzcv, x20",
"rmif x21, #7, #nzcV"
"rmif x20, #63, #nzCv",
"bic w20, w26, w27",
"rmif x20, #7, #nzcV"
]
},
"lock adc byte [rax], 0xFF": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 17,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"adc w20, wzr, w20",
"ldaddalb w20, w20, [x4]",
"eor w27, w20, #0xff",
"cset w21, hs",
"add w22, w20, #0xff (255)",
"add w22, w22, w21",
"uxtb w26, w22",
"adc w21, wzr, w20",
"ldaddalb w21, w21, [x4]",
"eor w27, w21, #0xff",
"cset w22, hs",
"adc w20, w21, w20",
"uxtb w26, w20",
"cmp w26, #0xff (255)",
"cset x20, lo",
"cmp w26, #0xff (255)",
"cset x23, ls",
"cmp x22, #0x1 (1)",
"csel x20, x23, x20, eq",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"cmp w26, #0xff (255)",
"cset x23, lo",
"cmp w26, #0xff (255)",
"cset x24, ls",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w21, w22, w21, lsl #29",
"bic w20, w20, w26",
"msr nzcv, x21",
"rmif x20, #63, #nzCv",
"bic w20, w21, w26",
"rmif x20, #7, #nzcV"
]
},
"lock adc word [rax], 0x100": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 16,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"adc w20, wzr, w20",
"ldaddalh w20, w27, [x4]",
"cset w20, hs",
"add w21, w27, #0x100 (256)",
"add w21, w21, w20",
"uxth w26, w21",
"adc w21, wzr, w20",
"ldaddalh w21, w27, [x4]",
"cset w21, hs",
"adc w20, w27, w20",
"uxth w26, w20",
"cmp w26, #0x100 (256)",
"cset x20, lo",
"cmp w26, #0x100 (256)",
"cset x22, ls",
"cmp x21, #0x1 (1)",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"cmp w26, #0x100 (256)",
"cset x22, lo",
"cmp w26, #0x100 (256)",
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
"orr w20, w21, w20, lsl #29",
"bic w21, w26, w27",
"msr nzcv, x20",
"rmif x21, #15, #nzcV"
"rmif x20, #63, #nzCv",
"bic w20, w26, w27",
"rmif x20, #15, #nzcV"
]
},
"lock adc word [rax], 0xFFFF": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 17,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
@ -660,21 +638,18 @@
"ldaddalh w21, w21, [x4]",
"eor w27, w21, #0xffff",
"cset w22, hs",
"add w23, w21, w20",
"add w23, w23, w22",
"adc w23, w21, w20",
"uxth w26, w23",
"cmn wzr, w26, lsl #16",
"mrs x23, nzcv",
"cmp w26, w20",
"cset x24, lo",
"cset x23, lo",
"cmp w26, w20",
"cset x20, ls",
"cmp x22, #0x1 (1)",
"csel x20, x20, x24, eq",
"orr w20, w23, w20, lsl #29",
"bic w21, w21, w26",
"msr nzcv, x20",
"rmif x21, #15, #nzcV"
"csel x20, x20, x23, eq",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"bic w20, w21, w26",
"rmif x20, #15, #nzcV"
]
},
"lock adc dword [rax], 0x100": {
@ -719,28 +694,25 @@
]
},
"lock adc word [rax], 1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 16,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adc w20, wzr, w20",
"ldaddalh w20, w27, [x4]",
"cset w20, hs",
"add w21, w27, #0x1 (1)",
"add w21, w21, w20",
"uxth w26, w21",
"adc w21, wzr, w20",
"ldaddalh w21, w27, [x4]",
"cset w21, hs",
"adc w20, w27, w20",
"uxth w26, w20",
"cmp w26, #0x1 (1)",
"cset x20, lo",
"cmp w26, #0x1 (1)",
"cset x22, ls",
"cmp x21, #0x1 (1)",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"cmp w26, #0x1 (1)",
"cset x22, lo",
"cmp w26, #0x1 (1)",
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
"orr w20, w21, w20, lsl #29",
"bic w21, w26, w27",
"msr nzcv, x20",
"rmif x21, #15, #nzcV"
"rmif x20, #63, #nzCv",
"bic w20, w26, w27",
"rmif x20, #15, #nzcV"
]
},
"lock adc dword [rax], 1": {
@ -764,220 +736,203 @@
]
},
"lock sbb byte [rax], 1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddalb w1, w27, [x4]",
"cset w21, hs",
"add w20, w20, w21",
"neg w1, w20",
"ldaddalb w1, w27, [x4]",
"sub w20, w27, w20",
"uxtb w26, w20",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"cmp w26, w27",
"cset x22, hi",
"cset x20, hi",
"cmp w26, w27",
"cset x23, hs",
"cset x22, hs",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w27, w26",
"msr nzcv, x20",
"rmif x21, #7, #nzcV"
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"bic w20, w27, w26",
"rmif x20, #7, #nzcV"
]
},
"lock sbb byte [rax], 0xFF": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 19,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"cset w21, hs",
"add w20, w20, w21",
"neg w1, w20",
"ldaddalb w1, w22, [x4]",
"sub w20, w22, w20",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddalb w1, w21, [x4]",
"eor w27, w21, #0xff",
"cset w22, hs",
"add w20, w20, w22",
"sub w20, w21, w20",
"uxtb w26, w20",
"eor w27, w22, #0xff",
"cmp w26, w21",
"cset x20, hi",
"cmp w26, w21",
"cset x23, hs",
"cmp x22, #0x1 (1)",
"csel x20, x23, x20, eq",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"cmp w26, w22",
"cset x23, hi",
"cmp w26, w22",
"cset x24, hs",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w26, w22",
"msr nzcv, x20",
"rmif x21, #7, #nzcV"
"rmif x20, #63, #nzCv",
"bic w20, w26, w21",
"rmif x20, #7, #nzcV"
]
},
"lock sbb word [rax], 0x100": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddalh w1, w27, [x4]",
"cset w21, hs",
"add w20, w20, w21",
"neg w1, w20",
"ldaddalh w1, w27, [x4]",
"sub w20, w27, w20",
"uxth w26, w20",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"cmp w26, w27",
"cset x22, hi",
"cset x20, hi",
"cmp w26, w27",
"cset x23, hs",
"cset x22, hs",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w27, w26",
"msr nzcv, x20",
"rmif x21, #15, #nzcV"
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"bic w20, w27, w26",
"rmif x20, #15, #nzcV"
]
},
"lock sbb word [rax], 0xFFFF": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 19,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"cset w21, hs",
"add w20, w20, w21",
"neg w1, w20",
"ldaddalh w1, w22, [x4]",
"sub w20, w22, w20",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddalh w1, w21, [x4]",
"eor w27, w21, #0xffff",
"cset w22, hs",
"add w20, w20, w22",
"sub w20, w21, w20",
"uxth w26, w20",
"eor w27, w22, #0xffff",
"cmp w26, w21",
"cset x20, hi",
"cmp w26, w21",
"cset x23, hs",
"cmp x22, #0x1 (1)",
"csel x20, x23, x20, eq",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"cmp w26, w22",
"cset x23, hi",
"cmp w26, w22",
"cset x24, hs",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w26, w22",
"msr nzcv, x20",
"rmif x21, #15, #nzcV"
"rmif x20, #63, #nzCv",
"bic w20, w26, w21",
"rmif x20, #15, #nzcV"
]
},
"lock sbb dword [rax], 0x100": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cset w21, hs",
"add w21, w20, w21",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddal w1, w27, [x4]",
"sub w26, w27, w21",
"cfinv",
"sbcs wzr, w27, w20",
"sbcs w26, w27, w20",
"cfinv"
]
},
"lock sbb dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 8,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"cset w21, hs",
"add w21, w20, w21",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddal w1, w22, [x4]",
"sub w26, w22, w21",
"eor w27, w22, w20",
"ldaddal w1, w21, [x4]",
"eor w27, w21, w20",
"cfinv",
"sbcs wzr, w22, w20",
"sbcs w26, w21, w20",
"cfinv"
]
},
"lock sbb qword [rax], 0x100": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cset w21, hs",
"add x21, x20, x21",
"adc x21, xzr, x20",
"neg x1, x21",
"ldaddal x1, x27, [x4]",
"sub x26, x27, x21",
"cfinv",
"sbcs xzr, x27, x20",
"sbcs x26, x27, x20",
"cfinv"
]
},
"lock sbb qword [rax], -2147483647": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"cset w21, hs",
"add x21, x20, x21",
"adc x21, xzr, x20",
"neg x1, x21",
"ldaddal x1, x27, [x4]",
"sub x26, x27, x21",
"cfinv",
"sbcs xzr, x27, x20",
"sbcs x26, x27, x20",
"cfinv"
]
},
"lock sbb word [rax], 1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddalh w1, w27, [x4]",
"cset w21, hs",
"add w20, w20, w21",
"neg w1, w20",
"ldaddalh w1, w27, [x4]",
"sub w20, w27, w20",
"uxth w26, w20",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"cmp w26, w27",
"cset x22, hi",
"cset x20, hi",
"cmp w26, w27",
"cset x23, hs",
"cset x22, hs",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w27, w26",
"msr nzcv, x20",
"rmif x21, #15, #nzcV"
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"bic w20, w27, w26",
"rmif x20, #15, #nzcV"
]
},
"lock sbb dword [rax], 1": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add w21, w20, w21",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddal w1, w27, [x4]",
"sub w26, w27, w21",
"cfinv",
"sbcs wzr, w27, w20",
"sbcs w26, w27, w20",
"cfinv"
]
},
"lock sbb qword [rax], 1": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add x21, x20, x21",
"adc x21, xzr, x20",
"neg x1, x21",
"ldaddal x1, x27, [x4]",
"sub x26, x27, x21",
"cfinv",
"sbcs xzr, x27, x20",
"sbcs x26, x27, x20",
"cfinv"
]
},

24
unittests/InstructionCountCI/FlagM/FlagOpts.json
View File

@ -24,7 +24,7 @@
]
},
"Chained sub": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 7,
"x86Insts": [
"sub rax, rbx",
"sbb rcx, rdx"
@ -32,15 +32,11 @@
"ExpectedArm64ASM": [
"subs x4, x4, x7",
"cfinv",
"cset w20, hs",
"add x20, x6, x20",
"mov x21, x5",
"sub x5, x21, x20",
"eor w27, w21, w6",
"mov x26, x5",
"eor w27, w5, w6",
"cfinv",
"sbcs xzr, x21, x6",
"cfinv"
"sbcs x26, x5, x6",
"cfinv",
"mov x5, x26"
]
},
"Inverted add": {
@ -59,7 +55,7 @@
]
},
"Inverted sub": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 8,
"x86Insts": [
"sub rax, rbx",
"sbb rcx, rcx",
@ -68,15 +64,11 @@
"ExpectedArm64ASM": [
"subs x4, x4, x7",
"cfinv",
"mov x20, x5",
"cset w21, hs",
"add x21, x20, x21",
"sub x5, x20, x21",
"mov w27, #0x0",
"mov x26, x5",
"cfinv",
"sbcs xzr, x20, x20",
"sbcs x26, x5, x5",
"cfinv",
"mov x5, x26",
"cfinv"
]
},

660
unittests/InstructionCountCI/FlagM/Primary.json
View File

@ -360,66 +360,57 @@
]
},
"adc bl, cl": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 17,
"Comment": "0x10",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"eor w27, w20, w5",
"cset w21, hs",
"add w22, w20, w5",
"add w22, w22, w21",
"uxtb w26, w22",
"eor w27, w7, w5",
"cset w20, hs",
"adc w21, w7, w5",
"uxtb w26, w21",
"cmp x26, x5",
"cset x21, lo",
"cmp x26, x5",
"cset x22, ls",
"cmp x20, #0x1 (1)",
"csel x20, x22, x21, eq",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"cmp x26, x5",
"cset x23, lo",
"cmp x26, x5",
"cset x24, ls",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, w5",
"eor w20, w26, w20",
"bic w20, w20, w22",
"msr nzcv, x21",
"rmif x20, #63, #nzCv",
"eor w20, w7, w5",
"eor w21, w26, w7",
"bic w20, w21, w20",
"rmif x20, #7, #nzcV",
"bfxil x7, x26, #0, #8"
]
},
"adc bx, cx": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 17,
"Comment": "0x11",
"ExpectedArm64ASM": [
"uxth w20, w7",
"eor w27, w20, w5",
"cset w21, hs",
"add w22, w20, w5",
"add w22, w22, w21",
"uxth w26, w22",
"eor w27, w7, w5",
"cset w20, hs",
"adc w21, w7, w5",
"uxth w26, w21",
"cmp x26, x5",
"cset x21, lo",
"cmp x26, x5",
"cset x22, ls",
"cmp x20, #0x1 (1)",
"csel x20, x22, x21, eq",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"cmp x26, x5",
"cset x23, lo",
"cmp x26, x5",
"cset x24, ls",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, w5",
"eor w20, w26, w20",
"bic w20, w20, w22",
"msr nzcv, x21",
"rmif x20, #63, #nzCv",
"eor w20, w7, w5",
"eor w21, w26, w7",
"bic w20, w21, w20",
"rmif x20, #15, #nzcV",
"bfxil x7, x26, #0, #16"
]
},
"adc ebx, ecx": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": "0x11",
"ExpectedArm64ASM": [
"mov w20, w7",
"eor w27, w20, w5",
"adcs w26, w20, w5",
"eor w27, w7, w5",
"adcs w26, w7, w5",
"mov x7, x26"
]
},
@ -433,75 +424,66 @@
]
},
"db 0x12, 0xcb": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 17,
"Comment": [
"0x12",
"adc bl, cl but modrm.rm as source"
],
"ExpectedArm64ASM": [
"uxtb w20, w5",
"eor w27, w20, w7",
"cset w21, hs",
"add w22, w20, w7",
"add w22, w22, w21",
"uxtb w26, w22",
"eor w27, w5, w7",
"cset w20, hs",
"adc w21, w5, w7",
"uxtb w26, w21",
"cmp x26, x7",
"cset x21, lo",
"cmp x26, x7",
"cset x22, ls",
"cmp x20, #0x1 (1)",
"csel x20, x22, x21, eq",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"cmp x26, x7",
"cset x23, lo",
"cmp x26, x7",
"cset x24, ls",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, w7",
"eor w20, w26, w20",
"bic w20, w20, w22",
"msr nzcv, x21",
"rmif x20, #63, #nzCv",
"eor w20, w5, w7",
"eor w21, w26, w5",
"bic w20, w21, w20",
"rmif x20, #7, #nzcV",
"bfxil x5, x26, #0, #8"
]
},
"db 0x66, 0x13, 0xcb": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 17,
"Comment": [
"0x13",
"adc bx, cx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"uxth w20, w5",
"eor w27, w20, w7",
"cset w21, hs",
"add w22, w20, w7",
"add w22, w22, w21",
"uxth w26, w22",
"eor w27, w5, w7",
"cset w20, hs",
"adc w21, w5, w7",
"uxth w26, w21",
"cmp x26, x7",
"cset x21, lo",
"cmp x26, x7",
"cset x22, ls",
"cmp x20, #0x1 (1)",
"csel x20, x22, x21, eq",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"cmp x26, x7",
"cset x23, lo",
"cmp x26, x7",
"cset x24, ls",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, w7",
"eor w20, w26, w20",
"bic w20, w20, w22",
"msr nzcv, x21",
"rmif x20, #63, #nzCv",
"eor w20, w5, w7",
"eor w21, w26, w5",
"bic w20, w21, w20",
"rmif x20, #15, #nzcV",
"bfxil x5, x26, #0, #16"
]
},
"db 0x13, 0xcb": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"0x13",
"adc ebx, ecx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"mov w20, w5",
"eor w27, w20, w7",
"adcs w26, w20, w7",
"eor w27, w5, w7",
"adcs w26, w5, w7",
"mov x5, x26"
]
},
@ -518,50 +500,48 @@
]
},
"adc al, 1": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 17,
"Comment": "0x14",
"ExpectedArm64ASM": [
"uxtb w27, w4",
"cset w20, hs",
"add w21, w27, #0x1 (1)",
"add w21, w21, w20",
"uxtb w26, w21",
"mov w20, #0x1",
"mov x27, x4",
"cset w21, hs",
"adc w20, w27, w20",
"uxtb w26, w20",
"cmp w26, #0x1 (1)",
"cset x20, lo",
"cmp w26, #0x1 (1)",
"cset x22, ls",
"cmp x21, #0x1 (1)",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"cmp w26, #0x1 (1)",
"cset x22, lo",
"cmp w26, #0x1 (1)",
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
"orr w20, w21, w20, lsl #29",
"bic w21, w26, w27",
"msr nzcv, x20",
"rmif x21, #7, #nzcV",
"rmif x20, #63, #nzCv",
"bic w20, w26, w27",
"rmif x20, #7, #nzcV",
"mov x4, x27",
"bfxil x4, x26, #0, #8"
]
},
"adc ax, 1": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 17,
"Comment": "0x15",
"ExpectedArm64ASM": [
"uxth w27, w4",
"cset w20, hs",
"add w21, w27, #0x1 (1)",
"add w21, w21, w20",
"uxth w26, w21",
"mov w20, #0x1",
"mov x27, x4",
"cset w21, hs",
"adc w20, w27, w20",
"uxth w26, w20",
"cmp w26, #0x1 (1)",
"cset x20, lo",
"cmp w26, #0x1 (1)",
"cset x22, ls",
"cmp x21, #0x1 (1)",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"cmp w26, #0x1 (1)",
"cset x22, lo",
"cmp w26, #0x1 (1)",
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
"orr w20, w21, w20, lsl #29",
"bic w21, w26, w27",
"msr nzcv, x20",
"rmif x21, #15, #nzcV",
"rmif x20, #63, #nzCv",
"bic w20, w26, w27",
"rmif x20, #15, #nzcV",
"mov x4, x27",
"bfxil x4, x26, #0, #16"
]
},
@ -570,7 +550,7 @@
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov w27, w4",
"mov x27, x4",
"adcs w26, w27, w20",
"mov x4, x26"
]
@ -586,64 +566,56 @@
]
},
"adc al, -1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 16,
"Comment": "0x14",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"eor w27, w20, #0xff",
"mov w20, #0xff",
"eor w27, w4, #0xff",
"cset w21, hs",
"add w22, w20, #0xff (255)",
"add w22, w22, w21",
"uxtb w26, w22",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"adc w20, w4, w20",
"uxtb w26, w20",
"cmp w26, #0xff (255)",
"cset x23, lo",
"cset x20, lo",
"cmp w26, #0xff (255)",
"cset x24, ls",
"cset x22, ls",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w21, w22, w21, lsl #29",
"bic w20, w20, w26",
"msr nzcv, x21",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"bic w20, w4, w26",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
},
"adc ax, -1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 16,
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"uxth w21, w4",
"eor w27, w21, #0xffff",
"cset w22, hs",
"add w23, w21, w20",
"add w23, w23, w22",
"uxth w26, w23",
"cmn wzr, w26, lsl #16",
"mrs x23, nzcv",
"eor w27, w4, #0xffff",
"cset w21, hs",
"adc w22, w4, w20",
"uxth w26, w22",
"cmp w26, w20",
"cset x24, lo",
"cset x22, lo",
"cmp w26, w20",
"cset x20, ls",
"cmp x22, #0x1 (1)",
"csel x20, x20, x24, eq",
"orr w20, w23, w20, lsl #29",
"bic w21, w21, w26",
"msr nzcv, x20",
"rmif x21, #15, #nzcV",
"cmp x21, #0x1 (1)",
"csel x20, x20, x22, eq",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"bic w20, w4, w26",
"rmif x20, #15, #nzcV",
"bfxil x4, x26, #0, #16"
]
},
"adc eax, -1": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"mov w21, w4",
"eor w27, w21, w20",
"adcs w26, w21, w20",
"eor w27, w4, w20",
"adcs w26, w4, w20",
"mov x4, x26"
]
},
@ -658,353 +630,297 @@
]
},
"sbb bl, cl": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 18,
"Comment": "0x18",
"ExpectedArm64ASM": [
"uxtb w20, w5",
"cset w21, hs",
"add w22, w20, w21",
"uxtb w23, w7",
"sub w22, w23, w22",
"bfxil x7, x22, #0, #8",
"uxtb w26, w22",
"eor w27, w23, w20",
"eor w27, w7, w5",
"cset w20, hs",
"add w21, w5, w20",
"sub w21, w7, w21",
"uxtb w26, w21",
"cmp x26, x7",
"cset x21, hi",
"cmp x26, x7",
"cset x22, hs",
"cmp x20, #0x1 (1)",
"csel x20, x22, x21, eq",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"cmp w26, w23",
"cset x24, hi",
"cmp w26, w23",
"cset x25, hs",
"cmp x21, #0x1 (1)",
"csel x21, x25, x24, eq",
"orr w21, w22, w21, lsl #29",
"eor w20, w23, w20",
"eor w22, w26, w23",
"and w20, w22, w20",
"msr nzcv, x21",
"rmif x20, #7, #nzcV"
"rmif x20, #63, #nzCv",
"eor w20, w7, w5",
"eor w21, w26, w7",
"and w20, w21, w20",
"rmif x20, #7, #nzcV",
"bfxil x7, x26, #0, #8"
]
},
"sbb bx, cx": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 18,
"Comment": "0x19",
"ExpectedArm64ASM": [
"uxth w20, w5",
"cset w21, hs",
"add w22, w20, w21",
"uxth w23, w7",
"sub w22, w23, w22",
"bfxil x7, x22, #0, #16",
"uxth w26, w22",
"eor w27, w23, w20",
"eor w27, w7, w5",
"cset w20, hs",
"add w21, w5, w20",
"sub w21, w7, w21",
"uxth w26, w21",
"cmp x26, x7",
"cset x21, hi",
"cmp x26, x7",
"cset x22, hs",
"cmp x20, #0x1 (1)",
"csel x20, x22, x21, eq",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"cmp w26, w23",
"cset x24, hi",
"cmp w26, w23",
"cset x25, hs",
"cmp x21, #0x1 (1)",
"csel x21, x25, x24, eq",
"orr w21, w22, w21, lsl #29",
"eor w20, w23, w20",
"eor w22, w26, w23",
"and w20, w22, w20",
"msr nzcv, x21",
"rmif x20, #15, #nzcV"
"rmif x20, #63, #nzCv",
"eor w20, w7, w5",
"eor w21, w26, w7",
"and w20, w21, w20",
"rmif x20, #15, #nzcV",
"bfxil x7, x26, #0, #16"
]
},
"sbb ebx, ecx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 5,
"Comment": "0x19",
"ExpectedArm64ASM": [
"mov w20, w5",
"cset w21, hs",
"add w21, w20, w21",
"mov w22, w7",
"sub w7, w22, w21",
"eor w27, w22, w20",
"mov x26, x7",
"eor w27, w7, w5",
"cfinv",
"sbcs wzr, w22, w20",
"cfinv"
"sbcs w26, w7, w5",
"cfinv",
"mov x7, x26"
]
},
"sbb rbx, rcx": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 5,
"Comment": "0x19",
"ExpectedArm64ASM": [
"cset w20, hs",
"add x20, x5, x20",
"mov x21, x7",
"sub x7, x21, x20",
"eor w27, w21, w5",
"mov x26, x7",
"eor w27, w7, w5",
"cfinv",
"sbcs xzr, x21, x5",
"cfinv"
"sbcs x26, x7, x5",
"cfinv",
"mov x7, x26"
]
},
"db 0x1A, 0xcb": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 18,
"Comment": [
"0x1A",
"sbb bl, cl but modrm.rm as source"
],
"ExpectedArm64ASM": [
"uxtb w20, w7",
"cset w21, hs",
"add w22, w20, w21",
"uxtb w23, w5",
"sub w22, w23, w22",
"bfxil x5, x22, #0, #8",
"uxtb w26, w22",
"eor w27, w23, w20",
"eor w27, w5, w7",
"cset w20, hs",
"add w21, w7, w20",
"sub w21, w5, w21",
"uxtb w26, w21",
"cmp x26, x5",
"cset x21, hi",
"cmp x26, x5",
"cset x22, hs",
"cmp x20, #0x1 (1)",
"csel x20, x22, x21, eq",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"cmp w26, w23",
"cset x24, hi",
"cmp w26, w23",
"cset x25, hs",
"cmp x21, #0x1 (1)",
"csel x21, x25, x24, eq",
"orr w21, w22, w21, lsl #29",
"eor w20, w23, w20",
"eor w22, w26, w23",
"and w20, w22, w20",
"msr nzcv, x21",
"rmif x20, #7, #nzcV"
"rmif x20, #63, #nzCv",
"eor w20, w5, w7",
"eor w21, w26, w5",
"and w20, w21, w20",
"rmif x20, #7, #nzcV",
"bfxil x5, x26, #0, #8"
]
},
"db 0x66, 0x1B, 0xcb": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 18,
"Comment": [
"0x1B",
"sbb bx, cx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"uxth w20, w7",
"cset w21, hs",
"add w22, w20, w21",
"uxth w23, w5",
"sub w22, w23, w22",
"bfxil x5, x22, #0, #16",
"uxth w26, w22",
"eor w27, w23, w20",
"eor w27, w5, w7",
"cset w20, hs",
"add w21, w7, w20",
"sub w21, w5, w21",
"uxth w26, w21",
"cmp x26, x5",
"cset x21, hi",
"cmp x26, x5",
"cset x22, hs",
"cmp x20, #0x1 (1)",
"csel x20, x22, x21, eq",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"cmp w26, w23",
"cset x24, hi",
"cmp w26, w23",
"cset x25, hs",
"cmp x21, #0x1 (1)",
"csel x21, x25, x24, eq",
"orr w21, w22, w21, lsl #29",
"eor w20, w23, w20",
"eor w22, w26, w23",
"and w20, w22, w20",
"msr nzcv, x21",
"rmif x20, #15, #nzcV"
"rmif x20, #63, #nzCv",
"eor w20, w5, w7",
"eor w21, w26, w5",
"and w20, w21, w20",
"rmif x20, #15, #nzcV",
"bfxil x5, x26, #0, #16"
]
},
"db 0x1B, 0xcb": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 5,
"Comment": [
"0x1B",
"sbb ebx, ecx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"mov w20, w7",
"cset w21, hs",
"add w21, w20, w21",
"mov w22, w5",
"sub w5, w22, w21",
"eor w27, w22, w20",
"mov x26, x5",
"eor w27, w5, w7",
"cfinv",
"sbcs wzr, w22, w20",
"cfinv"
"sbcs w26, w5, w7",
"cfinv",
"mov x5, x26"
]
},
"db 0x48, 0x1B, 0xcb": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 5,
"Comment": [
"0x1B",
"sbb rbx, rcx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"cset w20, hs",
"add x20, x7, x20",
"mov x21, x5",
"sub x5, x21, x20",
"eor w27, w21, w7",
"mov x26, x5",
"eor w27, w5, w7",
"cfinv",
"sbcs xzr, x21, x7",
"cfinv"
"sbcs x26, x5, x7",
"cfinv",
"mov x5, x26"
]
},
"sbb al, 1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": "0x1C",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"cset w21, hs",
"add w20, w20, w21",
"uxtb w27, w4",
"sub w20, w27, w20",
"bfxil x4, x20, #0, #8",
"uxtb w26, w20",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"cmp w26, w27",
"cset x22, hi",
"cmp w26, w27",
"cset x23, hs",
"cmp x26, x27",
"cset x20, hi",
"cmp x26, x27",
"cset x22, hs",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w27, w26",
"msr nzcv, x20",
"rmif x21, #7, #nzcV"
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"bic w20, w27, w26",
"rmif x20, #7, #nzcV",
"mov x4, x27",
"bfxil x4, x26, #0, #8"
]
},
"sbb ax, 1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"cset w21, hs",
"add w20, w20, w21",
"uxth w27, w4",
"sub w20, w27, w20",
"bfxil x4, x20, #0, #16",
"uxth w26, w20",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"cmp w26, w27",
"cset x22, hi",
"cmp w26, w27",
"cset x23, hs",
"cmp x26, x27",
"cset x20, hi",
"cmp x26, x27",
"cset x22, hs",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w27, w26",
"msr nzcv, x20",
"rmif x21, #15, #nzcV"
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"bic w20, w27, w26",
"rmif x20, #15, #nzcV",
"mov x4, x27",
"bfxil x4, x26, #0, #16"
]
},
"sbb eax, 1": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add w21, w20, w21",
"mov w27, w4",
"sub w4, w27, w21",
"mov x26, x4",
"mov x27, x4",
"cfinv",
"sbcs wzr, w27, w20",
"cfinv"
"sbcs w26, w27, w20",
"cfinv",
"mov x4, x26"
]
},
"sbb rax, 1": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add x21, x20, x21",
"mov x27, x4",
"sub x4, x27, x21",
"mov x26, x4",
"cfinv",
"sbcs xzr, x27, x20",
"cfinv"
"sbcs x26, x27, x20",
"cfinv",
"mov x4, x26"
]
},
"sbb al, -1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 17,
"Comment": "0x1C",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"eor w27, w4, #0xff",
"cset w21, hs",
"add w20, w20, w21",
"uxtb w22, w4",
"sub w20, w22, w20",
"bfxil x4, x20, #0, #8",
"sub w20, w4, w20",
"uxtb w26, w20",
"eor w27, w22, #0xff",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"cmp w26, w22",
"cset x23, hi",
"cmp w26, w22",
"cset x24, hs",
"cmp x26, x4",
"cset x20, hi",
"cmp x26, x4",
"cset x22, hs",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w26, w22",
"msr nzcv, x20",
"rmif x21, #7, #nzcV"
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"bic w20, w26, w4",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
},
"sbb ax, -1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 17,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"eor w27, w4, #0xffff",
"cset w21, hs",
"add w20, w20, w21",
"uxth w22, w4",
"sub w20, w22, w20",
"bfxil x4, x20, #0, #16",
"sub w20, w4, w20",
"uxth w26, w20",
"eor w27, w22, #0xffff",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"cmp w26, w22",
"cset x23, hi",
"cmp w26, w22",
"cset x24, hs",
"cmp x26, x4",
"cset x20, hi",
"cmp x26, x4",
"cset x22, hs",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w26, w22",
"msr nzcv, x20",
"rmif x21, #15, #nzcV"
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"bic w20, w26, w4",
"rmif x20, #15, #nzcV",
"bfxil x4, x26, #0, #16"
]
},
"sbb eax, -1": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"cset w21, hs",
"add w21, w20, w21",
"mov w22, w4",
"sub w4, w22, w21",
"eor w27, w22, w20",
"mov x26, x4",
"eor w27, w4, w20",
"cfinv",
"sbcs wzr, w22, w20",
"cfinv"
"sbcs w26, w4, w20",
"cfinv",
"mov x4, x26"
]
},
"sbb rax, -1": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"cset w21, hs",
"add x21, x20, x21",
"mov x22, x4",
"sub x4, x22, x21",
"eor w27, w22, w20",
"mov x26, x4",
"eor w27, w4, w20",
"cfinv",
"sbcs xzr, x22, x20",
"cfinv"
"sbcs x26, x4, x20",
"cfinv",
"mov x4, x26"
]
},
"and bl, cl": {

227
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
View File

@ -34,52 +34,50 @@
]
},
"adc al, 1": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 17,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"uxtb w27, w4",
"cset w20, hs",
"add w21, w27, #0x1 (1)",
"add w21, w21, w20",
"uxtb w26, w21",
"mov w20, #0x1",
"mov x27, x4",
"cset w21, hs",
"adc w20, w27, w20",
"uxtb w26, w20",
"cmp w26, #0x1 (1)",
"cset x20, lo",
"cmp w26, #0x1 (1)",
"cset x22, ls",
"cmp x21, #0x1 (1)",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"cmp w26, #0x1 (1)",
"cset x22, lo",
"cmp w26, #0x1 (1)",
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
"orr w20, w21, w20, lsl #29",
"bic w21, w26, w27",
"msr nzcv, x20",
"rmif x21, #7, #nzcV",
"rmif x20, #63, #nzCv",
"bic w20, w26, w27",
"rmif x20, #7, #nzcV",
"mov x4, x27",
"bfxil x4, x26, #0, #8"
]
},
"sbb al, 1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"cset w21, hs",
"add w20, w20, w21",
"uxtb w27, w4",
"sub w20, w27, w20",
"bfxil x4, x20, #0, #8",
"uxtb w26, w20",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"cmp w26, w27",
"cset x22, hi",
"cmp w26, w27",
"cset x23, hs",
"cmp x26, x27",
"cset x20, hi",
"cmp x26, x27",
"cset x22, hs",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w27, w26",
"msr nzcv, x20",
"rmif x21, #7, #nzcV"
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"bic w20, w27, w26",
"rmif x20, #7, #nzcV",
"mov x4, x27",
"bfxil x4, x26, #0, #8"
]
},
"and al, 1": {
@ -148,54 +146,48 @@
]
},
"adc al, -1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 16,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"eor w27, w20, #0xff",
"mov w20, #0xff",
"eor w27, w4, #0xff",
"cset w21, hs",
"add w22, w20, #0xff (255)",
"add w22, w22, w21",
"uxtb w26, w22",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"adc w20, w4, w20",
"uxtb w26, w20",
"cmp w26, #0xff (255)",
"cset x23, lo",
"cset x20, lo",
"cmp w26, #0xff (255)",
"cset x24, ls",
"cset x22, ls",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w21, w22, w21, lsl #29",
"bic w20, w20, w26",
"msr nzcv, x21",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"bic w20, w4, w26",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
},
"sbb al, -1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 17,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"eor w27, w4, #0xff",
"cset w21, hs",
"add w20, w20, w21",
"uxtb w22, w4",
"sub w20, w22, w20",
"bfxil x4, x20, #0, #8",
"sub w20, w4, w20",
"uxtb w26, w20",
"eor w27, w22, #0xff",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"cmp w26, w22",
"cset x23, hi",
"cmp w26, w22",
"cset x24, hs",
"cmp x26, x4",
"cset x20, hi",
"cmp x26, x4",
"cset x22, hs",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w26, w22",
"msr nzcv, x20",
"rmif x21, #7, #nzcV"
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"bic w20, w26, w4",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
},
"and al, -1": {
@ -295,7 +287,7 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov w27, w4",
"mov x27, x4",
"adcs w26, w27, w20",
"mov x4, x26"
]
@ -311,33 +303,27 @@
]
},
"sbb eax, 256": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cset w21, hs",
"add w21, w20, w21",
"mov w27, w4",
"sub w4, w27, w21",
"mov x26, x4",
"mov x27, x4",
"cfinv",
"sbcs wzr, w27, w20",
"cfinv"
"sbcs w26, w27, w20",
"cfinv",
"mov x4, x26"
]
},
"sbb rax, 256": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cset w21, hs",
"add x21, x20, x21",
"mov x27, x4",
"sub x4, x27, x21",
"mov x26, x4",
"cfinv",
"sbcs xzr, x27, x20",
"cfinv"
"sbcs x26, x27, x20",
"cfinv",
"mov x4, x26"
]
},
"and eax, 256": {
@ -468,7 +454,7 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov w27, w4",
"mov x27, x4",
"adcs w26, w27, w20",
"mov x4, x26"
]
@ -484,33 +470,27 @@
]
},
"sbb eax, -256": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"cset w21, hs",
"add w21, w20, w21",
"mov w27, w4",
"sub w4, w27, w21",
"mov x26, x4",
"mov x27, x4",
"cfinv",
"sbcs wzr, w27, w20",
"cfinv"
"sbcs w26, w27, w20",
"cfinv",
"mov x4, x26"
]
},
"sbb rax, -256": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffff00",
"cset w21, hs",
"add x21, x20, x21",
"mov x27, x4",
"sub x4, x27, x21",
"mov x26, x4",
"cfinv",
"sbcs xzr, x27, x20",
"cfinv"
"sbcs x26, x27, x20",
"cfinv",
"mov x4, x26"
]
},
"and eax, -256": {
@ -643,7 +623,7 @@
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov w27, w4",
"mov x27, x4",
"adcs w26, w27, w20",
"mov x4, x26"
]
@ -659,33 +639,27 @@
]
},
"sbb eax, 1": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add w21, w20, w21",
"mov w27, w4",
"sub w4, w27, w21",
"mov x26, x4",
"mov x27, x4",
"cfinv",
"sbcs wzr, w27, w20",
"cfinv"
"sbcs w26, w27, w20",
"cfinv",
"mov x4, x26"
]
},
"sbb rax, 1": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add x21, x20, x21",
"mov x27, x4",
"sub x4, x27, x21",
"mov x26, x4",
"cfinv",
"sbcs xzr, x27, x20",
"cfinv"
"sbcs x26, x27, x20",
"cfinv",
"mov x4, x26"
]
},
"and eax, 1": {
@ -813,13 +787,12 @@
]
},
"adc eax, -1": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"mov w21, w4",
"eor w27, w21, w20",
"adcs w26, w21, w20",
"eor w27, w4, w20",
"adcs w26, w4, w20",
"mov x4, x26"
]
},
@ -834,35 +807,27 @@
]
},
"sbb eax, -1": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"cset w21, hs",
"add w21, w20, w21",
"mov w22, w4",
"sub w4, w22, w21",
"eor w27, w22, w20",
"mov x26, x4",
"eor w27, w4, w20",
"cfinv",
"sbcs wzr, w22, w20",
"cfinv"
"sbcs w26, w4, w20",
"cfinv",
"mov x4, x26"
]
},
"sbb rax, -1": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"cset w21, hs",
"add x21, x20, x21",
"mov x22, x4",
"sub x4, x22, x21",
"eor w27, w22, w20",
"mov x26, x4",
"eor w27, w4, w20",
"cfinv",
"sbcs xzr, x22, x20",
"cfinv"
"sbcs x26, x4, x20",
"cfinv",
"mov x4, x26"
]
},
"and eax, -1": {

654
unittests/InstructionCountCI/Primary.json
View File

@ -359,68 +359,63 @@
]
},
"adc bl, cl": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 20,
"Comment": "0x10",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"eor w27, w20, w5",
"cset w21, hs",
"add w22, w20, w5",
"add w22, w22, w21",
"uxtb w26, w22",
"eor w27, w7, w5",
"cset w20, hs",
"adc w21, w7, w5",
"uxtb w26, w21",
"cmp x26, x5",
"cset x21, lo",
"cmp x26, x5",
"cset x22, ls",
"cmp x20, #0x1 (1)",
"csel x20, x22, x21, eq",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"cmp x26, x5",
"cset x23, lo",
"cmp x26, x5",
"cset x24, ls",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, w5",
"eor w20, w26, w20",
"bic w20, w20, w22",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"eor w21, w7, w5",
"eor w22, w26, w7",
"bic w21, w22, w21",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x7, x26, #0, #8",
"msr nzcv, x20"
]
},
"adc bx, cx": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 20,
"Comment": "0x11",
"ExpectedArm64ASM": [
"uxth w20, w7",
"eor w27, w20, w5",
"cset w21, hs",
"add w22, w20, w5",
"add w22, w22, w21",
"uxth w26, w22",
"eor w27, w7, w5",
"cset w20, hs",
"adc w21, w7, w5",
"uxth w26, w21",
"cmp x26, x5",
"cset x21, lo",
"cmp x26, x5",
"cset x22, ls",
"cmp x20, #0x1 (1)",
"csel x20, x22, x21, eq",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"cmp x26, x5",
"cset x23, lo",
"cmp x26, x5",
"cset x24, ls",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, w5",
"eor w20, w26, w20",
"bic w20, w20, w22",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"eor w21, w7, w5",
"eor w22, w26, w7",
"bic w21, w22, w21",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x7, x26, #0, #16",
"msr nzcv, x20"
]
},
"adc ebx, ecx": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": "0x11",
"ExpectedArm64ASM": [
"mov w20, w7",
"eor w27, w20, w5",
"adcs w26, w20, w5",
"eor w27, w7, w5",
"adcs w26, w7, w5",
"mov x7, x26"
]
},
@ -434,77 +429,72 @@
]
},
"db 0x12, 0xcb": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 20,
"Comment": [
"0x12",
"adc bl, cl but modrm.rm as source"
],
"ExpectedArm64ASM": [
"uxtb w20, w5",
"eor w27, w20, w7",
"cset w21, hs",
"add w22, w20, w7",
"add w22, w22, w21",
"uxtb w26, w22",
"eor w27, w5, w7",
"cset w20, hs",
"adc w21, w5, w7",
"uxtb w26, w21",
"cmp x26, x7",
"cset x21, lo",
"cmp x26, x7",
"cset x22, ls",
"cmp x20, #0x1 (1)",
"csel x20, x22, x21, eq",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"cmp x26, x7",
"cset x23, lo",
"cmp x26, x7",
"cset x24, ls",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, w7",
"eor w20, w26, w20",
"bic w20, w20, w22",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"eor w21, w5, w7",
"eor w22, w26, w5",
"bic w21, w22, w21",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x5, x26, #0, #8",
"msr nzcv, x20"
]
},
"db 0x66, 0x13, 0xcb": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 20,
"Comment": [
"0x13",
"adc bx, cx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"uxth w20, w5",
"eor w27, w20, w7",
"cset w21, hs",
"add w22, w20, w7",
"add w22, w22, w21",
"uxth w26, w22",
"eor w27, w5, w7",
"cset w20, hs",
"adc w21, w5, w7",
"uxth w26, w21",
"cmp x26, x7",
"cset x21, lo",
"cmp x26, x7",
"cset x22, ls",
"cmp x20, #0x1 (1)",
"csel x20, x22, x21, eq",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"cmp x26, x7",
"cset x23, lo",
"cmp x26, x7",
"cset x24, ls",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, w7",
"eor w20, w26, w20",
"bic w20, w20, w22",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"eor w21, w5, w7",
"eor w22, w26, w5",
"bic w21, w22, w21",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x5, x26, #0, #16",
"msr nzcv, x20"
]
},
"db 0x13, 0xcb": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": [
"0x13",
"adc ebx, ecx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"mov w20, w5",
"eor w27, w20, w7",
"adcs w26, w20, w7",
"eor w27, w5, w7",
"adcs w26, w5, w7",
"mov x5, x26"
]
},
@ -521,51 +511,53 @@
]
},
"adc al, 1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 20,
"Comment": "0x14",
"ExpectedArm64ASM": [
"uxtb w27, w4",
"cset w20, hs",
"add w21, w27, #0x1 (1)",
"add w21, w21, w20",
"uxtb w26, w21",
"mov w20, #0x1",
"mov x27, x4",
"cset w21, hs",
"adc w20, w27, w20",
"uxtb w26, w20",
"cmp w26, #0x1 (1)",
"cset x20, lo",
"cmp w26, #0x1 (1)",
"cset x22, ls",
"cmp x21, #0x1 (1)",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"cmp w26, #0x1 (1)",
"cset x22, lo",
"cmp w26, #0x1 (1)",
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
"orr w20, w21, w20, lsl #29",
"bic w21, w26, w27",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"mov x4, x27",
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
]
},
"adc ax, 1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 20,
"Comment": "0x15",
"ExpectedArm64ASM": [
"uxth w27, w4",
"cset w20, hs",
"add w21, w27, #0x1 (1)",
"add w21, w21, w20",
"uxth w26, w21",
"mov w20, #0x1",
"mov x27, x4",
"cset w21, hs",
"adc w20, w27, w20",
"uxth w26, w20",
"cmp w26, #0x1 (1)",
"cset x20, lo",
"cmp w26, #0x1 (1)",
"cset x22, ls",
"cmp x21, #0x1 (1)",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"cmp w26, #0x1 (1)",
"cset x22, lo",
"cmp w26, #0x1 (1)",
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
"orr w20, w21, w20, lsl #29",
"bic w21, w26, w27",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"mov x4, x27",
"bfxil x4, x26, #0, #16",
"msr nzcv, x20"
]
@ -575,7 +567,7 @@
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov w27, w4",
"mov x27, x4",
"adcs w26, w27, w20",
"mov x4, x26"
]
@ -591,52 +583,49 @@
]
},
"adc al, -1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 19,
"Comment": "0x14",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"eor w27, w20, #0xff",
"mov w20, #0xff",
"eor w27, w4, #0xff",
"cset w21, hs",
"add w22, w20, #0xff (255)",
"add w22, w22, w21",
"uxtb w26, w22",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"adc w20, w4, w20",
"uxtb w26, w20",
"cmp w26, #0xff (255)",
"cset x23, lo",
"cset x20, lo",
"cmp w26, #0xff (255)",
"cset x24, ls",
"cset x22, ls",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w21, w22, w21, lsl #29",
"bic w20, w20, w26",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"bic w21, w4, w26",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
]
},
"adc ax, -1": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 19,
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"uxth w21, w4",
"eor w27, w21, #0xffff",
"cset w22, hs",
"add w23, w21, w20",
"add w23, w23, w22",
"uxth w26, w23",
"cmn wzr, w26, lsl #16",
"mrs x23, nzcv",
"eor w27, w4, #0xffff",
"cset w21, hs",
"adc w22, w4, w20",
"uxth w26, w22",
"cmp w26, w20",
"cset x24, lo",
"cset x22, lo",
"cmp w26, w20",
"cset x20, ls",
"cmp x22, #0x1 (1)",
"csel x20, x20, x24, eq",
"orr w20, w23, w20, lsl #29",
"bic w21, w21, w26",
"cmp x21, #0x1 (1)",
"csel x20, x20, x22, eq",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"bic w21, w4, w26",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x4, x26, #0, #16",
@ -644,13 +633,12 @@
]
},
"adc eax, -1": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"mov w21, w4",
"eor w27, w21, w20",
"adcs w26, w21, w20",
"eor w27, w4, w20",
"adcs w26, w4, w20",
"mov x4, x26"
]
},
@ -665,392 +653,352 @@
]
},
"sbb bl, cl": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 21,
"Comment": "0x18",
"ExpectedArm64ASM": [
"uxtb w20, w5",
"cset w21, hs",
"add w22, w20, w21",
"uxtb w23, w7",
"sub w22, w23, w22",
"bfxil x7, x22, #0, #8",
"uxtb w26, w22",
"eor w27, w23, w20",
"eor w27, w7, w5",
"cset w20, hs",
"add w21, w5, w20",
"sub w21, w7, w21",
"uxtb w26, w21",
"cmp x26, x7",
"cset x21, hi",
"cmp x26, x7",
"cset x22, hs",
"cmp x20, #0x1 (1)",
"csel x20, x22, x21, eq",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"cmp w26, w23",
"cset x24, hi",
"cmp w26, w23",
"cset x25, hs",
"cmp x21, #0x1 (1)",
"csel x21, x25, x24, eq",
"orr w21, w22, w21, lsl #29",
"eor w20, w23, w20",
"eor w22, w26, w23",
"and w20, w22, w20",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"eor w21, w7, w5",
"eor w22, w26, w7",
"and w21, w22, w21",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x7, x26, #0, #8",
"msr nzcv, x20"
]
},
"sbb bx, cx": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 21,
"Comment": "0x19",
"ExpectedArm64ASM": [
"uxth w20, w5",
"cset w21, hs",
"add w22, w20, w21",
"uxth w23, w7",
"sub w22, w23, w22",
"bfxil x7, x22, #0, #16",
"uxth w26, w22",
"eor w27, w23, w20",
"eor w27, w7, w5",
"cset w20, hs",
"add w21, w5, w20",
"sub w21, w7, w21",
"uxth w26, w21",
"cmp x26, x7",
"cset x21, hi",
"cmp x26, x7",
"cset x22, hs",
"cmp x20, #0x1 (1)",
"csel x20, x22, x21, eq",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"cmp w26, w23",
"cset x24, hi",
"cmp w26, w23",
"cset x25, hs",
"cmp x21, #0x1 (1)",
"csel x21, x25, x24, eq",
"orr w21, w22, w21, lsl #29",
"eor w20, w23, w20",
"eor w22, w26, w23",
"and w20, w22, w20",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"eor w21, w7, w5",
"eor w22, w26, w7",
"and w21, w22, w21",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x7, x26, #0, #16",
"msr nzcv, x20"
]
},
"sbb ebx, ecx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 9,
"Comment": "0x19",
"ExpectedArm64ASM": [
"mov w20, w5",
"cset w21, hs",
"add w21, w20, w21",
"mov w22, w7",
"sub w7, w22, w21",
"eor w27, w22, w20",
"mov x26, x7",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs wzr, w22, w20",
"eor w27, w7, w5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"sbcs w26, w7, w5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x7, x26",
"msr nzcv, x20"
]
},
"sbb rbx, rcx": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 9,
"Comment": "0x19",
"ExpectedArm64ASM": [
"cset w20, hs",
"add x20, x5, x20",
"mov x21, x7",
"sub x7, x21, x20",
"eor w27, w21, w5",
"mov x26, x7",
"eor w27, w7, w5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"sbcs xzr, x21, x5",
"sbcs x26, x7, x5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x7, x26",
"msr nzcv, x20"
]
},
"db 0x1A, 0xcb": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 21,
"Comment": [
"0x1A",
"sbb bl, cl but modrm.rm as source"
],
"ExpectedArm64ASM": [
"uxtb w20, w7",
"cset w21, hs",
"add w22, w20, w21",
"uxtb w23, w5",
"sub w22, w23, w22",
"bfxil x5, x22, #0, #8",
"uxtb w26, w22",
"eor w27, w23, w20",
"eor w27, w5, w7",
"cset w20, hs",
"add w21, w7, w20",
"sub w21, w5, w21",
"uxtb w26, w21",
"cmp x26, x5",
"cset x21, hi",
"cmp x26, x5",
"cset x22, hs",
"cmp x20, #0x1 (1)",
"csel x20, x22, x21, eq",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"cmp w26, w23",
"cset x24, hi",
"cmp w26, w23",
"cset x25, hs",
"cmp x21, #0x1 (1)",
"csel x21, x25, x24, eq",
"orr w21, w22, w21, lsl #29",
"eor w20, w23, w20",
"eor w22, w26, w23",
"and w20, w22, w20",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"eor w21, w5, w7",
"eor w22, w26, w5",
"and w21, w22, w21",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x5, x26, #0, #8",
"msr nzcv, x20"
]
},
"db 0x66, 0x1B, 0xcb": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 21,
"Comment": [
"0x1B",
"sbb bx, cx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"uxth w20, w7",
"cset w21, hs",
"add w22, w20, w21",
"uxth w23, w5",
"sub w22, w23, w22",
"bfxil x5, x22, #0, #16",
"uxth w26, w22",
"eor w27, w23, w20",
"eor w27, w5, w7",
"cset w20, hs",
"add w21, w7, w20",
"sub w21, w5, w21",
"uxth w26, w21",
"cmp x26, x5",
"cset x21, hi",
"cmp x26, x5",
"cset x22, hs",
"cmp x20, #0x1 (1)",
"csel x20, x22, x21, eq",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"cmp w26, w23",
"cset x24, hi",
"cmp w26, w23",
"cset x25, hs",
"cmp x21, #0x1 (1)",
"csel x21, x25, x24, eq",
"orr w21, w22, w21, lsl #29",
"eor w20, w23, w20",
"eor w22, w26, w23",
"and w20, w22, w20",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"eor w21, w5, w7",
"eor w22, w26, w5",
"and w21, w22, w21",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x5, x26, #0, #16",
"msr nzcv, x20"
]
},
"db 0x1B, 0xcb": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 9,
"Comment": [
"0x1B",
"sbb ebx, ecx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"mov w20, w7",
"cset w21, hs",
"add w21, w20, w21",
"mov w22, w5",
"sub w5, w22, w21",
"eor w27, w22, w20",
"mov x26, x5",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs wzr, w22, w20",
"eor w27, w5, w7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"sbcs w26, w5, w7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x5, x26",
"msr nzcv, x20"
]
},
"db 0x48, 0x1B, 0xcb": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 9,
"Comment": [
"0x1B",
"sbb rbx, rcx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"cset w20, hs",
"add x20, x7, x20",
"mov x21, x5",
"sub x5, x21, x20",
"eor w27, w21, w7",
"mov x26, x5",
"eor w27, w5, w7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"sbcs xzr, x21, x7",
"sbcs x26, x5, x7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x5, x26",
"msr nzcv, x20"
]
},
"sbb al, 1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 21,
"Comment": "0x1C",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"cset w21, hs",
"add w20, w20, w21",
"uxtb w27, w4",
"sub w20, w27, w20",
"bfxil x4, x20, #0, #8",
"uxtb w26, w20",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"cmp w26, w27",
"cset x22, hi",
"cmp w26, w27",
"cset x23, hs",
"cmp x26, x27",
"cset x20, hi",
"cmp x26, x27",
"cset x22, hs",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"orr w20, w20, w21, lsl #29",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"bic w21, w27, w26",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"mov x4, x27",
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
]
},
"sbb ax, 1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 21,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"cset w21, hs",
"add w20, w20, w21",
"uxth w27, w4",
"sub w20, w27, w20",
"bfxil x4, x20, #0, #16",
"uxth w26, w20",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"cmp w26, w27",
"cset x22, hi",
"cmp w26, w27",
"cset x23, hs",
"cmp x26, x27",
"cset x20, hi",
"cmp x26, x27",
"cset x22, hs",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"orr w20, w20, w21, lsl #29",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"bic w21, w27, w26",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"mov x4, x27",
"bfxil x4, x26, #0, #16",
"msr nzcv, x20"
]
},
"sbb eax, 1": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 10,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add w21, w20, w21",
"mov w27, w4",
"sub w4, w27, w21",
"mov x26, x4",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs wzr, w27, w20",
"sbcs w26, w27, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
]
},
"sbb rax, 1": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 10,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add x21, x20, x21",
"mov x27, x4",
"sub x4, x27, x21",
"mov x26, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs xzr, x27, x20",
"sbcs x26, x27, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
]
},
"sbb al, -1": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 20,
"Comment": "0x1C",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"eor w27, w4, #0xff",
"cset w21, hs",
"add w20, w20, w21",
"uxtb w22, w4",
"sub w20, w22, w20",
"bfxil x4, x20, #0, #8",
"sub w20, w4, w20",
"uxtb w26, w20",
"eor w27, w22, #0xff",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"cmp w26, w22",
"cset x23, hi",
"cmp w26, w22",
"cset x24, hs",
"cmp x26, x4",
"cset x20, hi",
"cmp x26, x4",
"cset x22, hs",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w26, w22",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"bic w21, w26, w4",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
]
},
"sbb ax, -1": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 20,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"eor w27, w4, #0xffff",
"cset w21, hs",
"add w20, w20, w21",
"uxth w22, w4",
"sub w20, w22, w20",
"bfxil x4, x20, #0, #16",
"sub w20, w4, w20",
"uxth w26, w20",
"eor w27, w22, #0xffff",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"cmp w26, w22",
"cset x23, hi",
"cmp w26, w22",
"cset x24, hs",
"cmp x26, x4",
"cset x20, hi",
"cmp x26, x4",
"cset x22, hs",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w26, w22",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"bic w21, w26, w4",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x4, x26, #0, #16",
"msr nzcv, x20"
]
},
"sbb eax, -1": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"cset w21, hs",
"add w21, w20, w21",
"mov w22, w4",
"sub w4, w22, w21",
"eor w27, w22, w20",
"mov x26, x4",
"eor w27, w4, w20",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs wzr, w22, w20",
"sbcs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
]
},
"sbb rax, -1": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"cset w21, hs",
"add x21, x20, x21",
"mov x22, x4",
"sub x4, x22, x21",
"eor w27, w22, w20",
"mov x26, x4",
"eor w27, w4, w20",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs xzr, x22, x20",
"sbcs x26, x4, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
]
},

201
unittests/InstructionCountCI/PrimaryGroup.json
View File

@ -37,53 +37,55 @@
]
},
"adc al, 1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 20,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"uxtb w27, w4",
"cset w20, hs",
"add w21, w27, #0x1 (1)",
"add w21, w21, w20",
"uxtb w26, w21",
"mov w20, #0x1",
"mov x27, x4",
"cset w21, hs",
"adc w20, w27, w20",
"uxtb w26, w20",
"cmp w26, #0x1 (1)",
"cset x20, lo",
"cmp w26, #0x1 (1)",
"cset x22, ls",
"cmp x21, #0x1 (1)",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"cmp w26, #0x1 (1)",
"cset x22, lo",
"cmp w26, #0x1 (1)",
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
"orr w20, w21, w20, lsl #29",
"bic w21, w26, w27",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"mov x4, x27",
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
]
},
"sbb al, 1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 21,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"cset w21, hs",
"add w20, w20, w21",
"uxtb w27, w4",
"sub w20, w27, w20",
"bfxil x4, x20, #0, #8",
"uxtb w26, w20",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"cmp w26, w27",
"cset x22, hi",
"cmp w26, w27",
"cset x23, hs",
"cmp x26, x27",
"cset x20, hi",
"cmp x26, x27",
"cset x22, hs",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"orr w20, w20, w21, lsl #29",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"bic w21, w27, w26",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"mov x4, x27",
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
]
},
@ -157,55 +159,53 @@
]
},
"adc al, -1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 19,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"eor w27, w20, #0xff",
"mov w20, #0xff",
"eor w27, w4, #0xff",
"cset w21, hs",
"add w22, w20, #0xff (255)",
"add w22, w22, w21",
"uxtb w26, w22",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"adc w20, w4, w20",
"uxtb w26, w20",
"cmp w26, #0xff (255)",
"cset x23, lo",
"cset x20, lo",
"cmp w26, #0xff (255)",
"cset x24, ls",
"cset x22, ls",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w21, w22, w21, lsl #29",
"bic w20, w20, w26",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"bic w21, w4, w26",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
]
},
"sbb al, -1": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 20,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"eor w27, w4, #0xff",
"cset w21, hs",
"add w20, w20, w21",
"uxtb w22, w4",
"sub w20, w22, w20",
"bfxil x4, x20, #0, #8",
"sub w20, w4, w20",
"uxtb w26, w20",
"eor w27, w22, #0xff",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"cmp w26, w22",
"cset x23, hi",
"cmp w26, w22",
"cset x24, hs",
"cmp x26, x4",
"cset x20, hi",
"cmp x26, x4",
"cset x22, hs",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w26, w22",
"csel x20, x22, x20, eq",
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"bic w21, w26, w4",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
]
},
@ -310,7 +310,7 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov w27, w4",
"mov x27, x4",
"adcs w26, w27, w20",
"mov x4, x26"
]
@ -326,40 +326,34 @@
]
},
"sbb eax, 256": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 10,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cset w21, hs",
"add w21, w20, w21",
"mov w27, w4",
"sub w4, w27, w21",
"mov x26, x4",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs wzr, w27, w20",
"sbcs w26, w27, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
]
},
"sbb rax, 256": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 10,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cset w21, hs",
"add x21, x20, x21",
"mov x27, x4",
"sub x4, x27, x21",
"mov x26, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs xzr, x27, x20",
"sbcs x26, x27, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
]
},
@ -499,7 +493,7 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov w27, w4",
"mov x27, x4",
"adcs w26, w27, w20",
"mov x4, x26"
]
@ -515,40 +509,34 @@
]
},
"sbb eax, -256": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 10,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"cset w21, hs",
"add w21, w20, w21",
"mov w27, w4",
"sub w4, w27, w21",
"mov x26, x4",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs wzr, w27, w20",
"sbcs w26, w27, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
]
},
"sbb rax, -256": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 10,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffff00",
"cset w21, hs",
"add x21, x20, x21",
"mov x27, x4",
"sub x4, x27, x21",
"mov x26, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs xzr, x27, x20",
"sbcs x26, x27, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
]
},
@ -690,7 +678,7 @@
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov w27, w4",
"mov x27, x4",
"adcs w26, w27, w20",
"mov x4, x26"
]
@ -706,40 +694,34 @@
]
},
"sbb eax, 1": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 10,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add w21, w20, w21",
"mov w27, w4",
"sub w4, w27, w21",
"mov x26, x4",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs wzr, w27, w20",
"sbcs w26, w27, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
]
},
"sbb rax, 1": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 10,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add x21, x20, x21",
"mov x27, x4",
"sub x4, x27, x21",
"mov x26, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs xzr, x27, x20",
"sbcs x26, x27, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
]
},
@ -876,13 +858,12 @@
]
},
"adc eax, -1": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"mov w21, w4",
"eor w27, w21, w20",
"adcs w26, w21, w20",
"eor w27, w4, w20",
"adcs w26, w4, w20",
"mov x4, x26"
]
},
@ -897,42 +878,34 @@
]
},
"sbb eax, -1": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"cset w21, hs",
"add w21, w20, w21",
"mov w22, w4",
"sub w4, w22, w21",
"eor w27, w22, w20",
"mov x26, x4",
"eor w27, w4, w20",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs wzr, w22, w20",
"sbcs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
]
},
"sbb rax, -1": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"cset w21, hs",
"add x21, x20, x21",
"mov x22, x4",
"sub x4, x22, x21",
"eor w27, w22, w20",
"mov x26, x4",
"eor w27, w4, w20",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs xzr, x22, x20",
"sbcs x26, x4, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
]
},

8
unittests/InstructionCountCI/Primary_32Bit.json
View File

@ -484,14 +484,10 @@
]
},
"salc": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 2,
"Comment": "0xd6",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"cset w21, hs",
"add w20, w20, w21",
"uxtb w21, w4",
"sub w20, w21, w20",
"csetm w20, hs",
"bfxil w4, w20, #0, #8"
]
}