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IR: Change StoreRegister to use IR::OpSize

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This commit is contained in:
Ryan Houdek 2024-10-27 15:37:05 -07:00
parent f0f3c215ce
commit c045e14837
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3 changed files with 4 additions and 4 deletions
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4
FEXCore/Source/Interface/Core/Core.cpp
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@ -1017,9 +1017,9 @@ void ContextImpl::AddThunkTrampolineIRHandler(uintptr_t Entrypoint, uintptr_t Gu
IRHeader.first->Blocks = emit->WrapNode(Block);
emit->SetCurrentCodeBlock(Block);
const uint8_t GPRSize = GetGPRSize();
const auto GPRSize = GetGPROpSize();
if (GPRSize == 8) {
if (GPRSize == IR::OpSize::i64Bit) {
emit->_StoreRegister(emit->_Constant(Entrypoint), X86State::REG_R11, IR::GPRClass, GPRSize);
} else {
emit->_StoreContext(GPRSize, IR::FPRClass, emit->_VCastFromGPR(8, 8, emit->_Constant(Entrypoint)), offsetof(Core::CPUState, mm[0][0]));

2
FEXCore/Source/Interface/Core/OpcodeDispatcher.h
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@ -1188,7 +1188,7 @@ public:
CalculateDeferredFlags();
const uint8_t GPRSize = CTX->GetGPRSize();
const auto GPRSize = CTX->GetGPROpSize();
const auto VectorSize = GetGuestVectorLength();
// Write backwards. This is a heuristic to improve coalescing, since we

2
FEXCore/Source/Interface/IR/IR.json
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@ -376,7 +376,7 @@
"DestSize": "Size"
},
"StoreRegister SSA:$Value, u32:$Reg, RegisterClass:$Class, u8:#Size": {
"StoreRegister SSA:$Value, u32:$Reg, RegisterClass:$Class, OpSize:#Size": {
"HasSideEffects": true,
"Desc": ["Stores a value to a given register.",
"Size must match the execution mode."],