mirror of
https://github.com/FEX-Emu/FEX.git
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Merge pull request #3368 from bylaws/preprcr
FEXCore: Fix RCL/RCR shift wraparound behaviour
This commit is contained in:
Ryan Houdek
GitHub
commit
c0be974272
@ -2421,63 +2421,74 @@ void OpDispatchBuilder::RCROp(OpcodeArgs) {
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return;
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}
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const auto Mask = (Size == 64) ? 0x3F : 0x1F;
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// Calculate flags early.
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CalculateDeferredFlags();
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auto CF = GetRFLAG(FEXCore::X86State::RFLAG_CF_RAW_LOC);
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OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[1], Op->Flags);
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OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags);
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const auto OpSize = OpSizeFromSrc(Op);
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CalculateFlags_ShiftVariable(Src, [this, CF, Op, Size, Src](){
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const auto OpSize = OpSizeFromSrc(Op);
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OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags);
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// Res = Src >> Shift
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OrderedNode *Res = _Lshr(OpSize, Dest, Src);
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auto CF = GetRFLAG(FEXCore::X86State::RFLAG_CF_RAW_LOC);
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// Res = Src >> Shift
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OrderedNode *Res = _Lshr(OpSize, Dest, Src);
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uint64_t Const;
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if (IsValueConstant(WrapNode(Src), &Const)) {
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Const &= Mask;
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if (!Const)
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return;
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uint64_t Const;
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if (!IsValueConstant(WrapNode(Src), &Const)) {
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auto Zero = _Constant(Size, 0);
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auto One = _Constant(Size, 1);
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InvalidateDeferredFlags();
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// Res |= (Src << (Size - Shift + 1));
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OrderedNode *SrcShl = _Sub(OpSize, _Constant(Size, Size + 1), Src);
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auto TmpHigher = _Lshl(OpSize, Dest, SrcShl);
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// Constant folded version of the above, with fused shifts.
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if (Const > 1)
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Res = _Orlshl(OpSize, Res, Dest, Size + 1 - Const);
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auto CompareResult = _Select(FEXCore::IR::COND_UGT, Src, One, TmpHigher, Zero);
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Res = _Or(OpSize, Res, CompareResult);
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// Our new CF will be bit (Shift - 1) of the source.
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SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(Dest, Const - 1, true);
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// Our new CF will be bit (Shift - 1) of the source. this is hoisted up to
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// avoid the need to copy the source.
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auto NewCF = _Lshr(OpSize, Dest, _Sub(OpSize, Src, One));
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SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(NewCF, 0, true);
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// Since shift != 0 we can inject the CF
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Res = _Orlshl(OpSize, Res, CF, Size - Const);
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// Since shift != 0 we can inject the CF
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OrderedNode *CFShl = _Sub(OpSize, _Constant(Size, Size), Src);
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Res = _Or(OpSize, Res, _Lshl(OpSize::i64Bit, CF, CFShl));
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// OF is the top two MSBs XOR'd together
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// Only when Shift == 1, it is undefined otherwise
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// OF is the top two MSBs XOR'd together
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// Only when Shift == 1, it is undefined otherwise
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if (Const == 1) {
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auto Xor = _XorShift(OpSize, Res, Res, ShiftType::LSR, 1);
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SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(Xor, Size - 2, true);
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} else {
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// Constant folded version of the above, with fused shifts.
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if (Const > 1)
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Res = _Orlshl(OpSize, Res, Dest, Size + 1 - Const);
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// Our new CF will be bit (Shift - 1) of the source.
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SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(Dest, Const - 1, true);
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// Since shift != 0 we can inject the CF
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Res = _Orlshl(OpSize, Res, CF, Size - Const);
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// OF is the top two MSBs XOR'd together
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// Only when Shift == 1, it is undefined otherwise
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if (Const == 1) {
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auto Xor = _XorShift(OpSize, Res, Res, ShiftType::LSR, 1);
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SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(Xor, Size - 2, true);
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}
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}
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StoreResult(GPRClass, Op, Res, -1);
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return;
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}
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OrderedNode *SrcMasked = _And(OpSize, Src, _Constant(Size, Mask));
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CalculateFlags_ShiftVariable(SrcMasked, [this, CF, Op, Size, OpSize, SrcMasked, Dest, &Res](){
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auto Zero = _Constant(Size, 0);
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auto One = _Constant(Size, 1);
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// Res |= (SrcMasked << (Size - Shift + 1));
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OrderedNode *SrcMaskedShl = _Sub(OpSize, _Constant(Size, Size + 1), SrcMasked);
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auto TmpHigher = _Lshl(OpSize, Dest, SrcMaskedShl);
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auto CompareResult = _Select(FEXCore::IR::COND_UGT, SrcMasked, One, TmpHigher, Zero);
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Res = _Or(OpSize, Res, CompareResult);
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// Our new CF will be bit (Shift - 1) of the source. this is hoisted up to
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// avoid the need to copy the source.
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auto NewCF = _Lshr(OpSize, Dest, _Sub(OpSize, SrcMasked, One));
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SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(NewCF, 0, true);
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// Since shift != 0 we can inject the CF
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OrderedNode *CFShl = _Sub(OpSize, _Constant(Size, Size), SrcMasked);
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Res = _Or(OpSize, Res, _Lshl(OpSize::i64Bit, CF, CFShl));
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// OF is the top two MSBs XOR'd together
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// Only when Shift == 1, it is undefined otherwise
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auto Xor = _XorShift(OpSize, Res, Res, ShiftType::LSR, 1);
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SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(Xor, Size - 2, true);
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StoreResult(GPRClass, Op, Res, -1);
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});
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}
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@ -2607,65 +2618,77 @@ void OpDispatchBuilder::RCLOp(OpcodeArgs) {
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return;
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}
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const auto Mask = (Size == 64) ? 0x3F : 0x1F;
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// Calculate flags early.
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CalculateDeferredFlags();
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OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[1], Op->Flags);
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OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags);
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const auto OpSize = OpSizeFromSrc(Op);
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// Res = Src << Shift
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OrderedNode *Res = _Lshl(OpSize, Dest, Src);
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auto CF = GetRFLAG(FEXCore::X86State::RFLAG_CF_RAW_LOC);
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CalculateFlags_ShiftVariable(Src, [this, CF, Op, Size, Src](){
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// Res = Src << Shift
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const auto OpSize = OpSizeFromSrc(Op);
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OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags);
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OrderedNode *Res = _Lshl(OpSize, Dest, Src);
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uint64_t Const;
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if (IsValueConstant(WrapNode(Src), &Const)) {
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Const &= Mask;
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if (!Const)
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return;
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uint64_t Const;
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if (!IsValueConstant(WrapNode(Src), &Const)) {
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// Res |= (Src << (Size - Shift + 1));
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OrderedNode *SrcShl = _Sub(OpSize, _Constant(Size, Size + 1), Src);
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auto TmpHigher = _Lshr(OpSize, Dest, SrcShl);
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InvalidateDeferredFlags();
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auto One = _Constant(Size, 1);
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auto Zero = _Constant(Size, 0);
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// Res |= (Src << (Size - Shift + 1));
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if (Const > 1)
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Res = _Orlshr(OpSize, Res, Dest, Size + 1 - Const);
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auto CompareResult = _Select(FEXCore::IR::COND_UGT, Src, One, TmpHigher, Zero);
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Res = _Or(OpSize, Res, CompareResult);
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// Our new CF will be bit (Shift - 1) of the source
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SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(Dest, Size - Const, true);
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// Our new CF will be bit (Shift - 1) of the source
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auto NewCF = _Lshr(OpSize, Dest, _Sub(OpSize, _Constant(Size, Size), Src));
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SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(NewCF, 0, true);
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// Since Shift != 0 we can inject the CF
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Res = _Orlshl(OpSize, Res, CF, Const - 1);
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// Since Shift != 0 we can inject the CF
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OrderedNode *CFShl = _Sub(OpSize, Src, _Constant(Size, 1));
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auto TmpCF = _Lshl(OpSize::i64Bit, CF, CFShl);
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Res = _Or(OpSize, Res, TmpCF);
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// OF is the top two MSBs XOR'd together
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// Only when Shift == 1, it is undefined otherwise
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//
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// Note that NewCF has garbage in the upper bits, but we ignore them here
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// and mask as part of the set after.
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auto NewOF = _XorShift(OpSize, Res, NewCF, ShiftType::LSL, Size - 1);
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// OF is the top two MSBs XOR'd together
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// Only when Shift == 1, it is undefined otherwise
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if (Const == 1) {
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auto NewOF = _Xor(OpSize, Res, Dest);
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SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(NewOF, Size - 1, true);
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} else {
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// Res |= (Src << (Size - Shift + 1));
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if (Const > 1)
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Res = _Orlshr(OpSize, Res, Dest, Size + 1 - Const);
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// Our new CF will be bit (Shift - 1) of the source
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SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(Dest, Size - Const, true);
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// Since Shift != 0 we can inject the CF
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Res = _Orlshl(OpSize, Res, CF, Const - 1);
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// OF is the top two MSBs XOR'd together
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// Only when Shift == 1, it is undefined otherwise
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if (Const == 1) {
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auto NewOF = _Xor(OpSize, Res, Dest);
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SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(NewOF, Size - 1, true);
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}
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}
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StoreResult(GPRClass, Op, Res, -1);
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return;
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}
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OrderedNode *SrcMasked = _And(OpSize, Src, _Constant(Size, Mask));
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CalculateFlags_ShiftVariable(SrcMasked, [this, CF, Op, Size, OpSize, SrcMasked, Dest, &Res](){
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// Res |= (SrcMasked << (Size - Shift + 1));
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OrderedNode *SrcMaskedShl = _Sub(OpSize, _Constant(Size, Size + 1), SrcMasked);
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auto TmpHigher = _Lshr(OpSize, Dest, SrcMaskedShl);
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auto One = _Constant(Size, 1);
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auto Zero = _Constant(Size, 0);
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auto CompareResult = _Select(FEXCore::IR::COND_UGT, SrcMasked, One, TmpHigher, Zero);
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Res = _Or(OpSize, Res, CompareResult);
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// Our new CF will be bit (Shift - 1) of the source
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auto NewCF = _Lshr(OpSize, Dest, _Sub(OpSize, _Constant(Size, Size), SrcMasked));
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SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(NewCF, 0, true);
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// Since Shift != 0 we can inject the CF
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OrderedNode *CFShl = _Sub(OpSize, SrcMasked, _Constant(Size, 1));
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auto TmpCF = _Lshl(OpSize::i64Bit, CF, CFShl);
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Res = _Or(OpSize, Res, TmpCF);
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// OF is the top two MSBs XOR'd together
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// Only when Shift == 1, it is undefined otherwise
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//
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// Note that NewCF has garbage in the upper bits, but we ignore them here
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// and mask as part of the set after.
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auto NewOF = _XorShift(OpSize, Res, NewCF, ShiftType::LSL, Size - 1);
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SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(NewOF, Size - 1, true);
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StoreResult(GPRClass, Op, Res, -1);
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});
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}
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50
unittests/ASM/PrimaryGroup/2_D3_02_4.asm
Normal file
50
unittests/ASM/PrimaryGroup/2_D3_02_4.asm
Normal file
@ -0,0 +1,50 @@
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%ifdef CONFIG
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{
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"RegData": {
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"RBX": "0x00000006",
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"RDI": "0x00000004",
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"RDX": "0x00000002",
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"RSI": "0x00000000",
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"R8": "0x0",
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"R9": "0x0",
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"R10": "0x1",
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"R11": "0x1"
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}
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}
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%endif
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mov rbx, 0x00000001
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mov rdi, 0x00000001
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mov rdx, 0x40000000
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mov rsi, 0x40000000
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mov rcx, 34 ; Test wraparound
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stc
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rcl ebx, cl
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lahf
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mov r8w, ax
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shr r8, 8
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and r8, 1 ; We only care about carry flag here
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clc
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rcl edi, cl
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lahf
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mov r9w, ax
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shr r9, 8
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and r9, 1 ; We only care about carry flag here
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stc
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rcl edx, cl
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lahf
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mov r10w, ax
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shr r10, 8
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and r10, 1 ; We only care about carry flag here
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clc
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rcl esi, cl
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lahf
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mov r11w, ax
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shr r11, 8
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and r11, 1 ; We only care about carry flag here
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hlt
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50
unittests/ASM/PrimaryGroup/2_D3_02_5.asm
Normal file
50
unittests/ASM/PrimaryGroup/2_D3_02_5.asm
Normal file
@ -0,0 +1,50 @@
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%ifdef CONFIG
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{
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"RegData": {
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"RBX": "0x00000001",
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"RDI": "0x00000001",
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"RDX": "0x40000000",
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"RSI": "0x40000000",
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"R8": "0x1",
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"R9": "0x0",
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"R10": "0x1",
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"R11": "0x0"
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}
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}
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%endif
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mov rbx, 0x00000001
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mov rdi, 0x00000001
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mov rdx, 0x40000000
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mov rsi, 0x40000000
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mov rcx, 32 ; Test wraparound with zero shift
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stc
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rcl ebx, cl
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lahf
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mov r8w, ax
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shr r8, 8
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and r8, 1 ; We only care about carry flag here
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clc
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rcl edi, cl
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lahf
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mov r9w, ax
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shr r9, 8
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and r9, 1 ; We only care about carry flag here
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stc
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rcl edx, cl
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lahf
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mov r10w, ax
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shr r10, 8
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and r10, 1 ; We only care about carry flag here
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clc
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rcl esi, cl
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lahf
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mov r11w, ax
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shr r11, 8
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and r11, 1 ; We only care about carry flag here
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hlt
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50
unittests/ASM/PrimaryGroup/2_D3_03_7.asm
Normal file
50
unittests/ASM/PrimaryGroup/2_D3_03_7.asm
Normal file
@ -0,0 +1,50 @@
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%ifdef CONFIG
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{
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"RegData": {
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"RBX": "0x40000000",
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"RDI": "0x00000000",
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"RDX": "0x60000000",
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"RSI": "0x20000000",
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"R8": "0x1",
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"R9": "0x1",
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"R10": "0x0",
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"R11": "0x0"
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}
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}
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%endif
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mov rbx, 0x00000002
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mov rdi, 0x00000002
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mov rdx, 0x80000000
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mov rsi, 0x80000000
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mov rcx, 34 ; Test wraparound
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stc
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rcr ebx, cl
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lahf
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mov r8w, ax
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shr r8, 8
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and r8, 1 ; We only care about carry flag here
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clc
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rcr edi, cl
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lahf
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mov r9w, ax
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shr r9, 8
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and r9, 1 ; We only care about carry flag here
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stc
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rcr edx, cl
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lahf
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mov r10w, ax
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shr r10, 8
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and r10, 1 ; We only care about carry flag here
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clc
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rcr esi, cl
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lahf
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mov r11w, ax
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shr r11, 8
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and r11, 1 ; We only care about carry flag here
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hlt
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50
unittests/ASM/PrimaryGroup/2_D3_03_8.asm
Normal file
50
unittests/ASM/PrimaryGroup/2_D3_03_8.asm
Normal file
@ -0,0 +1,50 @@
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%ifdef CONFIG
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{
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"RegData": {
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"RBX": "0x00000002",
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"RDI": "0x00000002",
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"RDX": "0x80000000",
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"RSI": "0x80000000",
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"R8": "0x1",
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"R9": "0x0",
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"R10": "0x1",
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"R11": "0x0"
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}
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}
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%endif
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mov rbx, 0x00000002
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mov rdi, 0x00000002
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mov rdx, 0x80000000
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mov rsi, 0x80000000
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mov rcx, 32 ; Test wraparound with zero shift
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stc
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rcr ebx, cl
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lahf
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mov r8w, ax
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shr r8, 8
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and r8, 1 ; We only care about carry flag here
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clc
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rcr edi, cl
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lahf
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mov r9w, ax
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shr r9, 8
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and r9, 1 ; We only care about carry flag here
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stc
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rcr edx, cl
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lahf
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mov r10w, ax
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shr r10, 8
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and r10, 1 ; We only care about carry flag here
|
||||
|
||||
clc
|
||||
rcr esi, cl
|
||||
lahf
|
||||
mov r11w, ax
|
||||
shr r11, 8
|
||||
and r11, 1 ; We only care about carry flag here
|
||||
|
||||
hlt
|
||||
@ -1230,23 +1230,23 @@
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "GROUP2 0xC1 /2",
|
||||
"ExpectedArm64ASM": [
|
||||
"cset w20, hs",
|
||||
"mov w21, w4",
|
||||
"lsl w22, w21, #2",
|
||||
"orr w22, w22, w21, lsr #31",
|
||||
"rmif x21, #29, #nzCv",
|
||||
"orr w4, w22, w20, lsl #1"
|
||||
"mov w20, w4",
|
||||
"lsl w21, w20, #2",
|
||||
"cset w22, hs",
|
||||
"orr w21, w21, w20, lsr #31",
|
||||
"rmif x20, #29, #nzCv",
|
||||
"orr w4, w21, w22, lsl #1"
|
||||
]
|
||||
},
|
||||
"rcl rax, 2": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP2 0xC1 /2",
|
||||
"ExpectedArm64ASM": [
|
||||
"cset w20, hs",
|
||||
"lsl x21, x4, #2",
|
||||
"orr x21, x21, x4, lsr #63",
|
||||
"lsl x20, x4, #2",
|
||||
"cset w21, hs",
|
||||
"orr x20, x20, x4, lsr #63",
|
||||
"rmif x4, #61, #nzCv",
|
||||
"orr x4, x21, x20, lsl #1"
|
||||
"orr x4, x20, x21, lsl #1"
|
||||
]
|
||||
},
|
||||
"rcr ax, 2": {
|
||||
@ -1278,23 +1278,23 @@
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "GROUP2 0xC1 /3",
|
||||
"ExpectedArm64ASM": [
|
||||
"cset w20, hs",
|
||||
"mov w21, w4",
|
||||
"lsr w22, w21, #2",
|
||||
"orr w22, w22, w21, lsl #31",
|
||||
"rmif x21, #0, #nzCv",
|
||||
"orr w4, w22, w20, lsl #30"
|
||||
"mov w20, w4",
|
||||
"lsr w21, w20, #2",
|
||||
"cset w22, hs",
|
||||
"orr w21, w21, w20, lsl #31",
|
||||
"rmif x20, #0, #nzCv",
|
||||
"orr w4, w21, w22, lsl #30"
|
||||
]
|
||||
},
|
||||
"rcr rax, 2": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP2 0xC1 /3",
|
||||
"ExpectedArm64ASM": [
|
||||
"cset w20, hs",
|
||||
"lsr x21, x4, #2",
|
||||
"orr x21, x21, x4, lsl #63",
|
||||
"lsr x20, x4, #2",
|
||||
"cset w21, hs",
|
||||
"orr x20, x20, x4, lsl #63",
|
||||
"rmif x4, #0, #nzCv",
|
||||
"orr x4, x21, x20, lsl #62"
|
||||
"orr x4, x20, x21, lsl #62"
|
||||
]
|
||||
},
|
||||
"shl ax, 2": {
|
||||
@ -2057,59 +2057,61 @@
|
||||
]
|
||||
},
|
||||
"rcl eax, cl": {
|
||||
"ExpectedInstructionCount": 23,
|
||||
"ExpectedInstructionCount": 24,
|
||||
"Comment": "GROUP2 0xd3 /2",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, w5",
|
||||
"cset w21, hs",
|
||||
"cbz x20, #+0x54",
|
||||
"mov w22, w4",
|
||||
"lsl w23, w22, w20",
|
||||
"mov w21, w4",
|
||||
"lsl w22, w21, w20",
|
||||
"cset w23, hs",
|
||||
"and w20, w20, #0x1f",
|
||||
"cbz x20, #+0x4c",
|
||||
"mov w24, #0x21",
|
||||
"sub w24, w24, w20",
|
||||
"lsr w24, w22, w24",
|
||||
"lsr w24, w21, w24",
|
||||
"mov w25, #0x0",
|
||||
"mrs x30, nzcv",
|
||||
"cmp w20, #0x1 (1)",
|
||||
"csel w24, w24, w25, hi",
|
||||
"orr w23, w23, w24",
|
||||
"orr w22, w22, w24",
|
||||
"mov w24, #0x20",
|
||||
"sub w24, w24, w20",
|
||||
"lsr w22, w22, w24",
|
||||
"lsr w21, w21, w24",
|
||||
"msr nzcv, x30",
|
||||
"rmif x22, #63, #nzCv",
|
||||
"rmif x21, #63, #nzCv",
|
||||
"sub w20, w20, #0x1 (1)",
|
||||
"lsl x20, x21, x20",
|
||||
"orr w4, w23, w20",
|
||||
"eor w20, w4, w22, lsl #31",
|
||||
"lsl x20, x23, x20",
|
||||
"orr w4, w22, w20",
|
||||
"eor w20, w4, w21, lsl #31",
|
||||
"rmif x20, #31, #nzcV"
|
||||
]
|
||||
},
|
||||
"rcl rax, cl": {
|
||||
"ExpectedInstructionCount": 22,
|
||||
"ExpectedInstructionCount": 23,
|
||||
"Comment": "GROUP2 0xd3 /2",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, x5",
|
||||
"cset w21, hs",
|
||||
"cbz x20, #+0x50",
|
||||
"lsl x22, x4, x20",
|
||||
"mov w23, #0x41",
|
||||
"sub x23, x23, x20",
|
||||
"lsr x23, x4, x23",
|
||||
"mov w24, #0x0",
|
||||
"mrs x25, nzcv",
|
||||
"cmp x20, #0x1 (1)",
|
||||
"csel x23, x23, x24, hi",
|
||||
"orr x22, x22, x23",
|
||||
"mov w23, #0x40",
|
||||
"sub x23, x23, x20",
|
||||
"lsr x23, x4, x23",
|
||||
"msr nzcv, x25",
|
||||
"rmif x23, #63, #nzCv",
|
||||
"sub x20, x20, #0x1 (1)",
|
||||
"lsl x20, x21, x20",
|
||||
"orr x4, x22, x20",
|
||||
"eor x20, x4, x23, lsl #63",
|
||||
"mov x20, x4",
|
||||
"lsl x21, x20, x5",
|
||||
"cset w22, hs",
|
||||
"and x23, x5, #0x3f",
|
||||
"cbz x23, #+0x4c",
|
||||
"mov w24, #0x41",
|
||||
"sub x24, x24, x23",
|
||||
"lsr x24, x20, x24",
|
||||
"mov w25, #0x0",
|
||||
"mrs x30, nzcv",
|
||||
"cmp x23, #0x1 (1)",
|
||||
"csel x24, x24, x25, hi",
|
||||
"orr x21, x21, x24",
|
||||
"mov w24, #0x40",
|
||||
"sub x24, x24, x23",
|
||||
"lsr x20, x20, x24",
|
||||
"msr nzcv, x30",
|
||||
"rmif x20, #63, #nzCv",
|
||||
"sub x23, x23, #0x1 (1)",
|
||||
"lsl x22, x22, x23",
|
||||
"orr x4, x21, x22",
|
||||
"eor x20, x4, x20, lsl #63",
|
||||
"rmif x20, #63, #nzcV"
|
||||
]
|
||||
},
|
||||
@ -2141,58 +2143,60 @@
|
||||
]
|
||||
},
|
||||
"rcr eax, cl": {
|
||||
"ExpectedInstructionCount": 23,
|
||||
"ExpectedInstructionCount": 24,
|
||||
"Comment": "GROUP2 0xd3 /3",
|
||||
"ExpectedArm64ASM": [
|
||||
"cset w20, hs",
|
||||
"mov w21, w5",
|
||||
"cbz x21, #+0x54",
|
||||
"mov w22, w4",
|
||||
"lsr w23, w22, w21",
|
||||
"mov w20, w5",
|
||||
"mov w21, w4",
|
||||
"lsr w22, w21, w20",
|
||||
"cset w23, hs",
|
||||
"and w20, w20, #0x1f",
|
||||
"cbz x20, #+0x4c",
|
||||
"mov w24, #0x0",
|
||||
"mov w25, #0x21",
|
||||
"sub w25, w25, w21",
|
||||
"lsl w25, w22, w25",
|
||||
"sub w25, w25, w20",
|
||||
"lsl w25, w21, w25",
|
||||
"mrs x30, nzcv",
|
||||
"cmp w21, #0x1 (1)",
|
||||
"cmp w20, #0x1 (1)",
|
||||
"csel w24, w25, w24, hi",
|
||||
"orr w23, w23, w24",
|
||||
"sub w24, w21, #0x1 (1)",
|
||||
"lsr w22, w22, w24",
|
||||
"orr w22, w22, w24",
|
||||
"sub w24, w20, #0x1 (1)",
|
||||
"lsr w21, w21, w24",
|
||||
"msr nzcv, x30",
|
||||
"rmif x22, #63, #nzCv",
|
||||
"mov w22, #0x20",
|
||||
"sub w21, w22, w21",
|
||||
"lsl x20, x20, x21",
|
||||
"orr w4, w23, w20",
|
||||
"rmif x21, #63, #nzCv",
|
||||
"mov w21, #0x20",
|
||||
"sub w20, w21, w20",
|
||||
"lsl x20, x23, x20",
|
||||
"orr w4, w22, w20",
|
||||
"eor w20, w4, w4, lsr #1",
|
||||
"rmif x20, #30, #nzcV"
|
||||
]
|
||||
},
|
||||
"rcr rax, cl": {
|
||||
"ExpectedInstructionCount": 22,
|
||||
"ExpectedInstructionCount": 23,
|
||||
"Comment": "GROUP2 0xd3 /3",
|
||||
"ExpectedArm64ASM": [
|
||||
"cset w20, hs",
|
||||
"mov x21, x5",
|
||||
"cbz x21, #+0x50",
|
||||
"lsr x22, x4, x21",
|
||||
"mov w23, #0x0",
|
||||
"mov w24, #0x41",
|
||||
"sub x24, x24, x21",
|
||||
"lsl x24, x4, x24",
|
||||
"mrs x25, nzcv",
|
||||
"cmp x21, #0x1 (1)",
|
||||
"csel x23, x24, x23, hi",
|
||||
"orr x22, x22, x23",
|
||||
"sub x23, x21, #0x1 (1)",
|
||||
"lsr x23, x4, x23",
|
||||
"msr nzcv, x25",
|
||||
"rmif x23, #63, #nzCv",
|
||||
"mov w23, #0x40",
|
||||
"sub x21, x23, x21",
|
||||
"lsl x20, x20, x21",
|
||||
"orr x4, x22, x20",
|
||||
"mov x20, x4",
|
||||
"lsr x21, x20, x5",
|
||||
"cset w22, hs",
|
||||
"and x23, x5, #0x3f",
|
||||
"cbz x23, #+0x4c",
|
||||
"mov w24, #0x0",
|
||||
"mov w25, #0x41",
|
||||
"sub x25, x25, x23",
|
||||
"lsl x25, x20, x25",
|
||||
"mrs x30, nzcv",
|
||||
"cmp x23, #0x1 (1)",
|
||||
"csel x24, x25, x24, hi",
|
||||
"orr x21, x21, x24",
|
||||
"sub x24, x23, #0x1 (1)",
|
||||
"lsr x20, x20, x24",
|
||||
"msr nzcv, x30",
|
||||
"rmif x20, #63, #nzCv",
|
||||
"mov w20, #0x40",
|
||||
"sub x20, x20, x23",
|
||||
"lsl x20, x22, x20",
|
||||
"orr x4, x21, x20",
|
||||
"eor x20, x4, x4, lsr #1",
|
||||
"rmif x20, #62, #nzcV"
|
||||
]
|
||||
|
||||
@ -1388,26 +1388,26 @@
|
||||
"ExpectedInstructionCount": 8,
|
||||
"Comment": "GROUP2 0xC1 /2",
|
||||
"ExpectedArm64ASM": [
|
||||
"cset w20, hs",
|
||||
"mov w21, w4",
|
||||
"lsl w22, w21, #2",
|
||||
"orr w22, w22, w21, lsr #31",
|
||||
"ubfx x21, x21, #30, #1",
|
||||
"lsl x21, x21, #29",
|
||||
"orr w4, w22, w20, lsl #1",
|
||||
"msr nzcv, x21"
|
||||
"mov w20, w4",
|
||||
"lsl w21, w20, #2",
|
||||
"cset w22, hs",
|
||||
"orr w21, w21, w20, lsr #31",
|
||||
"ubfx x20, x20, #30, #1",
|
||||
"lsl x20, x20, #29",
|
||||
"orr w4, w21, w22, lsl #1",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"rcl rax, 2": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "GROUP2 0xC1 /2",
|
||||
"ExpectedArm64ASM": [
|
||||
"cset w20, hs",
|
||||
"lsl x21, x4, #2",
|
||||
"orr x21, x21, x4, lsr #63",
|
||||
"lsl x20, x4, #2",
|
||||
"cset w21, hs",
|
||||
"orr x20, x20, x4, lsr #63",
|
||||
"ubfx x22, x4, #62, #1",
|
||||
"lsl x22, x22, #29",
|
||||
"orr x4, x21, x20, lsl #1",
|
||||
"orr x4, x20, x21, lsl #1",
|
||||
"msr nzcv, x22"
|
||||
]
|
||||
},
|
||||
@ -1442,26 +1442,26 @@
|
||||
"ExpectedInstructionCount": 8,
|
||||
"Comment": "GROUP2 0xC1 /3",
|
||||
"ExpectedArm64ASM": [
|
||||
"cset w20, hs",
|
||||
"mov w21, w4",
|
||||
"lsr w22, w21, #2",
|
||||
"orr w22, w22, w21, lsl #31",
|
||||
"ubfx x21, x21, #1, #1",
|
||||
"lsl x21, x21, #29",
|
||||
"orr w4, w22, w20, lsl #30",
|
||||
"msr nzcv, x21"
|
||||
"mov w20, w4",
|
||||
"lsr w21, w20, #2",
|
||||
"cset w22, hs",
|
||||
"orr w21, w21, w20, lsl #31",
|
||||
"ubfx x20, x20, #1, #1",
|
||||
"lsl x20, x20, #29",
|
||||
"orr w4, w21, w22, lsl #30",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"rcr rax, 2": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "GROUP2 0xC1 /3",
|
||||
"ExpectedArm64ASM": [
|
||||
"cset w20, hs",
|
||||
"lsr x21, x4, #2",
|
||||
"orr x21, x21, x4, lsl #63",
|
||||
"lsr x20, x4, #2",
|
||||
"cset w21, hs",
|
||||
"orr x20, x20, x4, lsl #63",
|
||||
"ubfx x22, x4, #1, #1",
|
||||
"lsl x22, x22, #29",
|
||||
"orr x4, x21, x20, lsl #62",
|
||||
"orr x4, x20, x21, lsl #62",
|
||||
"msr nzcv, x22"
|
||||
]
|
||||
},
|
||||
@ -2449,33 +2449,34 @@
|
||||
]
|
||||
},
|
||||
"rcl eax, cl": {
|
||||
"ExpectedInstructionCount": 29,
|
||||
"ExpectedInstructionCount": 30,
|
||||
"Comment": "GROUP2 0xd3 /2",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, w5",
|
||||
"cset w21, hs",
|
||||
"cbz x20, #+0x6c",
|
||||
"mov w22, w4",
|
||||
"lsl w23, w22, w20",
|
||||
"mov w21, w4",
|
||||
"lsl w22, w21, w20",
|
||||
"cset w23, hs",
|
||||
"and w20, w20, #0x1f",
|
||||
"cbz x20, #+0x64",
|
||||
"mov w24, #0x21",
|
||||
"sub w24, w24, w20",
|
||||
"lsr w24, w22, w24",
|
||||
"lsr w24, w21, w24",
|
||||
"mov w25, #0x0",
|
||||
"mrs x30, nzcv",
|
||||
"cmp w20, #0x1 (1)",
|
||||
"csel w24, w24, w25, hi",
|
||||
"orr w23, w23, w24",
|
||||
"orr w22, w22, w24",
|
||||
"mov w24, #0x20",
|
||||
"sub w24, w24, w20",
|
||||
"lsr w22, w22, w24",
|
||||
"ubfx x24, x22, #0, #1",
|
||||
"lsr w21, w21, w24",
|
||||
"ubfx x24, x21, #0, #1",
|
||||
"mov w0, w30",
|
||||
"bfi w0, w24, #29, #1",
|
||||
"mov w24, w0",
|
||||
"sub w20, w20, #0x1 (1)",
|
||||
"lsl x20, x21, x20",
|
||||
"orr w4, w23, w20",
|
||||
"eor w20, w4, w22, lsl #31",
|
||||
"lsl x20, x23, x20",
|
||||
"orr w4, w22, w20",
|
||||
"eor w20, w4, w21, lsl #31",
|
||||
"ubfx x20, x20, #31, #1",
|
||||
"mov w0, w24",
|
||||
"bfi w0, w20, #28, #1",
|
||||
@ -2484,32 +2485,33 @@
|
||||
]
|
||||
},
|
||||
"rcl rax, cl": {
|
||||
"ExpectedInstructionCount": 28,
|
||||
"ExpectedInstructionCount": 29,
|
||||
"Comment": "GROUP2 0xd3 /2",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, x5",
|
||||
"cset w21, hs",
|
||||
"cbz x20, #+0x68",
|
||||
"lsl x22, x4, x20",
|
||||
"mov w23, #0x41",
|
||||
"sub x23, x23, x20",
|
||||
"lsr x23, x4, x23",
|
||||
"mov w24, #0x0",
|
||||
"mrs x25, nzcv",
|
||||
"cmp x20, #0x1 (1)",
|
||||
"csel x23, x23, x24, hi",
|
||||
"orr x22, x22, x23",
|
||||
"mov w23, #0x40",
|
||||
"sub x23, x23, x20",
|
||||
"lsr x23, x4, x23",
|
||||
"ubfx x24, x23, #0, #1",
|
||||
"mov w0, w25",
|
||||
"mov x20, x4",
|
||||
"lsl x21, x20, x5",
|
||||
"cset w22, hs",
|
||||
"and x23, x5, #0x3f",
|
||||
"cbz x23, #+0x64",
|
||||
"mov w24, #0x41",
|
||||
"sub x24, x24, x23",
|
||||
"lsr x24, x20, x24",
|
||||
"mov w25, #0x0",
|
||||
"mrs x30, nzcv",
|
||||
"cmp x23, #0x1 (1)",
|
||||
"csel x24, x24, x25, hi",
|
||||
"orr x21, x21, x24",
|
||||
"mov w24, #0x40",
|
||||
"sub x24, x24, x23",
|
||||
"lsr x20, x20, x24",
|
||||
"ubfx x24, x20, #0, #1",
|
||||
"mov w0, w30",
|
||||
"bfi w0, w24, #29, #1",
|
||||
"mov w24, w0",
|
||||
"sub x20, x20, #0x1 (1)",
|
||||
"lsl x20, x21, x20",
|
||||
"orr x4, x22, x20",
|
||||
"eor x20, x4, x23, lsl #63",
|
||||
"sub x23, x23, #0x1 (1)",
|
||||
"lsl x22, x22, x23",
|
||||
"orr x4, x21, x22",
|
||||
"eor x20, x4, x20, lsl #63",
|
||||
"lsr x20, x20, #63",
|
||||
"mov w0, w24",
|
||||
"bfi w0, w20, #28, #1",
|
||||
@ -2547,71 +2549,71 @@
|
||||
]
|
||||
},
|
||||
"rcr eax, cl": {
|
||||
"ExpectedInstructionCount": 29,
|
||||
"ExpectedInstructionCount": 30,
|
||||
"Comment": "GROUP2 0xd3 /3",
|
||||
"ExpectedArm64ASM": [
|
||||
"cset w20, hs",
|
||||
"mov w21, w5",
|
||||
"cbz x21, #+0x6c",
|
||||
"mov w22, w4",
|
||||
"lsr w23, w22, w21",
|
||||
"mov w20, w5",
|
||||
"mov w21, w4",
|
||||
"lsr w22, w21, w20",
|
||||
"cset w23, hs",
|
||||
"and w20, w20, #0x1f",
|
||||
"cbz x20, #+0x64",
|
||||
"mov w24, #0x0",
|
||||
"mov w25, #0x21",
|
||||
"sub w25, w25, w21",
|
||||
"lsl w25, w22, w25",
|
||||
"sub w25, w25, w20",
|
||||
"lsl w25, w21, w25",
|
||||
"mrs x30, nzcv",
|
||||
"cmp w21, #0x1 (1)",
|
||||
"cmp w20, #0x1 (1)",
|
||||
"csel w24, w25, w24, hi",
|
||||
"orr w23, w23, w24",
|
||||
"sub w24, w21, #0x1 (1)",
|
||||
"lsr w22, w22, w24",
|
||||
"ubfx x22, x22, #0, #1",
|
||||
"orr w22, w22, w24",
|
||||
"sub w24, w20, #0x1 (1)",
|
||||
"lsr w21, w21, w24",
|
||||
"ubfx x21, x21, #0, #1",
|
||||
"mov w0, w30",
|
||||
"bfi w0, w22, #29, #1",
|
||||
"mov w22, w0",
|
||||
"bfi w0, w21, #29, #1",
|
||||
"mov w21, w0",
|
||||
"mov w24, #0x20",
|
||||
"sub w21, w24, w21",
|
||||
"lsl x20, x20, x21",
|
||||
"orr w4, w23, w20",
|
||||
"sub w20, w24, w20",
|
||||
"lsl x20, x23, x20",
|
||||
"orr w4, w22, w20",
|
||||
"eor w20, w4, w4, lsr #1",
|
||||
"ubfx x20, x20, #30, #1",
|
||||
"mov w0, w22",
|
||||
"mov w0, w21",
|
||||
"bfi w0, w20, #28, #1",
|
||||
"mov w20, w0",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"rcr rax, cl": {
|
||||
"ExpectedInstructionCount": 28,
|
||||
"ExpectedInstructionCount": 27,
|
||||
"Comment": "GROUP2 0xd3 /3",
|
||||
"ExpectedArm64ASM": [
|
||||
"cset w20, hs",
|
||||
"mov x21, x5",
|
||||
"cbz x21, #+0x68",
|
||||
"lsr x22, x4, x21",
|
||||
"mov w23, #0x0",
|
||||
"mov w24, #0x41",
|
||||
"sub x24, x24, x21",
|
||||
"lsl x24, x4, x24",
|
||||
"mrs x25, nzcv",
|
||||
"cmp x21, #0x1 (1)",
|
||||
"csel x23, x24, x23, hi",
|
||||
"orr x22, x22, x23",
|
||||
"sub x23, x21, #0x1 (1)",
|
||||
"lsr x23, x4, x23",
|
||||
"ubfx x23, x23, #0, #1",
|
||||
"mov w0, w25",
|
||||
"bfi w0, w23, #29, #1",
|
||||
"mov w23, w0",
|
||||
"mov w24, #0x40",
|
||||
"sub x21, x24, x21",
|
||||
"lsl x20, x20, x21",
|
||||
"orr x4, x22, x20",
|
||||
"eor x20, x4, x4, lsr #1",
|
||||
"ubfx x20, x20, #62, #1",
|
||||
"mov w0, w23",
|
||||
"bfi w0, w20, #28, #1",
|
||||
"mov x20, x4",
|
||||
"lsr x21, x20, x5",
|
||||
"cset w22, hs",
|
||||
"and x23, x5, #0x3f",
|
||||
"cbz x23, #+0x5c",
|
||||
"mov w24, #0x0",
|
||||
"mov w25, #0x41",
|
||||
"sub x25, x25, x23",
|
||||
"lsl x25, x20, x25",
|
||||
"mrs x30, nzcv",
|
||||
"cmp x23, #0x1 (1)",
|
||||
"csel x24, x25, x24, hi",
|
||||
"orr x21, x21, x24",
|
||||
"sub x24, x23, #0x1 (1)",
|
||||
"lsr x20, x20, x24",
|
||||
"ubfx x20, x20, #0, #1",
|
||||
"mov w0, w30",
|
||||
"bfi w0, w20, #29, #1",
|
||||
"mov w20, w0",
|
||||
"mov w24, #0x40",
|
||||
"sub x23, x24, x23",
|
||||
"lsl x22, x22, x23",
|
||||
"orr x4, x21, x22",
|
||||
"eor x21, x4, x4, lsr #1",
|
||||
"ubfx x21, x21, #62, #1",
|
||||
"bfi w20, w21, #28, #1",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user